STM32W108C8

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Interrupts STM32W108C8 12.1.2 Faults and switch has occurred, the STM32W108C8 triggers the CLK24M_FAIL second-level interrupt, which then triggers the NMI. 2. Watchdog low water mark: If the STM32W108C8's watchdog is active and the watchdog counter has not been reset for 1.792 seconds, the watchdog triggers the WATCHDOG_INT second level interrupt, which then triggers the NMI. Four of the exceptions in the NVIC are faults: Hard Fault, Memory Fault, Bus Fault, and Usage Fault. Of these four, three of the faults (Hard Fault, Memory Fault, and Usage Fault) are all standard ARM® Cortex-M3 exceptions. The Bus Fault, though, is derived from STM32W108C8-specific sources. The Bus Fault sources are recorded in the SCS_AFSR register. Note that it is possible for one access to set multiple SCS_AFSR bits. Also note that MPU configurations could prevent most of these bus fault accesses from occurring, with the advantage that illegal writes are made precise faults. The four bus faults are: ● WRONGSIZE - Generated by an 8-bit or 16-bit read or write of an APB peripheral register. This fault can also result from an unaligned 32-bit access. ● PROTECTED - Generated by a user mode (unprivileged) write to a system APB or AHB peripheral or protected RAM. ● RESERVED - Generated by a read or write to an address within an APB peripheral's 4-Kbyte block range, but the address is above the last physical register in that block range. Also generated by a read or write to an address above the top of RAM or Flash memory. ● MISSED - Generated by a second SCS_AFSR fault. In practice, this bit is not seen since a second fault also generates a hard fault, and the hard fault preempts the bus fault. 12.2 Event manager While the standard ARM® Cortex-M3 Nested Vectored Interrupt Controller provides toplevel interrupts into the CPU, the Event Manager provides second-level interrupts. The Event Manager takes a large variety of hardware interrupt sources from the peripherals and merges them into a smaller group of interrupts in the NVIC. Effectively, all second-level interrupts from a peripheral are "ORed" together into a single interrupt in the NVIC. In addition, the Event Manager provides missed indicators for the top-level peripheral interrupts with the register INT_MISS. 177/215 Doc ID 018587 Rev 2
STM32W108C8 Interrupts Figure 50. Peripheral interrupts block diagram interrupts into NVIC /CPU OR peripheral interrupt instance OR AND Q latch S R write 1 read INT_CFGCLR write 1 INT_CFGSET AND AND INT_periphCFG Q latch S R read read OR write 1 INT_PENDCLR Q latch S R INT_periphFLAG write 1 Q latch S R write 1 INT_PENDSET read write 1 INT_MISS source interrupt events interrupts from all peripherals The description of each peripheral's interrupt configuration and flag registers can be found in the chapters of this datasheet describing each peripheral. Given a peripheral, 'periph', the Event Manager registers (INT_periphCFG and INT_periphFLAG) follow the form: ● INT_periphCFG enables and disables second-level interrupts. Writing 1 to a bit in the INT_periphCFG register enables the second-level interrupt. Writing 0 to a bit in the INT_periphCFG register disables it. The INT_periphCFG register behaves like a mask, and is responsible for allowing the INT_periphFLAG bits to propagate into the top level NVIC interrupts. ● INT_periphFLAG indicates second-level interrupts that have occurred. Writing 1 to a bit in a INT_periphFLAG register clears the second-level interrupt. Writing 0 to any bit in the INT_periphFLAG register is ineffective. The INT_periphFLAG register is always active and may be set or cleared at any time, meaning if any second-level interrupt occurs, then the corresponding bit in the INT_periphFLAG register is set regardless of the state of INT_periphCFG. If a bit in the INT_periphCFG register is set after the corresponding bit in the INT_periphFLAG register is set then the second-level interrupt propagates into the top level interrupts. The interrupt flags (signals) from the second-level interrupts into the top-level interrupts are level-sensitive. If a top-level NVIC interrupt is driven by a second-level EM interrupt, then the top-level NVIC interrupt cannot be cleared until all second-level EM interrupts are cleared. The INT_periphFLAG register bits are designed to remain set if the second-level interrupt event re-occurs at the same moment as the INT_periphFLAG register bit is being cleared. This ensures the re-occurring second-level interrupt event is not missed. If another enabled second-level interrupt event of the same type occurs before the first interrupt event is cleared, the second interrupt event is lost because no counting or queuing is used. However, this condition is detected and stored in the top-level INT_MISS register to Doc ID 018587 Rev 2 178/215
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STM32W108C8 High-performance, IEEE
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STM32W108C8 Software reset . . . .
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STM32W108C8 9 Serial interfaces . .
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STM32W108C8 10.1.4 Capture/compare
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STM32W108C8 12.1.1 Non-maskable int
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STM32W108C8 Description 1 Descripti
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STM32W108C8 Description 1.2 Overvie
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STM32W108C8 Documentation conventio
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STM32W108C8 Pinout and pin descript
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STM32W108C8 Embedded memory 4 Embed
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STM32W108C8 Embedded memory 6. Seri
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STM32W108C8 Radio frequency module
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STM32W108C8 System modules 6 System
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STM32W108C8 System modules 6.2 Rese
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STM32W108C8 System modules ● PRES
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STM32W108C8 System modules Figure 5
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STM32W108C8 System modules In addit
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STM32W108C8 System modules 6.4.3 Ev
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STM32W108C8 System modules Table 11
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STM32W108C8 System modules Bits [15
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STM32W108C8 System modules debugger
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STM32W108C8 Serial interfaces Bit 2
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STM32W108C8 General-purpose timers
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STM32W108C8

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