STM32W108C8

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Interrupts STM32W108C8 Table 122. NVIC exception table Exception Position Description - 0 Stack top is loaded from first entry of vector table on reset. Reset 1 NMI 2 Hard Fault 3 Memory Fault 4 Bus Fault 5 Usage Fault 6 - 7-10 Reserved. Invoked on power up and warm reset. On first instruction, drops to lowest priority (Thread mode). Asynchronous. Cannot be stopped or preempted by any exception but reset. Asynchronous. All classes of fault, when the fault cannot activate because of priority or the Configurable Fault handler has been disabled. Synchronous. MPU mismatch, including access violation and no match. Synchronous. Pre-fetch, memory access, and other address/memory-related faults. Synchronous when precise and asynchronous when imprecise. Usage fault, such as 'undefined instruction executed' or 'illegal state transition attempt'. Synchronous. SVCall 11 System service call with SVC instruction. Synchronous. Debug Monitor 12 - 13 Reserved. PendSV 14 Debug monitor, when not halting. Synchronous, but only active when enabled. It does not activate if lower priority than the current activation. Pendable request for system service. Asynchronous and only pended by software. SysTick 15 System tick timer has fired. Asynchronous. Timer 1 16 Timer 1 peripheral interrupt. Timer 2 17 Timer 2 peripheral interrupt. Management 18 Management peripheral interrupt. Baseband 19 Baseband peripheral interrupt. Sleep Timer 20 Sleep Timer peripheral interrupt. Serial Controller 1 21 Serial Controller 1 peripheral interrupt. Serial Controller 2 22 Serial Controller 2 peripheral interrupt. Security 23 Security peripheral interrupt. MAC Timer 24 MAC Timer peripheral interrupt. MAC Transmit 25 MAC Transmit peripheral interrupt. MAC Receive 26 MAC Receive peripheral interrupt. ADC 27 ADC peripheral interrupt. IRQA 28 IRQA peripheral interrupt. IRQB 29 IRQB peripheral interrupt. IRQC 30 IRQC peripheral interrupt. 175/215 Doc ID 018587 Rev 2
STM32W108C8 Interrupts Table 122. NVIC exception table (continued) Exception Position Description IRQD 31 IRQD peripheral interrupt. Debug 32 Debug peripheral interrupt. The NVIC also contains a software-configurable interrupt prioritization mechanism. The Reset, NMI, and Hard Fault exceptions, in that order, are always the highest priority, and are not software-configurable. All other exceptions can be assigned a 5-bit priority number, with low values representing higher priority. If any exceptions have the same softwareconfigurable priority, then the NVIC uses the hardware-defined priority. The hardwaredefined priority number is the same as the position of the exception in the exception table. For example, if IRQA and IRQB both fire at the same time and have the same softwaredefined priority, the NVIC handles IRQA, with priority number 28, first because it has a higher hardware priority than IRQB with priority number 29. The top level interrupts are controlled through five ARM® Cortex-M3 NVIC registers: INT_CFGSET, INT_CFGCLR, INT_PENDSET, INT_PENDCLR, and INT_ACTIVE. Writing 0 into any bit in any of these five register is ineffectual. ● INT_CFGSET - Writing 1 to a bit in INT_CFGSET enables that top level interrupt. ● ● ● INT_CFGCLR - Writing 1 to a bit in INT_CFGCLR disables that top level interrupt. INT_PENDSET - Writing 1 to a bit in INT_PENDSET triggers that top level interrupt. INT_PENDCLR - Writing 1 to a bit in INT_PENDCLR clear that top level interrupt. ● INT_ACTIVE cannot be written to and is used for indicating which interrupts are currently active. INT_PENDSET and INT_PENDCLR set and clear a simple latch; INT_CFGSET and INT_CFGCLR set and clear a mask on the output of the latch. Interrupts may be pended and cleared at any time, but any pended interrupt will not be taken unless the corresponding mask (INT_CFGSET) is set, which allows that interrupt to propagate. If an INT_CFGSET bit is set and the corresponding INT_PENDSET bit is set, then the interrupt will propagate and be taken. If INT_CFGSET is set after INT_PENDSET is set, then the interrupt will also propagate and be taken. Interrupt flags (signals) from the top level interrupts are levelsensitive. The second-level interrupt registers, which provide control of the second-level Event Manager peripheral interrupts, are described in Section 12.2: Event manager. For further information on the NVIC and Cortex-M3 exceptions, refer to the ARM® Cortex- M3 Technical Reference Manual and the ARM ARMv7-M Architecture Reference Manual. 12.1.1 Non-maskable interrupt (NMI) The non-maskable interrupt (NMI) is a special case. Despite being one of the 10 standard ARM® Cortex-M3 NVIC interrupts, it is sourced from the Event Manager like a peripheral interrupt. The NMI has two second-level sources; failure of the 24 MHz crystal and watchdog low water mark. 1. Failure of the 24 MHz crystal: If the STM32W108C8's main clock, SCLK, is operating from the 24 MHz crystal and the crystal fails, the STM32W108C8 detects the failure and automatically switch to the internal 12 MHz RC clock. When this failure detection Doc ID 018587 Rev 2 176/215
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STM32W108C8 High-performance, IEEE
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STM32W108C8

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