STM32W108C8

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Analog-to-digital converter STM32W108C8 11.3.10 ADC interrupt flag register (INT_ADCFLAG) Table 120. Address offset: 0xA810 Reset value: 0x0000 0000 ADC interrupt flag register (INT_ADCFLAG) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved INT_A DCOV F INT_A DCSAT INT_A DCUL DFULL INT_A DCUL DHALF ST Reserved rw rw rw rw rw Bit 4 INT_ADCOVF: DMA buffer overflow interrupt pending. Bit 3 INT_ADCSAT: Gain correction saturation interrupt pending. Bit 2 INT_ADCULDFULL: DMA buffer full interrupt pending. Bit 1 INT_ADCULDHALF: DMA buffer half full interrupt pending. Bit 0 Reserved: this bit should always be set to 1. 11.3.11 ADC interrupt configuration register (INT_ADCCFG) Table 121. Address offset: 0xA850 Reset value: 0x0000 0000 ADC interrupt configuration register (INT_ADCCFG) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved INT_A DCOV F INT_A DCSAT INT_A DCUL DFULL INT_A DCUL DHALF rw rw rw rw ST Reserved Bit 4 INT_ADCOVF: DMA buffer overflow interrupt enable. Bit 3 INT_ADCSAT: Gain correction saturation interrupt enable. Bit 2 INT_ADCULDFULL: DMA buffer full interrupt enable. Bit 1 INT_ADCULDHALF: DMA buffer half full interrupt enable. Bit 0 ST Reserved: this bit must always be set to 0. 173/215 Doc ID 018587 Rev 2
STM32W108C8 Interrupts 12 Interrupts The STM32W108C8's interrupt system is composed of two parts: a standard ARM® Cortex- M3 Nested Vectored Interrupt Controller (NVIC) that provides top level interrupts, and an Event Manager (EM) that provides second level interrupts. The NVIC and EM provide a simple hierarchy. All second level interrupts from the EM feed into top level interrupts in the NVIC. This two-level hierarchy allows for both fine granular control of interrupt sources and coarse granular control over entire peripherals, while allowing peripherals to have their own interrupt vector. The Section 12.3: Nested vectored interrupt controller (NVIC) interrupts provides a description of the NVIC and an overview of the exception table (ARM nomenclature refers to interrupts as exceptions) and Section 12.2: Event manager provides a more detailed description of the Event Manager including a table of all top-level peripheral interrupts and their second-level interrupt sources. In practice, top-level peripheral interrupts are only used to enable or disable interrupts for an entire peripheral. Second-level interrupts originate from hardware sources, and therefore are the main focus of applications using interrupts. 12.1 Nested vectored interrupt controller (NVIC) The ARM® Cortex-M3 Nested Vectored Interrupt Controller (NVIC) facilitates low-latency exception and interrupt handling. The NVIC and the processor core interface are closely coupled, which enables low-latency interrupt processing and efficient processing of late arriving interrupts. The NVIC also maintains knowledge of the stacked (nested) interrupts to enable tail-chaining of interrupts. The ARM® Cortex-M3 NVIC contains 10 standard interrupts that are related to chip and CPU operation and management. In addition to the 10 standard interrupts, it contains 17 individually vectored peripheral interrupts specific to the STM32W108C8. The NVIC defines a list of exceptions. These exceptions include not only traditional peripheral interrupts, but also more specialized events such as faults and CPU reset. In the ARM® Cortex-M3 NVIC, a CPU reset event is considered an exception of the highest priority, and the stack pointer is loaded from the first position in the NVIC exception table. The NVIC exception table defines all exceptions and their position, including peripheral interrupts. The position of each exception is important since it directly translates to the location of a 32-bit interrupt vector for each interrupt, and defines the hardware priority of exceptions. Each exception in the table is a 32-bit address that is loaded into the program counter when that exception occurs. Table 122 lists the entire exception table. Exceptions 0 (stack pointer) through 15 (SysTick) are part of the standard ARM® Cortex-M3 NVIC, while exceptions 16 (Timer 1) through 32 (Debug) are the peripheral interrupts specific to the STM32W108C8 peripherals. The peripheral interrupts are listed in greater detail in Table 123. Doc ID 018587 Rev 2 174/215
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STM32W108C8 High-performance, IEEE
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STM32W108C8 Software reset . . . .
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STM32W108C8 9 Serial interfaces . .
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STM32W108C8 10.1.4 Capture/compare
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STM32W108C8 12.1.1 Non-maskable int
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STM32W108C8 Description 1 Descripti
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STM32W108C8 Description 1.2 Overvie
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STM32W108C8 Documentation conventio
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STM32W108C8 Pinout and pin descript
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STM32W108C8 Embedded memory 4 Embed
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STM32W108C8 Radio frequency module
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STM32W108C8 System modules 6 System
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STM32W108C8 System modules 6.2 Rese
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STM32W108C8 System modules ● PRES
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STM32W108C8 System modules Figure 5
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STM32W108C8 System modules In addit
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STM32W108C8 System modules 6.4.3 Ev
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STM32W108C8 System modules Table 11
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STM32W108C8 System modules Bits [15
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STM32W108C8 System modules Bit 1 SL
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STM32W108C8 System modules debugger
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STM32W108C8 Integrated voltage regu
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STM32W108C8 General-purpose input/o
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STM32W108C8 Serial interfaces 9.13
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STM32W108C8 Serial interfaces Bit 2
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STM32W108C8 General-purpose timers
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STM32W108C8

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