STM32W108C8

STM32W108C8
Analog-to-digital converter
11.3.4 ADC DMA configuration register (ADC_DMACFG)
Table 114.
Address offset: 0xD010
Reset value: 0x0000 0000
ADC DMA configuration register (ADC_DMACFG)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
ADC_
DMAR
ST
Reserved
ADC_
DMAA
UTOW
RAP
ADC_
DMAL
OAD
w rw rw
Bit 4 ADC_DMARST: Write 1 to reset the ADC DMA. This bit auto-clears.
Bit 1 ADC_DMAAUTOWRAP: Selects DMA mode.
0: Linear mode, the DMA stops when the buffer is full.
1: Auto-wrap mode, the DMA output wraps back to the start when the buffer is full.
Bit 0 ADC_DMALOAD: Loads the DMA buffer.
Write 1 to start DMA (writing 0 has no effect). Cleared when DMA starts or is reset.
11.3.5 ADC DMA status register (ADC_DMASTAT)
Table 115.
Address offset: 0xD014
Reset value: 0x0000 0000
ADC DMA status register (ADC_DMASTAT)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
ADC_D
MAOVF
r
ADC_D
MAACT
r
Bit 1 ADC_DMAOVF: DMA overflow: occurs when an ADC result is ready and the DMA is not active.
Cleared by DMA reset.
Bit 0 ADC_DMAACT: DMA status: reads 1 if DMA is active.
Doc ID 018587 Rev 2 170/215