STM32W108C8

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Analog-to-digital converter STM32W108C8 Table 109. ADC sample times (continued) ADC_PERIOD Sample clocks Sample time (µs) Sample frequency (kHz) 1 MHz clock 6 MHz clock 1 MHz clock 6 MHz clock Significant bits 6 2048 2048 341 0.488 2.93 11 7 4096 4096 682 0.244 1.47 12 Note: ADC sample timing is the same whether the STM32W108C8 is using the 24 MHz crystal oscillator or the 12 MHz high-speed RC oscillator. This facilitates using the ADC soon after the CPU wakes from deep sleep, before switching to the crystal oscillator. 11.1.7 Operation Setting the ADC_EN bit in the ADC_CFG register enables the ADC; once enabled, it performs conversions continuously until it is disabled. If the ADC had previously been disabled, a 21 µs analog startup delay is imposed before the ADC starts conversions. The delay timing is performed in hardware and is simply added to the time until the first conversion result is output. When the ADC is first enabled, and or if any change is made to ADC_CFG after it is enabled, the time until a result is output is double the normal sample time. This is because the ADC’s internal design requires it to discard the first conversion after startup or a configuration change. This is done automatically and is hidden from software except for the longer timing. Switching the processor clock between the RC and crystal oscillator also causes the ADC to go through this startup cycle. If the ADC was newly enabled, the analog delay time is added to the doubled sample time. If the DMA is running when ADC_CFG is modified, the DMA does not stop, so the DMA buffer may contain conversion results from both the old and new configurations. The following procedure illustrates a simple polled method of using the ADC. After completing the procedure, the latest conversion results is available in the location written to by the DMA. This assumes that any GPIOs and the voltage reference have already been configured. 1. Allocate a 16-bit signed variable, for example analogData, to receive the ADC output. (Make sure that analogData is half-word aligned – that is, at an even address.) 2. Disable all ADC interrupts – write 0 to INT_ADCCFG. 3. Set up the DMA to output conversion results to the variable, analogData. Reset the DMA – set the ADC_DMARST bit in ADC_DMACFG. Define a one sample buffer – write analogData’s address to ADC_DMABEG, set ADC_DMASIZE to 1. 4. Write the desired offset and gain correction values to the ADC_OFFSET and ADC_GAIN registers. 5. Start the ADC and the DMA. Write the desired conversion configuration, with the ADC_EN bit set, to ADC_CFG. Clear the ADC buffer full flag – write INT_ADCULDFULL to INT_ADCFLAG. Start the DMA in auto wrap mode – set the ADC_DMAAUTOWRAP and ADC_DMALOAD bits in ADC_DMACFG. 6. Wait until the INT_ADCULDFULL bit is set in INT_ADCFLAG, then read the result from analogData. 165/215 Doc ID 018587 Rev 2
STM32W108C8 Analog-to-digital converter To convert multiple inputs using this approach, repeat Steps 4 through 6, loading the desired input configurations to ADC_CFG in Step 5. If the inputs can use the same offset/gain correction, just repeat Steps 5 and 6. 11.1.8 Calibration Sampling of internal connections GND, VREF/2, and VREF allow for offset and gain calibration of the ADC in applications where absolute accuracy is important. Offset error is calculated from the minimum input and gain error is calculated from the full scale input range. Correction using VREF is recommended because VREF is calibrated by the ST software against VDD_PADSA. The VDD_PADSA regulator is factory-trimmed to 1.80 V ± 20 mV. If better absolute accuracy is required, the ADC can be configured to use an external reference. The ADC calibrates as a single-ended measurement. Differential signals require correction of both their inputs. Table 110 shows the equations used to calculate the gain and offset correction values. Table 110. ADC gain and offset correction equations Calibration Correction value Gain, buffer disabled Gain, buffer enabled Offset, buffer disabled (after applying gain correction) Offset, buffer enabled (after applying gain correction) Equation notes ● ● ● ● ● All N are 16-bit two’s complement numbers. N GND is a sampling of ground. Due to the ADC's internal design, VGND does not yield the minimum two’s complement value 0x8000 as the conversion result. Instead, VGND yields a two’s complement value close to 0xE000 when the input buffer is not selected. VGND cannot be measured when the input buffer is enabled because it is outside the buffer’s input range. N VREF is a sampling of VREF. Due to the ADC's internal design, VREF does not yield the maximum positive two’s complement 0x7FFF as the conversion result. Instead, VREF yields a two’s complement value close to 0x2000 when the input buffer is not selected and yields a two’s complement value close to 0xF000 when the input buffer is selected. N VREF/2 is a sampling of VREF/2. VREF/2 yields a two’s complement value close to 0x0000 when the input buffer is not selected, and yields a two’s complement value close to 0xE800 when the input buffer is selected. Offset correction is affected by the gain correction value. Offset correction is calculated after gain correction has been applied. Doc ID 018587 Rev 2 166/215
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STM32W108C8 High-performance, IEEE
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STM32W108C8 Software reset . . . .
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STM32W108C8 9 Serial interfaces . .
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STM32W108C8 10.1.4 Capture/compare
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STM32W108C8 12.1.1 Non-maskable int
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STM32W108C8 Description 1 Descripti
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STM32W108C8 Radio frequency module
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STM32W108C8 General-purpose timers
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STM32W108C8 General-purpose timers
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STM32W108C8

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