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<strong>STM32W108C8</strong><br />
Analog-to-digital converter<br />
Table 108.<br />
Typical ADC input configurations (continued)<br />
ADC P input ADC N input ADC_MUXP ADC_MUXN Purpose<br />
ADC5 ADC4 5 4 Differential<br />
GND VREF/2 8 9 Calibration<br />
VREF VREF/2 10 9 Calibration<br />
VDD_PADSA/2 VREF/2 11 9 Calibration<br />
Input range<br />
ADC inputs can be routed through input buffers to expand the input voltage range. The input<br />
buffers have a fixed 0.25 gain and the converted data is scaled by that factor.<br />
With the input buffers disabled the single-ended input range is 0 to VREF and the differential<br />
input range is -VREF to +VREF. With the input buffers enabled the single-ended range is 0<br />
to VDD_PADS and the differential range is -VDD_PADS to +VDD_PADS.<br />
The input buffers are enabled for the ADC P and N inputs by setting the ADC_HVSELP and<br />
ADC_HVSELN bits respectively, in the ADC_CFG register. The ADC accuracy is reduced<br />
when the input buffer is selected.<br />
Sample time<br />
ADC sample time is programmed by selecting the sampling clock and the clocks per<br />
sample.<br />
● The sampling clock may be either 1 MHz or 6 MHz. If the ADC_1MHZCLK bit in the<br />
ADC_CFG register is clear, the 6 MHz clock is used; if it is set, the 1 MHz clock is<br />
selected. The 6 MHz sample clock offers faster conversion times but the ADC<br />
resolution is lower than that achieved with the 1 MHz clock.<br />
● The number of clocks per sample is determined by the ADC_PERIOD bits in the<br />
ADC_CFG register. ADC_PERIOD values select from 32 to 4096 sampling clocks in<br />
powers of two. Longer sample times produce more significant bits. Regardless of the<br />
sample time, converted samples are always 16-bits in size with the significant bits leftaligned<br />
within the value.<br />
Table 109 shows the options for ADC sample times and the significant bits in the conversion<br />
results.<br />
Table 109.<br />
ADC sample times<br />
ADC_PERIOD Sample<br />
clocks<br />
Sample time (µs)<br />
Sample frequency (kHz)<br />
1 MHz clock 6 MHz clock 1 MHz clock 6 MHz clock<br />
Significant<br />
bits<br />
0 32 32 5.33 31.3 188 5<br />
1 64 64 10.7 15.6 93.8 6<br />
2 128 128 21.3 7.81 46.9 7<br />
3 256 256 42.7 3.91 23.4 8<br />
4 512 512 85.3 1.95 11.7 9<br />
5 1024 1024 170 0.977 5.86 10<br />
Doc ID 018587 Rev 2 164/215