STM32W108C8

STM32W108C8
General-purpose timers
Bit 3 TIM_ORRSVD
Reserved: this bit must always be set to 0.
Bit 2 TIM_CLKMSKEN
Enables TIM2MSK when TIM2CLK is selected as the external trigger: 0 = TIM2MSK not used,
1 = TIM2CLK is ANDed with the TIM2MSK input.
Bits [1:0] TIM1_EXTRIGSEL
Selects the external trigger used in external clock mode 2: 0 = PCLK, 1 = calibrated 1 kHz
clock, 2 = 32 kHz reference clock (if available), 3 = TIM2CLK pin.
10.3.17 Timer x interrupt configuration register (INT_TIMxCFG)
Table 103.
Address offset: 0xA840 (TIM1) and 0xA844 (TIM2)
Reset value: 0x0000 0000
Timer x interrupt configuration register (INT_TIMxCFG)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
INT_TI
MTIF
Reserv
ed
INT_T
IMCC
4IF
INT_TI
MCC3I
F
INT_TI
MCC2I
F
INT_TI
MCC1I
F
INT_TI
MUIF
rw rw rw rw rw rw
Bit 6 INT_TIMTIF: Trigger interrupt enable.
Bit 4 INT_TIMCC4IF: Capture or compare 4 interrupt enable.
Bit 3 INT_TIMCC3IF: Capture or compare 3 interrupt enable.
Bit 2 INT_TIMCC2IF: Capture or compare 2 interrupt enable.
Bit 1 INT_TIMCC1IF: Capture or compare 1 interrupt enable.
Bit 0 INT_TIMUIF: Update interrupt enable.
10.3.18 Timer x interrupt flag register (INT_TIMxFLAG)
Table 104.
Address offset: 0xA800 (TIM1) and 0xA804 (TIM2)
Reset value: 0x0000 0000
Timer x interrupt flag register (INT_TIMxFLAG)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
INT_T INT_TI INT_TI INT_TI
INT_TI
INT_TI
INT_TIMRSVD
IMCC
MTIF Reserv
MCC3I MCC2I MCC1I
MUIF
Reserved
ed
4IF F F F
r rw rw rw rw rw rw
Doc ID 018587 Rev 2 158/215