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<strong>STM32W108C8</strong><br />
General-purpose timers<br />
Bit 5 TIM_CC2P<br />
Refer to the CC4P description above.<br />
Bit 4 TIM_CC2E<br />
Refer to the CC43 description above.<br />
Bit 1 TIM_CC1P<br />
Refer to the CC4P description above.<br />
Bit 0 TIM_CC1E<br />
Refer to the CC4E description above.<br />
10.3.8 Timer x counter register (TIMx_CNT)<br />
Table 94.<br />
Address offset: 0xE024 (TIM1) and 0xF024 (TIM2)<br />
Reset value: 0x0000 0000<br />
Timer x counter register (TIMx_CNT)<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16<br />
Reserved<br />
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />
TIM_CNT<br />
rw<br />
Bits [15:0] TIM_CNT: Counter value<br />
10.3.9 Timer x prescaler register (TIMx_PSC)<br />
Table 95.<br />
Address offset: 0xE028 (TIM1) and 0xF028 (TIM2)<br />
Reset value: 0x0000 0000<br />
Timer x prescaler register (TIMx_PSC)<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16<br />
Reserved<br />
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />
Reserved<br />
TIM_PSC<br />
rw<br />
Bits [3:0] TIM_PSC: Prescaler value<br />
The prescaler divides the internal timer clock frequency. The counter clock frequency CK_CNT<br />
is equal to fCK_PSC / (2 ^ TIM_PSC). Clock division factors can range from 1 through 32768.<br />
The division factor is loaded into the shadow prescaler register at each update event (including<br />
when the counter is cleared through TIM_UG bit of TMR1_EGR register or through the trigger<br />
controller when configured in reset mode).<br />
Doc ID 018587 Rev 2 154/215
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