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General-purpose timers<br />
<strong>STM32W108C8</strong><br />
Bit 10 TIM_OC2FE: Output Compare 2 Fast Enable. (Applies only if TIM_CC2S = 0)<br />
This bit speeds the effect of an event on the trigger in input on the OC2 output.<br />
0: OC2 behaves normally depending on the counter and TIM_CCR2 values even when the<br />
trigger is ON. The minimum delay to activate OC2 when an edge occurs on the trigger input is 5<br />
clock cycles.<br />
1: An active edge on the trigger input acts like a compare match on the OC2 output. OC2 is set<br />
to the compare level independently from the result of the comparison. Delay to sample the<br />
trigger input and to activate OC2 output is reduced to 3 clock cycles. TIM_OC2FE acts only if<br />
the channel is configured in PWM 1 or PWM 2 mode.<br />
Bits [15:12] TIM_IC2F: Input Capture 1 Filter. (Applies only if TIM_CC2S > 0)<br />
This defines the frequency used to sample the TI2 input, Fsampling, and the length of the<br />
digital filter applied to TI2. The digital filter requires N consecutive samples in the same state<br />
before being output.<br />
0000: Fsampling=PCLK, no filtering. 1000: Fsampling=PCLK/8, N=6.<br />
0001: Fsampling=PCLK, N=2. 1001: Fsampling=PCLK/8, N=8.<br />
0010: Fsampling=PCLK, N=4. 1010: Fsampling=PCLK/16, N=5.<br />
0011: Fsampling=PCLK, N=8. 1011: Fsampling=PCLK/16, N=6.<br />
0100: Fsampling=PCLK/2, N=6. 1100: Fsampling=PCLK/16, N=8.<br />
0101: Fsampling=PCLK/2, N=8. 1101: Fsampling=PCLK/32, N=5.<br />
0110: Fsampling=PCLK/4, N=6. 1110: Fsampling=PCLK/32, N=6.<br />
0111: Fsampling=PCLK/4, N=8. 1111: Fsampling=PCLK/32, N=8.<br />
Note: PCLK is 12 MHz when using the 24 MHz crystal oscillator, and 6 MHz using the 12 MHz<br />
RC oscillator.<br />
Bits [11:10] TIM_IC2PSC: Input Capture 1 Prescaler. (Applies only if TIM_CC2S > 0)<br />
00: No prescaling, capture each time an edge is detected on the capture input.<br />
01: Capture once every 2 events.<br />
10: Capture once every 4 events.<br />
11: Capture once every 6 events.<br />
Bits [9:8] TIM_CC2S: Capture / Compare 1 Selection<br />
This configures the channel as an output or an input. If an input, it selects the input source.<br />
00: Channel is an output.<br />
01: Channel is an input and is mapped to TI2.<br />
10: Channel is an input and is mapped to TI1.<br />
11: Channel is an input and is mapped to TRGI. This mode requires an internal trigger input<br />
selected by the TIM_TS bit in the TIMx_SMCR register.<br />
Note: TIM_CC2S may be written only when the channel is off (TIM_CC2E = 0 in the<br />
TIMx_CCER register).<br />
Bits [6:4] TIM_OC1M: Output Compare 1 Mode. (Applies only if TIM_CC1S = 0)<br />
See TIM_OC2M description above.<br />
Bit 3 TIM_OC1BE: Output Compare 1 Buffer Enable. (Applies only if TIM_CC1S = 0)<br />
See TIM_OC2BE description above.<br />
Bit 2 TIM_OC1FE: Output Compare 1 Fast Enable. (Applies only if TIM_CC1S = 0)<br />
See TIM_OC2FE description above.<br />
Bits [7:4] TIM_IC1F: Input Capture 1 Filter. (Applies only if TIM_CC1S > 0)<br />
See TIM_IC2F description above.<br />
Bits [3:2] TIM_IC1PSC: Input Capture 1 Prescaler. (Applies only if TIM_CC1S > 0)<br />
See TIM_IC2PSC description above.<br />
149/215 Doc ID 018587 Rev 2