STM32W108C8

General-purpose timers
STM32W108C8
Bit 14 TIM_ECE: External Clock Enable
This bit enables external clock mode 2.
0: External clock mode 2 disabled.
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF
signal.
Note: Setting the TIM_ECE bit has the same effect as selecting external clock mode 1 with
TRGI connected to ETRF (TIM_SMS=111 and TIM_TS=111).
It is possible to use this mode simultaneously with the following slave modes: reset
mode, gated mode and trigger mode. TRGI must not be connected to ETRF in this case
(the TIM_TS bits must not be 111).
If external clock mode 1 and external clock mode 2 are enabled at the same time, the
external clock input will be ETRF.
Bits [13:12] TIM_ETPS: External Trigger Prescaler
External trigger signal ETRP frequency must be at most 1/4 of CK frequency. A prescaler can
be enabled to reduce ETRP frequency. It is useful with fast external clocks.
00: ETRP prescaler off.
01: Divide ETRP frequency by 2.
10: Divide ETRP frequency by 4.
11: Divide ETRP frequency by 8.
Bits [11:8] TIM_ETF: External Trigger Filter
This defines the frequency used to sample the ETRP signal, f Sampling , and the length of the
digital filter applied to ETRP. The digital filter is made of an event counter in which N events are
needed to validate a transition on the output:
0000: f Sampling = PCLK, no filtering. 1111: f Sampling = PCLK/32, N=8.
0001: f Sampling = PCLK, N=2. 1110: f Sampling = PCLK/32, N=6.
0010: f Sampling = PCLK, N=4. 1101: f Sampling = PCLK/32, N=5.
0011: f Sampling = PCLK, N=8. 1100: f Sampling = PCLK/16, N=8.
0100: f Sampling = PCLK/2, N=6. 1011: f Sampling = PCLK/16, N=6.
0101: f Sampling = PCLK/2, N=8. 1010: f Sampling = PCLK/16, N=5.
0110: f Sampling = PCLK/4, N=6. 1001: f Sampling = PCLK/8, N=8.
0111: f Sampling = PCLK/4, N=8. 1000: f Sampling = PCLK/8, N=6.
Note: PCLK is 12 MHz when the STM32W108C8 is using the 24 MHz crystal oscillator, and 6
MHz if using the 12 MHz RC oscillator.
Bit 7 TIM_MSM: Master/Slave Mode
0: No action.
1: The effect of an event on the trigger input (TRGI) is delayed to allow exact synchronization
between the current timer and the slave (through TRGO). It is useful for synchronizing timers
on a single external event.
Bits [6:4] TIM_TS: Trigger Selection
This bit field selects the trigger input used to synchronize the counter.
000 : Internal Trigger 0 (ITR0).
100 : TI1 Edge Detector (TI1F_ED).
101 : Filtered Timer Input 1 (TI1FP1).
110 : Filtered Timer Input 2 (TI2FP2).
111 : External Trigger input (ETRF).
Note: These bits must be changed only when they are not used (when TIM_SMS=000) to
avoid detecting spurious edges during the transition.
145/215 Doc ID 018587 Rev 2