STM32W108C8

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General-purpose timers <strong>STM32W108C8</strong> Table 86. Timer signal descriptions (continued) Signal Internal/external Description ICyPS ITR0 OCy OCyREF PCLK Internal Internal External Internal External Input capture signal after filtering, edge detection and prescaling: input to the capture register. Internal trigger input: connected to the other timer's output, TRGO. Output compare: TIMxCy when used as an output. Same as OCyREF but includes possible polarity inversion. Output compare reference: always active high, but may be inverted to produce OCy. Peripheral clock connects to CK_INT and used to clock input filtering. Its frequency is 12MHz if using the 24MHz crystal oscillator and 6Mhz if using the 12MHz RC oscillator. TIy Internal Timer input: TIMxCy when used as a timer input. TIyFPy Internal Timer input after filtering and polarity selection. TIMxCy Internal Timer channel at a GPIO pin: can be a capture input (ICy) or a compare output (OCy). TIMxCLK External Clock input (if selected) to the external trigger signal (ETR). TIMxMSK External Clock mask (if enabled) AND'ed with the other timer's TIMxCLK signal. TRGI Internal Trigger input for slave mode controller. 10.2 Interrupts Each timer has its own ARM® Cortex-M3 vectored interrupt with programmable priority. Writing 1 to the INT_TIMx bit in the INT_CFGSET register enables the TIMx interrupt, and writing 1 to the INT_TIMx bit in the INT_CFGCLR register disables it. Section 12: Interrupts on page 174 describes the interrupt system in detail. Several kinds of timer events can generate a timer interrupt, and each has a status flag in the INT_TIMxFLAG register to identify the reason(s) for the interrupt: ● INT_TIMTIF - set by a rising edge on an external trigger, either edge in gated mode ● INT_TIMCCRyIF -set by a channel y input capture or output compare event ● INT_TIMUIF - set by an update event Clear bits in INT_TIMxFLAG by writing a 1 to their bit position. When a channel is in capture mode, reading the TIMx_CCRy register will also clear the INT_TIMCCRyIF bit. The INT_TIMxCFG register controls whether or not the INT_TIMxFLAG bits actually request an ARM® Cortex-M3 timer interrupt. Only the events whose bits are set to 1 in INT_TIMxCFG can do so. If an input capture or output compare event occurs and its INT_TIMMISSCCyIF is already set, the corresponding capture/compare missed flag is set in the INT_TMRxMISS register. Clear a bit in the INT_TMRxMISS register by writing a 1 to it. 141/215 Doc ID 018587 Rev 2
<strong>STM32W108C8</strong> General-purpose timers 10.3 General-purpose timer (1 and 2) registers 10.3.1 Timer x control register 1 (TIMx_CR1) Address offset: 0xE000 (TIM1) and 0xF000 (TIM2) Reset value: 0x0000 0000 Table 87. Timer x control register 1 (TIMx_CR1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TIM_A RBE TIM_CMS TIM_D IR TIM_O PM TIM_U RS TIM_U DIS TIM_C EN rw rw rw rw rw rw rw Bit 7 TIM_ARBE: Auto-Reload Buffer Enable 0: TIMx_ARR register is not buffered. 1: TIMx_ARR register is buffered. Bits [6:5] TIM_CMS: Center-aligned Mode Selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (TIM_DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of configured output channels (TIM_CCyS=00 in TIMx_CCMRy register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of configured output channels (TIM_CCyS=00 in TIMx_CCMRy register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of configured output channels (TIM_CCyS=00 in TIMx_CCMRy register) are set both when the counter is counting up or down. Note: Software may not switch from edge-aligned mode to center-aligned mode when the counter is enabled (TIM_CEN=1). Bit 4 TIM_DIR: Direction 0: Counter used as up-counter. 1: Counter used as down-counter. Bit 3 TIM_OPM: One Pulse Mode 0: Counter does not stop counting at the next update event. 1: Counter stops counting at the next update event (and clears the bit TIM_CEN). Bit 2 TIM_URS: Update Request Source 0: When enabled, update interrupt requests are sent as soon as registers are updated (counter overflow/underflow, setting the TIM_UG bit, or update generation through the slave mode controller). 1: When enabled, update interrupt requests are sent only when the counter reaches overflow or underflow. Doc ID 018587 Rev 2 142/215
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STM32W108C8 High-performance, IEEE
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STM32W108C8 Software reset . . . .
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STM32W108C8 9 Serial interfaces . .
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STM32W108C8 10.1.4 Capture/compare
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STM32W108C8 12.1.1 Non-maskable int
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STM32W108C8 Description 1 Descripti
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STM32W108C8 Documentation conventio
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STM32W108C8 Pinout and pin descript
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STM32W108C8 Radio frequency module
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STM32W108C8 System modules ● PRES
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STM32W108C8 Serial interfaces 9 Ser
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STM32W108C8 Index of registers TIMx
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STM32W108C8

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