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<strong>STM32W108C8</strong><br />
General-purpose timers<br />
Note:<br />
● Configure the Timer 1 in master/slave mode by writing TIM_MSM = 1 (TIM1_SMCR<br />
register).<br />
● Configure Timer 2 to get the input trigger from Timer 1 (TIM_TS = 000 in the<br />
TIM2_SMCR register).<br />
● Configure Timer 2 in trigger mode (TIM_SMS = 110 in the TIM2_SMCR register).<br />
When a rising edge occurs on TI1 (Timer 1), both counters start counting synchronously on<br />
the internal clock and both timers' INT_TIMTIF flags are set.<br />
In this example both timers are initialized before starting by setting their respective TIM_UG<br />
bits. Both counters starts from 0, but an offset can be inserted between them by writing any<br />
of the counter registers (TIMx_CNT). The master/slave mode inserts a delay between<br />
CNT_EN and CK_PSC on Timer 1.<br />
Figure 48.<br />
Triggering Timers 1 and 2 with Timer 1 TI1 input<br />
10.1.15 Timer signal descriptions<br />
Table 86.<br />
Timer signal descriptions<br />
Signal Internal/external Description<br />
CK_INT<br />
Internal<br />
Internal clock source: connects to <strong>STM32W108C8</strong> peripheral<br />
clock (PCLK) in internal clock mode.<br />
CK_PSC Internal Input to the clock prescaler.<br />
ETR<br />
Internal<br />
External trigger input (used in external timer mode 2): a clock<br />
selected by TIM_EXTRIGSEL in TIMx_OR.<br />
ETRF Internal External trigger: ETRP after filtering.<br />
ETRP<br />
Internal<br />
External trigger: ETR after polarity selection, edge detection<br />
and prescaling.<br />
ICy External Input capture or clock: TIy after filtering and edge detection.<br />
Doc ID 018587 Rev 2 140/215