STM32W108C8

STM32W108C8
General-purpose timers
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Reset Timer 2 by writing 1 in the TIM_UG bit (TIM2_EGR register).
Initialize Timer 2 to 0xE7 by writing 0xE7 in the Timer 2 counter (TIM2_CNTL).
Enable Timer 2 by writing 1 in the TIM_CEN bit (TIM2_CR1 register).
Start Timer 1 by writing 1 in the TIM_CEN bit (TIM1_CR1 register).
Stop Timer 1 by writing 0 in the TIM_CEN bit (TIM1_CR1 register).
Figure 45. Gating Timer 2 with enable of Timer 1
Using one timer to start the other timer
In this example, the enable of Timer 2 is set with the update event of Timer 1. Refer to
Figure 43 for connections. Timer 2 starts counting from its current value (which can be nonzero)
on the divided internal clock as soon as Timer 1 generates the update event.
When Timer 2 receives the trigger signal its TIM_CEN bit is automatically set and the
counter counts until 0 is written to the TIM_CEN bit in the TIM2_CR1 register. Both counter
clock frequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT =
fCK_INT/3).
● Configure Timer 1 in master mode to send its update event as trigger output
(TIM_MMS = 010 in the TIM1_CR2 register).
● Configure the Timer 1 period (TIM1_ARR register).
● Configure Timer 2 to get the input trigger from Timer 1 (TIM_TS = 000 in the
TIM2_SMCR register).
● Configure Timer 2 in trigger mode (TIM_SMS = 110 in the TIM2_SMCR register).
● Start Timer 1: Write 1 in the TIM_CEN bit (TIM1_CR1 register).
Doc ID 018587 Rev 2 138/215