STM32W108C8

STM32W108C8
General-purpose timers
Figure 42.
Control circuit in External clock mode 2 + Trigger mode
10.1.14 Timer synchronization
The two timers can be linked together internally for timer synchronization or chaining. A
timer configured in Master mode can reset, start, stop or clock the counter of the other timer
configured in Slave mode.
Figure 43 presents an overview of the trigger selection and the master mode selection
blocks.
Using one timer as prescaler for the other timer
Note:
For example, to configure Timer 1 to act as a prescaler for Timer 2 (see Figure 43):
● Configure Timer 1 in Master mode so that it outputs a periodic trigger signal on each
update event. Writing TIM_MMS = 010 in the TIM1_CR2 register causes a rising edge
to be output on TRGO each time an update event is generated.
● To connect the TRGO output of Timer 1 to Timer 2, configure Timer 2 in slave mode
using ITR0 as an internal trigger. Select this through the TIM_TS bits in the
TIM2_SMCR register (writing TIM_TS = 000).
● Put the slave mode controller in external clock mode 1 (write TIM_SMS = 111 in the
TIM2_SMCR register). This causes Timer 2 to be clocked by the rising edge of the
periodic Timer 1 trigger signal (which corresponds to the Timer 1 counter overflow).
● Finally both timers must be enabled by setting their respective TIM_CEN bits
(TIMx_CR1 register).
If OCy is selected on Timer 1 as trigger output (TIM_MMS = 1xx), its rising edge is used to
clock the counter of Timer 2.
Figure 43.
Master/slave timer example
Doc ID 018587 Rev 2 136/215