STM32W108C8

General-purpose timers
STM32W108C8
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on the TI2 input.
Figure 41.
Control circuit in Trigger mode
Slave mode: External clock mode 2 + Trigger mode
External clock mode 2 can be used in combination with another slave mode (except external
clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock
input, and another input can be selected as trigger input when operating in reset mode,
gated mode or trigger mode. It is not recommended to select ETR as TRGI through the
TIM_TS bits of TIMx_SMCR register.
In the following example, the up-counter is incremented at each rising edge of the ETR
signal as soon as a rising edge of TI1 occurs:
● Configure the external trigger input circuit by programming the TIMx_SMCR register as
follows:
– TIM_ETF = 0000: no filter.
– TIM_ETPS = 00: prescaler disabled.
– TIM_ETP = 0: detection of rising edges on ETR and TIM_ECE = 1 to enable the
external clock mode 2.
● Configure the channel 1 as follows, to detect rising edges on TI:
– TIM_IC1F = 0000: no filter.
– The capture prescaler is not used for triggering and does not need to be
configured.
– TIM_CC1S = 01in the TIMx_CCMR1 register to select only the input capture
source.
– TIM_CC1P = 0 in the TIMx_CCER register to validate the polarity (and detect
rising edge only).
● Configure the timer in Trigger mode by writing TIM_SMS = 110 in the TIMx_SMCR
register. Select TI1 as the input source by writing TIM_TS = 101 in the TIMx_SMCR
register.
A rising edge on TI1 enables the counter and sets the INT_TIMTIF flag. The counter then
counts on ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.
135/215 Doc ID 018587 Rev 2