You also want an ePaper? Increase the reach of your titles
YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.
General-purpose timers<br />
<strong>STM32W108C8</strong><br />
The XOR output can be used with all the timer input functions such as trigger or input<br />
capture. It is especially useful to interface to Hall effect sensors.<br />
10.1.13 Timers and external trigger synchronization<br />
The timers can be synchronized with an external trigger in several modes: Reset mode,<br />
Gated mode, and Trigger mode.<br />
Slave mode: Reset mode<br />
Reset mode reinitializes the counter and its prescaler in response to an event on a trigger<br />
input. Moreover, if the TIM_URS bit in the TIMx_CR1 register is low, an update event is<br />
generated. Then all the buffered registers (TIMx_ARR, TIMx_CCRy) are updated.<br />
In the following example, the up-counter is cleared in response to a rising edge on the TI1<br />
input:<br />
● Configure the channel 1 to detect rising edges on TI1: Configure the input filter<br />
duration. In this example, no filter is required so TIM_IC1F = 0000. The capture<br />
prescaler is not used for triggering, so it is not configured. The TIM_CC1S bits select<br />
the input capture source only, TIM_CC1S = 01 in the TIMx_CCMR1 register. Write<br />
TIM_CC1P = 0 in the TIMx_CCER register to validate the polarity, and detect rising<br />
edges only.<br />
● Configure the timer in Reset mode by writing TIM_SMS = 100 in the TIMx_SMCR<br />
register. Select TI1 as the input source by writing TIM_TS = 101 in the TIMx_SMCR<br />
register.<br />
● Start the counter by writing TIM_CEN = 1 in the TIMx_CR1 register.<br />
The counter starts counting on the internal clock, then behaves normally until the TI1 rising<br />
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the<br />
trigger flag is set (the INT_TIMTIF bit in the INT_TIMxFLAG register) and an interrupt<br />
request can be sent if enabled (depending on the INT_TIMTIF bit in the INT_TIMxCFG<br />
register).<br />
Figure 39 shows this behavior when the auto-reload register TIMx_ARR = 0x36. The delay<br />
between the rising edge on TI1 and the actual reset of the counter is due to the<br />
resynchronization circuit on the TI1 input.<br />
Figure 39.<br />
Control circuit in Reset mode<br />
133/215 Doc ID 018587 Rev 2
Change language