STM32W108C8

STM32W108C8
General-purpose timers
For example, to measure the period in the TIMx_CCR1 register and the duty cycle in the
TIMx_CCR2 register of the PWM applied on TI1, use the following procedure depending on
CK_INT frequency and prescaler value:
● Select the active input for TIMx_CCR1: write the TIM_CC1S bits to 01 in the
TIMx_CCMR1 register (TI1 selected).
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Select the active polarity for TI1FP1, used both for capture in the TIMx_CCR1 and
counter clear, by writing the TIM_CC1P bit to 0 (active on rising edge).
Select the active input for TIMx_CCR2by writing the TIM_CC2S bits to 10 in the
TIMx_CCMR1 register (TI1 selected).
Select the active polarity for TI1FP2 (used for capture in the TIMx_CCR2) by writing the
TIM_CC2P bit to 1 (active on falling edge).
● Select the valid trigger input by writing the TIM_TS bits to 101 in the TIMx_SMCR
register (TI1FP1 selected).
● Configure the slave mode controller in reset mode by writing the TIM_SMS bits to 100
in the TIMx_SMCR register.
● Enable the captures by writing the TIM_CC1E and TIM_CC2E bits to 1 in the
TIMx_CCER register.
Figure 32.
PWM input mode timing
10.1.7 Forced output mode
In output mode (CCyS bits = 00 in the TIMx_CCMR1 register), software can force each
output compare signal (OCyREF and then OCy) to an active or inactive level independently
of any comparison between the output compare register and the counter.
To force an output compare signal (OCyREF/OCy) to its active level, write 101 in the
TIM_OCyM bits in the corresponding TIMx_CCMR1 register. OCyREF is forced high
(OCyREF is always active high) and OCy gets the opposite value to the TIM_CCyP polarity
bit. For example, TIM_CCyP = 0 defines OCy as active high, so when OCyREF is active,
OCy is also set to a high level.
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