STM32W108C8

STM32W108C8
General-purpose timers
Figure 30.
Capture/compare channel 1 main circuit
Figure 31. Output stage of capture/compare channel (channel 1)
The capture/compare block is made of a buffer register and a shadow register. Writes and
reads always access the buffer register.
In capture mode, captures are first written to the shadow register, then copied into the buffer
register.
In compare mode, the content of the buffer register is copied into the shadow register which
is compared to the counter.
10.1.5 Input capture mode
In input capture mode, a capture/compare register (TIMx_CCRy) latches the value of the
counter after a transition is detected by the corresponding ICy signal. When a capture
occurs, the corresponding INT_TIMCCyIF flag in the INT_TIMxFLAG register is set, and an
interrupt request is sent if enabled.
If a capture occurs when the INT_TIMCCyIF flag is already high, then the missed capture
flag INT_TIMMISSCCyIF in the INT_TIMxMISS register is set. INT_TIMCCyIF can be
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