STM32W108C8

STM32W108C8
General-purpose timers
10.1.3 Clock selection
The counter clock can be provided by the following clock sources:
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Internal clock (PCLK)
External clock mode 1: external input pin (TIy)
External clock mode 2: external trigger input (ETR)
Internal trigger input (ITR0): using the other timer as prescaler. Refer to the Using one
timer as prescaler for the other timer for more details.
Internal clock source (CK_INT)
The internal clock is selected when the slave mode controller is disabled (TIM_SMS = 000 in
the TIMx_SMCR register). In this mode, the TIM_CEN, TIM_DIR (in the TIMx_CR1
register), and TIM_UG bits (in the TIMx_EGR register) are actual control bits and can be
changed only by software, except for TIM_UG, which remains cleared automatically. As
soon as the TIM_CEN bit is written to 1, the prescaler is clocked by the internal clock
CK_INT.
Figure 24 shows the behavior of the control circuit and the up-counter in normal mode,
without prescaling.
Figure 24. Control circuit in Normal mode, internal clock divided by 1
External clock source mode 1
This mode is selected when TIM_SMS = 111 in the TIMx_SMCR register. The counter can
count at each rising or falling edge on a selected input.
Doc ID 018587 Rev 2 118/215