STM32W108C8

STM32W108C8
General-purpose timers
autoreload value down to 1 and generates a counter underflow event. Then it restarts
counting from 0.
In this mode, the direction bit (TIM_DIR in the TIMx_CR1 register) cannot be written. It is
updated by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter
underflow. Setting the TIM_UG bit in the TIMx_EGR register by software or by using the
slave mode controller also generates an update event. In this case, the both the counter and
the prescalar's counter restart counting from 0.
Software can disable the update event by setting the TIM_UDIS bit in the TIMx_CR1
register. This avoids updating the shadow registers while writing new values in the buffer
registers. Then no update event occurs until the TIM_UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload
value.
In addition, if the TIM_URS bit in the TIMx_CR1 register is set, setting the TIM_UG bit
generates an update event, but without setting the INT_TIMUIF flag. Thus no interrupt
request is sent. This avoids generating both update and capture interrupt when clearing the
counter on the capture event.
When an update event occurs, the update flag (the INT_TIMUIF bit in the INT_TIMxFLAG
register) is set (unless TIM_USR is 1) and the following registers are updated:
● The prescaler shadow register is reloaded with the buffer value (contents of the
TIMx_PSC register).
● The auto-reload active register is updated with the buffer value (contents of the
TIMx_ARR register). If the update source is a counter overflow, the auto-reload is
updated before the counter is reloaded, so that the next period is the expected one.
The counter is loaded with the new value.
The following figures show some examples of the counter behavior for different clock
frequencies.
Figure 21.
Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6
Doc ID 018587 Rev 2 116/215