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General-purpose timers<br />
<strong>STM32W108C8</strong><br />
reload value, whereas the prescalar's counter restarts from 0, but the prescale rate doesn't<br />
change.<br />
In addition, if the TIM_URS bit in the TIMx_CR1 register is set, setting the TIM_UG bit<br />
generates an update event, but without setting the INT_TIMUIF flag. Thus no interrupt<br />
request is sent. This avoids generating both update and capture interrupts when clearing the<br />
counter on the capture event.<br />
When an update event occurs, the update flag (the INT_TIMUIF bit in the INT_TIMxFLAG<br />
register) is set (unless TIM_USR is 1) and the following registers are updated:<br />
● The prescaler shadow register is reloaded with the buffer value (contents of the<br />
TIMx_PSC register).<br />
● The auto-reload active register is updated with the buffer value (contents of the<br />
TIMx_ARR register). The auto-reload is updated before the counter is reloaded, so that<br />
the next period is the expected one.<br />
Figure 19 and Figure 20 show some examples of the counter behavior for different clock<br />
frequencies when TIMx_ARR = 0x36.<br />
Figure 19. Counter timing diagram, internal clock divided by 1<br />
Figure 20. Counter timing diagram, internal clock divided by 4<br />
Center-aligned mode (up/down counting)<br />
In center-aligned mode, the counter counts from 0 to the auto-reload value (contents of the<br />
TIMx_ARR register) - 1 and generates a counter overflow event, then counts from the<br />
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