STM32W108C8

STM32W108C8
General-purpose timers
Figure 17. Counter timing diagram, update event when TIM_ARBE = 0
(TIMx_ARR not buffered)
Figure 18.
Counter timing diagram, update event when TIM_ARBE = 1 (TIMx_ARR
buffered)
Down-counting mode
In down-counting mode, the counter counts from the auto-reload value (contents of the
TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a
counter underflow event.
An update event can be generated at each counter underflow, by setting the TIM_UG bit in
the TIMx_EGR register, or by using the slave mode controller). Software can disable the
update event by setting the TIM_UDIS bit in the TIMx_CR1 register, to avoid updating the
shadow registers while writing new values in the buffer registers. No update event occurs
until the TIM_UDIS bit is written to 0. However, the counter restarts from the current auto-
Doc ID 018587 Rev 2 114/215