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Serial interfaces<br />
<strong>STM32W108C8</strong><br />
9.13.14 Saved receive DMA count register (SCx_RXCNTSAVED)<br />
Table 80.<br />
Address offset: 0xC870 (SC1_RXCNTSAVED) and 0xC070 (SC2_RXCNTSAVED)<br />
Reset value: 0x0000 0000<br />
Saved receive DMA count register (SCx_RXCNTSAVED)<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16<br />
Reserved<br />
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />
Reserved<br />
SC_RXCNTSAVED<br />
r<br />
Bits [12:0] SC_RXCNTSAVED: Receive DMA count saved in SPI slave mode when nSSEL deasserts.<br />
The count is only saved the first time nSSEL deasserts.<br />
9.13.15 DMA first receive error register A (SCx_RXERRA)<br />
Table 81.<br />
Address offset: 0xC834 (SC1_RXERRA) and 0xC034 (SC2_RXERRA)<br />
Reset value: 0x0000 0000<br />
DMA first receive error register A (SCx_RXERRA)<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16<br />
Reserved<br />
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />
Reserved<br />
SC_RXERRA<br />
r<br />
Bits [12:0] SC_RXERRA: The offset from the start of DMA receive buffer A of the first byte received with a<br />
parity, frame, or overflow error. Note that an overflow error occurs at the input to the receive<br />
FIFO, so this offset is 4 bytes before the overflow position. If there is no error, it reads zero. This<br />
register will not be updated by subsequent errors until the buffer unloads and is reloaded, or the<br />
receive DMA is reset.<br />
107/215 Doc ID 018587 Rev 2
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