STM32W108C8

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Serial interfaces <strong>STM32W108C8</strong> 9.13.2 Serial DMA status register (SCx_DMASTAT) Table 68. Address offset: 0xC82C (SC1_DMASTAT) and 0xC02C (SC2_DMASTAT) Reset value: 0x0000 0000 Serial DMA status register (SCx_DMASTAT) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SC_RXSSEL SC_RX FRMB SC_RX FRMA SC_RX PARB SC_RX PARA SC_RX OVFB SC_R XOVF A SC_TX ACTB SC_TX ACTA SC_RX ACTB r r r r r r r r r r r SC_RX ACTA Bits [12:10] SC_RXSSEL: Status of the receive count saved in SCx_RXCNTSAVED (SPI slave mode) when nSSEL deasserts. Cleared when a receive buffer is loaded and when the receive DMA is reset. 0: No count was saved because nSSEL did not deassert. 2: Buffer A's count was saved, nSSEL deasserted once. 3: Buffer B's count was saved, nSSEL deasserted once. 6: Buffer A's count was saved, nSSEL deasserted more than once. 7: Buffer B's count was saved, nSSEL deasserted more than once. 1, 4, 5: Reserved. Bit 9 SC_RXFRMB: This bit is set when DMA receive buffer B reads a byte with a frame error from the receive FIFO. It is cleared the next time buffer B is loaded or when the receive DMA is reset. (SC1 in UART mode only) Bit 8 SC_RXFRMA: This bit is set when DMA receive buffer A reads a byte with a frame error from the receive FIFO. It is cleared the next time buffer A is loaded or when the receive DMA is reset. (SC1 in UART mode only) Bit 7 This bit is set when DMA receive buffer B reads a byte with a parity error from the receive FIFO. It is cleared the next time buffer B is loaded or when the receive DMA is reset. (SC1 in UART mode only) Bit 6 This bit is set when DMA receive buffer A reads a byte with a parity error from the receive FIFO. It is cleared the next time buffer A is loaded or when the receive DMA is reset. (SC1 in UART mode only) Bit 5 This bit is set when DMA receive buffer B was passed an overrun error from the receive FIFO. Neither receive buffer was capable of accepting any more bytes (unloaded), and the FIFO filled up. Buffer B was the next buffer to load, and when it drained the FIFO the overrun error was passed up to the DMA and flagged with this bit. Cleared the next time buffer B is loaded and when the receive DMA is reset. Bit 4 This bit is set when DMA receive buffer A was passed an overrun error from the receive FIFO. Neither receive buffer was capable of accepting any more bytes (unloaded), and the FIFO filled up. Buffer A was the next buffer to load, and when it drained the FIFO the overrun error was passed up to the DMA and flagged with this bit. Cleared the next time buffer A is loaded and when the receive DMA is reset. Bit 3 This bit is set when DMA transmit buffer B is active. 101/215 Doc ID 018587 Rev 2
<strong>STM32W108C8</strong> Serial interfaces Bit 2 This bit is set when DMA transmit buffer A is active. Bit 1 This bit is set when DMA receive buffer B is active. Bit 0 This bit is set when DMA receive buffer A is active. 9.13.3 Transmit DMA begin address register A (SCx_TXBEGA) Table 69. Address offset: 0xC810 (SC1_TXBEGA) and 0xC010 (SC2_TXBEGA) Reset value: 0x2000 0000 Transmit DMA begin address register A (SCx_TXBEGA) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SC_TXBEGA rw Bits [12:0] SC_TXBEGA: DMA transmit buffer A start address. 9.13.4 Transmit DMA begin address register B (SCx_TXBEGB) Table 70. Address offset: 0xC818 (SC1_TXBEGB) and 0xC018 (SC2_TXBEGB) Reset value: 0x2000 0000 Transmit DMA begin address register B (SCx_TXBEGB) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SC_TXBEGB rw Bits [12:0] SC_TXBEGA: DMA transmit buffer B start address. Doc ID 018587 Rev 2 102/215
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STM32W108C8 High-performance, IEEE
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STM32W108C8 Software reset . . . .
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STM32W108C8 9 Serial interfaces . .
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STM32W108C8 10.1.4 Capture/compare
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STM32W108C8 12.1.1 Non-maskable int
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STM32W108C8 Description 1 Descripti
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STM32W108C8 Description 1.2 Overvie
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STM32W108C8 Documentation conventio
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STM32W108C8 Pinout and pin descript
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STM32W108C8 Embedded memory 4 Embed
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STM32W108C8 Embedded memory 6. Seri
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STM32W108C8 Radio frequency module
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STM32W108C8 System modules 6 System
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STM32W108C8 System modules 6.2 Rese
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STM32W108C8 System modules ● PRES
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STM32W108C8 System modules Figure 5
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STM32W108C8 System modules In addit
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STM32W108C8 System modules 6.4.3 Ev
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STM32W108C8 System modules Table 11
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STM32W108C8 System modules Bits [15
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STM32W108C8 System modules Bit 1 SL
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STM32W108C8 General-purpose timers
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STM32W108C8 Analog-to-digital conve
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STM32W108C8 Interrupts 12 Interrupt
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STM32W108C8 Interrupts Table 122. N
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STM32W108C8 Interrupts Figure 50. P
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STM32W108C8 Interrupts Table 123. N
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STM32W108C8 Interrupts 12.3.2 Top-l
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STM32W108C8 Debug support 13 Debug
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STM32W108C8 Electrical characterist
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STM32W108C8 Package characteristics
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STM32W108C8 Revision history 17 Rev
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STM32W108C8 Index of registers TIMx
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STM32W108C8

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