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Serial interfaces<br />
<strong>STM32W108C8</strong><br />
9.13.2 Serial DMA status register (SCx_DMASTAT)<br />
Table 68.<br />
Address offset: 0xC82C (SC1_DMASTAT) and 0xC02C (SC2_DMASTAT)<br />
Reset value: 0x0000 0000<br />
Serial DMA status register (SCx_DMASTAT)<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16<br />
Reserved<br />
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />
Reserved<br />
SC_RXSSEL<br />
SC_RX<br />
FRMB<br />
SC_RX<br />
FRMA<br />
SC_RX<br />
PARB<br />
SC_RX<br />
PARA<br />
SC_RX<br />
OVFB<br />
SC_R<br />
XOVF<br />
A<br />
SC_TX<br />
ACTB<br />
SC_TX<br />
ACTA<br />
SC_RX<br />
ACTB<br />
r r r r r r r r r r r<br />
SC_RX<br />
ACTA<br />
Bits [12:10] SC_RXSSEL: Status of the receive count saved in SCx_RXCNTSAVED (SPI slave mode)<br />
when nSSEL deasserts. Cleared when a receive buffer is loaded and when the receive DMA is<br />
reset.<br />
0: No count was saved because nSSEL did not deassert.<br />
2: Buffer A's count was saved, nSSEL deasserted once.<br />
3: Buffer B's count was saved, nSSEL deasserted once.<br />
6: Buffer A's count was saved, nSSEL deasserted more than once.<br />
7: Buffer B's count was saved, nSSEL deasserted more than once.<br />
1, 4, 5: Reserved.<br />
Bit 9 SC_RXFRMB: This bit is set when DMA receive buffer B reads a byte with a frame error from<br />
the receive FIFO. It is cleared the next time buffer B is loaded or when the receive DMA is reset.<br />
(SC1 in UART mode only)<br />
Bit 8 SC_RXFRMA: This bit is set when DMA receive buffer A reads a byte with a frame error from<br />
the receive FIFO. It is cleared the next time buffer A is loaded or when the receive DMA is reset.<br />
(SC1 in UART mode only)<br />
Bit 7 This bit is set when DMA receive buffer B reads a byte with a parity error from the receive FIFO.<br />
It is cleared the next time buffer B is loaded or when the receive DMA is reset. (SC1 in UART<br />
mode only)<br />
Bit 6 This bit is set when DMA receive buffer A reads a byte with a parity error from the receive FIFO.<br />
It is cleared the next time buffer A is loaded or when the receive DMA is reset. (SC1 in UART<br />
mode only)<br />
Bit 5 This bit is set when DMA receive buffer B was passed an overrun error from the receive FIFO.<br />
Neither receive buffer was capable of accepting any more bytes (unloaded), and the FIFO filled<br />
up. Buffer B was the next buffer to load, and when it drained the FIFO the overrun error was<br />
passed up to the DMA and flagged with this bit. Cleared the next time buffer B is loaded and<br />
when the receive DMA is reset.<br />
Bit 4 This bit is set when DMA receive buffer A was passed an overrun error from the receive FIFO.<br />
Neither receive buffer was capable of accepting any more bytes (unloaded), and the FIFO filled<br />
up. Buffer A was the next buffer to load, and when it drained the FIFO the overrun error was<br />
passed up to the DMA and flagged with this bit. Cleared the next time buffer A is loaded and<br />
when the receive DMA is reset.<br />
Bit 3 This bit is set when DMA transmit buffer B is active.<br />
101/215 Doc ID 018587 Rev 2
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