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<strong>STM32W108C8</strong><br />
Serial interfaces<br />
9.13 DMA channel registers<br />
9.13.1 Serial DMA control register (SCx_DMACTRL)<br />
Table 67.<br />
Address offset: 0xC830 (SC1_DMACTRL) and 0xC030 (SC2_DMACTRL)<br />
Reset value: 0x0000 0000<br />
Serial DMA control register (SCx_DMACTRL)<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16<br />
Reserved<br />
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />
Reserved<br />
SC_TX<br />
DMARS<br />
T<br />
SC_R<br />
XDMA<br />
RST<br />
SC_TX<br />
LODB<br />
SC_TX<br />
LODA<br />
SC_RX<br />
LODB<br />
SC_RX<br />
LODA<br />
w w rw rw rw rw<br />
Bit 5 SC_TXDMARST: Setting this bit resets the transmit DMA. The bit clears automatically.<br />
Bit 4 SC_RXDMARST: Setting this bit resets the receive DMA. The bit clears automatically.<br />
Bit 3 SC_TXLODB: Setting this bit loads DMA transmit buffer B addresses and allows the DMA<br />
controller to start processing transmit buffer B. If both buffer A and B are loaded simultaneously,<br />
buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has<br />
no effect.<br />
Reading this bit returns DMA buffer status:<br />
0: DMA processing is complete or idle.<br />
1: DMA processing is active or pending.<br />
Bit 2 SC_TXLODA: Setting this bit loads DMA transmit buffer A addresses and allows the DMA<br />
controller to start processing transmit buffer A. If both buffer A and B are loaded simultaneously,<br />
buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has<br />
no effect.<br />
Reading this bit returns DMA buffer status:<br />
0: DMA processing is complete or idle.<br />
1: DMA processing is active or pending.<br />
Bit 1 SC_RXLODB: Setting this bit loads DMA receive buffer B addresses and allows the DMA<br />
controller to start processing receive buffer B. If both buffer A and B are loaded simultaneously,<br />
buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has<br />
no effect.<br />
Reading this bit returns DMA buffer status:<br />
0: DMA processing is complete or idle.<br />
1: DMA processing is active or pending.<br />
Bit 0 SC_RXLODA: Setting this bit loads DMA receive buffer A addresses and allows the DMA<br />
controller to start processing receive buffer A. If both buffer A and B are loaded simultaneously,<br />
buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has<br />
no effect.<br />
Reading this bit returns DMA buffer status:<br />
0: DMA processing is complete or idle.<br />
1: DMA processing is active or pending.<br />
Doc ID 018587 Rev 2 100/215
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