STM32W108C8

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Serial interfaces <strong>STM32W108C8</strong> 9.12.3 UART baud rate period register (SC1_UARTPER) Table 65. Address offset: 0xC868 Reset value: 0x0000 0000 UART baud rate period register (SC1_UARTPER) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SC_UARTPER rw Bits [15:0] SC_UARTPER: The integer part of baud rate period (N) in the equation: Rate = 24 MHz / ( (2 * N) + F ) 9.12.4 UART baud rate fractional period register (SC1_UARTFRAC) Table 66. Address offset: 0xC86C Reset value: 0x0000 0000 UART baud rate fractional period register (SC1_UARTFRAC) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SC_UA RTFRA C rw Bits [0] SC_UARTFRAC: The fractional part of the baud rate period (F) in the equation: Rate = 24 MHz / ( (2 * N) + F ) 99/215 Doc ID 018587 Rev 2
<strong>STM32W108C8</strong> Serial interfaces 9.13 DMA channel registers 9.13.1 Serial DMA control register (SCx_DMACTRL) Table 67. Address offset: 0xC830 (SC1_DMACTRL) and 0xC030 (SC2_DMACTRL) Reset value: 0x0000 0000 Serial DMA control register (SCx_DMACTRL) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SC_TX DMARS T SC_R XDMA RST SC_TX LODB SC_TX LODA SC_RX LODB SC_RX LODA w w rw rw rw rw Bit 5 SC_TXDMARST: Setting this bit resets the transmit DMA. The bit clears automatically. Bit 4 SC_RXDMARST: Setting this bit resets the receive DMA. The bit clears automatically. Bit 3 SC_TXLODB: Setting this bit loads DMA transmit buffer B addresses and allows the DMA controller to start processing transmit buffer B. If both buffer A and B are loaded simultaneously, buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has no effect. Reading this bit returns DMA buffer status: 0: DMA processing is complete or idle. 1: DMA processing is active or pending. Bit 2 SC_TXLODA: Setting this bit loads DMA transmit buffer A addresses and allows the DMA controller to start processing transmit buffer A. If both buffer A and B are loaded simultaneously, buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has no effect. Reading this bit returns DMA buffer status: 0: DMA processing is complete or idle. 1: DMA processing is active or pending. Bit 1 SC_RXLODB: Setting this bit loads DMA receive buffer B addresses and allows the DMA controller to start processing receive buffer B. If both buffer A and B are loaded simultaneously, buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has no effect. Reading this bit returns DMA buffer status: 0: DMA processing is complete or idle. 1: DMA processing is active or pending. Bit 0 SC_RXLODA: Setting this bit loads DMA receive buffer A addresses and allows the DMA controller to start processing receive buffer A. If both buffer A and B are loaded simultaneously, buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has no effect. Reading this bit returns DMA buffer status: 0: DMA processing is complete or idle. 1: DMA processing is active or pending. Doc ID 018587 Rev 2 100/215
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STM32W108C8 High-performance, IEEE
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STM32W108C8 Software reset . . . .
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STM32W108C8 9 Serial interfaces . .
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STM32W108C8 10.1.4 Capture/compare
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STM32W108C8 12.1.1 Non-maskable int
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STM32W108C8 Description 1 Descripti
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STM32W108C8 Description 1.2 Overvie
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STM32W108C8 Documentation conventio
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STM32W108C8 Pinout and pin descript
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STM32W108C8 Embedded memory 4 Embed
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STM32W108C8 Embedded memory 6. Seri
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STM32W108C8 Radio frequency module
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STM32W108C8 System modules 6 System
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STM32W108C8 System modules 6.2 Rese
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STM32W108C8 System modules ● PRES
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STM32W108C8 System modules Figure 5
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STM32W108C8 System modules In addit
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STM32W108C8 System modules 6.4.3 Ev
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STM32W108C8 System modules Table 11
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STM32W108C8 System modules Bits [15
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STM32W108C8 General-purpose timers
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STM32W108C8 Analog-to-digital conve
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STM32W108C8 Interrupts 12 Interrupt
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STM32W108C8 Interrupts Table 122. N
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STM32W108C8 Interrupts Figure 50. P
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STM32W108C8 Interrupts Table 123. N
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STM32W108C8 Interrupts 12.3.2 Top-l
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STM32W108C8 Debug support 13 Debug
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STM32W108C8 Electrical characterist
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STM32W108C8 Package characteristics
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STM32W108C8 Revision history 17 Rev
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STM32W108C8 Index of registers TIMx
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STM32W108C8

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