STM32W108C8

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STM32W108C8 14.6 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 14.7 Digital I/O specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 14.8 Non-RF system electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 206 14.9 RF electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 14.9.1 Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 14.9.2 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 14.9.3 Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 15 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 16 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 9/215 Doc ID 018587 Rev 2
STM32W108C8 Description 1 Description The STM32W108C8 is a fully integrated System-on-Chip that integrates a 2.4 GHz, IEEE 802.15.4-compliant transceiver, 32-bit ARM® Cortex-M3 microprocessor, Flash and RAM memory, and peripherals of use to designers of 802.15.4-based systems. Figure 1. STM32W108C8 block diagram PA select TX_ACTIVE Data SRAM 8 kBytes Program Flash 64 kBytes RF_TX_ALT_P,N RF_P,N PA PA LNA SYNTH IF DAC ADC MAC + Baseband ARM CORTEX-M3 ® CPU with NVIC and MPU 2 nd level Interrupt controller BIAS_R OSCA OSCB VREG_OUT nRESET Bias HF crystal OSC Regulator POR LF crystal OSC Internal HF RC-OSC Internal LF RC-OSC Calibration ADC General Purpose ADC Packet Trace sniffer General purpose timers GPIO registers UART/ SPI/I 2 C CPU debug TPIU/ITM/ FPB/DWT Always Powered Domain Watchdog Chip manage r Encryption acclerator Serial Wire and JTAG debug Sleep timer SWCLK, JTCK GPIO multiplexor swtich PA[7:0], PB[7:0], PC[7:0] The transceiver utilizes an efficient architecture that exceeds the dynamic range requirements imposed by the IEEE 802.15.4-2003 standard by over 15 dB. The integrated receive channel filtering allows for robust co-existence with other communication standards in the 2.4 GHz spectrum, such as IEEE 802.11 and Bluetooth. The integrated regulator, VCO, loop filter, and power amplifier keep the external component count low. An optional high performance radio mode (boost mode) is software-selectable to boost dynamic range. The integrated 32-bit ARM® Cortex-M3 microprocessor is highly optimized for high performance, low power consumption, and efficient memory utilization. Including an integrated MPU, it supports two different modes of operation: Privileged mode and Unprivileged mode. This architecture could be used to separate the networking stack from the application code and prevent unwanted modification of restricted areas of memory and registers resulting in increased stability and reliability of deployed solutions. The STM32W108C8 has 64 Kbytes of embedded Flash memory and 8 Kbytes of integrated RAM for data and program storage. The STM32W108C8 HAL software employs an effective wear-leveling algorithm that optimizes the lifetime of the embedded Flash. To maintain the strict timing requirements imposed by the IEEE 802.15.4-2003 standards, the STM32W108C8 integrates a number of MAC functions into the hardware. The MAC hardware handles automatic ACK transmission and reception, automatic backoff delay, and clear channel assessment for transmission, as well as automatic filtering of received packets. A packet trace interface is also integrated with the MAC, allowing complete, nonintrusive capture of all packets to and from the STM32W108C8. Doc ID 018587 Rev 2 10/215
Page 1 and 2: STM32W108C8 High-performance, IEEE
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STM32W108C8 General-purpose input/o
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STM32W108C8 Serial interfaces 9 Ser
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STM32W108C8 Serial interfaces Table
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STM32W108C8 Serial interfaces 9.4.3
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STM32W108C8 Serial interfaces 9.11.
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STM32W108C8 Serial interfaces 9.13
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STM32W108C8 Serial interfaces Bit 2
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STM32W108C8 Serial interfaces Bits
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STM32W108C8 General-purpose timers
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STM32W108C8 Interrupts 12 Interrupt
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STM32W108C8 Interrupts Table 122. N
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STM32W108C8 Interrupts Figure 50. P
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STM32W108C8 Interrupts Table 123. N
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STM32W108C8 Interrupts 12.3.2 Top-l
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STM32W108C8 Debug support 13 Debug
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STM32W108C8 Electrical characterist
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STM32W108C8 Package characteristics
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STM32W108C8 Revision history 17 Rev
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STM32W108C8 Index of registers TIMx
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STM32W108C8

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