Design Guide: CompactPCI Â® PlusIO - picmg

Design Guide: 

CompactPCI ® PlusIO 

as a link for 

CompactPCI ® / CompactPCI ® Serial 

Hybrid Systems

1 General 

1.1 About CompactPCI® PlusIO 

PICMG 2.30 CompactPCI® PlusIO is based on the basic CompactPCI® standard PICMG 2.0. The 

basic standard PICMG 2.0 is complemented by PICMG 2.30. This complement defines the pin 

assignment and the function of the user pins on the J2 connector for 32-bit system slots. With PICMG 

2.0, the signals are indicated as BP(I/O) signals and not specified further. CompactPCI® PlusIO makes 

up for this. The pin number is sufficient for leading four PCI Express® x1 links, four SATA, four USB 

2.0 as well as two Ethernet 1000Base-T interfaces to the backplane. 

Despite using the new UHM connector from 3M or equivalent, the connector on the backplane does 

not have to be changed. If an assembly is equipped with this connector, it remains completely 

compatible to the original CompactPCI® standard. These boards can be used in all existing systems 

without limitations. The new connectors make PCI Express®, SATA, USB and Ethernet available on 

the backplane - beside the legacy PCI bus. Forward and backward compatibility is guaranteed without 

limitations. 

To use the new serial interfaces they can either be wired via a rear I/O adapter or by adding new slots to 

the existing CompactPCI® system. Four new slots with identical assignment can be realized with the 

four PCI Express®, SATA and USB interfaces. Several of these systems can by connected, e.g., via 

Ethernet. The new slots can be used for, e.g., building hard drive RAIDs, the connection of frame 

grabbers via PCI Express® or the integration of PCI Express® Mini Card boards for wireless 

communication - functions which are constantly needed today and which are often realized after a 

fashion with customer-specific solutions. 

CPU boards which support PICMG 2.30 (3U as well as 6U) remain compatible to the basic standard 

without limitations and can also be used in existing systems. If a CPU board cannot serve all interfaces, 

the remaining pins can still be used specifically. The new connector allows for transmission of signals 

with up to 5 Gb/s, mechanically it remains 100% compatible to the standard. 

1.1.1 CompactPCI® PlusIO Pin Assignment 

The pin assignment for CompactPCI® PlusIO – PICMG 2.30 – has been chosen in such a way that a 32- 

bit PICMG 2.30 board can function in a 64-bit backplane. However, the additional CompactPCI® 

PlusIO pins cannot be used in that case as the pins are needed for the 64-bit extension. 64-bit PCI 

transmissions are not possible. 

CompactPCI® PlusIO Design Guide Page 2

Table 1. CompactPCI® PlusIO J1 and J2 pin assignment 

Pin Z A B C D E F 

22 GND GA4 GA3 GA2 GA1 GA0 GND 

21 GND CLK6 GND 2_ETH_B+ 1_ETH_D+ 1_ETH_B+ GND 

20 GND CLK5 GND 2_ETH_B- 1_ETH_D- 1_ETH_B- GND 

19 GND GND GND 2_ETH_A+ 1_ETH_C+ 1_ETH_A+ GND 

18 GND 2_ETH_D+ 2_ETH_C+ 2_ETH_A- 1_ETH_C- 1_ETH_A- GND 

17 GND 2_ETH_D- 2_ETH_C- PRST# REQ6# GNT6# GND 

16 GND 4_PE_CLK- 2_PE_CLK+ DEG# GND reserved GND 

15 GND 4_PE_CLK+ 2_PE_CLK- FAL# REQ5# GNT5# GND 

14 GND 3_PE_CLK- 1_PE_CLK+ 4_PE_CLKE# SATA_SCL reserved GND 

13 GND 3_PE_CLK+ 1_PE_CLK- 3_PE_CLKE# SATA_SDO SATA_SL GND 

12 GND 4_PE_Rx00+ 1_PE_CLKE# 2_PE_CLKE# SATA_SDI 4_SATA_Rx+ GND 

11 GND 4_PE_Rx00- 4_PE_Tx00+ 4_USB2+ 4_SATA_Tx+ 4_SATA_Rx- GND 

10 GND 3_PE_Rx00+ 4_PE_Tx00- 4_USB2- 4_SATA_Tx- 3_SATA_Rx+ GND 






4 GND VIO 1_PE_Tx00- 1_USB2- 1_SATA_Tx- reserved GND 

3 GND CLK4 GND GNT3 # REQ4# GNT4# GND 

2 GND CLK2 CLK3 SYSEN# GNT2# REQ3# GND 

1 GND CLK1 GND REQ1# GNT1# REQ2# GND 

25 GND +5V REQ64# ENUM# +3.3V +5V GND 

24 GND AD[1] +5V VIO AD[0] ACK64# GND 

23 GND +3.3V AD[4] AD[3] +5V AD[2] GND 

22 GND AD[7] GND +3.3V AD[6] AD[5] GND 

21 GND +3.3V AD[9] AD[8] M66EN C/BE[0]# GND 

20 GND AD[12] GND VIO AD[11] AD[10] GND 

19 GND +3.3V AD[15] AD[14] GND AD[13] GND 

18 GND SERR# GND +3.3V PAR C/BE[1]# GND 

17 GND +3.3V IPMB_SCL IPMB_SDA GND PERR# GND 

16 GND DEVSEL# GND VIO STOP# LOCK# GND 

15 GND +3.3V FRAME# IRDY# GND TRDY# GND 

14 GND GND 

13 GND GND 

12 GND GND 

11 GND AD[18] AD[17] AD[16] GND C/BE[2]# GND 

10 GND AD[21] GND +3.3V AD[20] AD[19] GND 

9 GND C/BE[3]# GND AD[23] GND AD[22] GND 

8 GND AD[26] GND VIO AD[25] AD[24] GND 

7 GND AD[30] AD[29] AD[28] GND AD[27] GND 

6 GND REQ0# GND +3.3V CLK0 AD[31] GND 

5 GND BRSVP1A5 BRSVP1B5 RST# GND GNT0# GND 

4 GND IPMB_PWR HEALTHY# VIO INTP INTS GND 

3 GND INTA# INTB# INTC# +5V INTD# GND 

2 GND TCK +5V TMS TDO TDI GND 

1 GND +5V -12V TRST +12V +5V GND 

Pin Z A B C D E F 


1.2 About CompactPCI® Serial 

CompactPCI® Serial (CPCI-S.0) is an all-new standard that defines a modular computer system 

consisting of a backplane, a system slot and up to 8 peripheral slots. It defines the support of PCI 

Express, SATA/SAS, USB and Ethernet, concurrently. 

To support the high-speed serial interfaces, a connector is introduced which is compatible to 

[IEEE1101]. 

The mechanical design is fully backward compatible to CompactPCI® and will interoperate with 

existing systems. This specification allows the implementation of hybrid backplanes: CompactPCI® 

Serial with CompactPCI®, CompactPCI® PlusIO and/or with CompactPCI® Express. 3U and 6U 

boards are supported with the main focus being on 3U. This design guide deals with 3U systems 

exclusively for the sake of brevity, but it could easily be adapted for 6U systems as the general approach 

would be very similar. 


1.2.1 CompactPCI® Serial Pin Assignment 

Since this document deals with CompactPCI PlusIO hybrid systems exclusively, it covers only the 

peripheral slots as defined in the CompactPCI Serial specification. J2/P2..J5/P5 are reserved for 

CompactPCI Serial rear I/O and are not used in a CompactPCI PlusIO hybrid system. 

Table 2. Peripheral Slot Pin Assignment J1/P1…J6/P6 Row A…F 

Pin A B C D E F 

6 - 08 GND 8_ETH_A+ 8_ETH_A- GND 8_ETH_B+ 8_ETH_B- 

6 - 07 7_ETH_A+ 7_ETH_A- GND 7_ETH_B+ 7_ETH_B- GND 







5 - 06 GND IO IO GND IO IO 

5 - 05 IO IO GND IO IO GND 





























1 - 06 GND 1_PE_Tx02+ 1_PE_Tx02- GND 1_PE_Rx02+ 1_PE_Rx02- 

1 - 05 1_PE_Tx00+ 1_PE_Tx00- GND 1_PE_Rx00+ 1_PE_Rx00- GND 

1 - 04 GND 1_USB2+ 1_USB2- GND PE_CLKIN+ PE_CLKIN- 

1 - 03 1_USB3_Tx+ 1_USB3_Tx- GA0 1_USB3_Rx+ 1_USB3_Rx- GA1 

1 - 02 GND I²C_SCL I²C_SDA GND reserved reserved 

1 - 01 +12V STNDBY GND +12V +12V GND 

Pin A B C D E F 


Table 3. Peripheral Slot Pin Assignment J1/P1…J6/P6 Row G…L 

G H I J K L Pin 

GND 8_ETH_C+ 8_ETH_C- GND 8_ETH_D+ 8_ETH_D- 6 - 08 

7_ETH_C+ 7_ETH_C- GND 7_ETH_D+ 7_ETH_D- GND 6 - 07 







GND IO IO GND IO IO 5 - 06 

IO IO GND IO IO GND 5 - 05 



























GND 1_PE_Tx07+ 1_PE_Tx07- GND 1_PE_Rx07+ 1_PE_Rx07- 2 - 02 

1_PE_Tx05+ 1_PE_Tx05- GND 1_PE_Rx05+ 1_PE_Rx05- GND 2 - 01 

GND 1_PE_Tx03+ 1_PE_Tx03- GND 1_PE_Rx03+ 1_PE_Rx03- 1 - 06 

1_PE_Tx01+ 1_PE_Tx01- GND 1_PE_Rx01+ 1_PE_Rx01- GND 1 - 05 

GND 1_SATA_Tx+ 1_SATA_Tx- GND 1_SATA_Rx+ 1_SATA_Rx- 1 - 04 

SATA_SDI SATA_SDO GA2 SATA_SCL SATA_SL GA3 1 - 03 

GND RST# WAKE_OUT# GND PCIE_EN# SYSEN# *) 1 - 02 

+12V +12V GND +12V +12V GND 1 - 01 


6 U only 6 U only 6 U only 6 U only 

GND +12V +12V GND +12V +12V 0 - 06 

STANDBY GND GND STANDBY GND GND 0 - 05 

GND 2_UP_C+ 2_UP_C- GND 2_UP_D+ 2_UP_D- 0 - 04 

1_UP_C+ 1_UP_C- GND 1_UP_D+ 1_UP_D- GND 0 - 03 

nc nc nc nc nc nc 0 - 02 

-48V_B -48V_B nc -48V RTN_B -48V RTN_B nc 0 - 01 


6 U only 6 U only 6 U only 6 U only 

*) Open on the Backplane 


2 Designing Hybrid Systems 

2.1 CompactPCI® PlusIO System Architecture 

The original CompactPCI® architecture is based on a parallel bus which connects the system slot to the 

peripheral slots. PICMG 2.16 – a CompactPCI® extension – introduced Ethernet on the backplane as 

another transmission medium beside the parallel PCI bus. CompactPCI® Express turns away 

completely from the parallel PCI bus and is based exclusively on PCI Express® as a fast serial point-topoint 

connection. 

The new standard PICMG 2.30 CompactPCI® PlusIO extends CompactPCI® by PCI-Express, 

Ethernet, SATA/SAS and USB. It supports the PCI bus and the modern, serial, fast interconnects at the 

same time. It extends CompactPCI® by PCI Express® and Ethernet for multiprocessing. SATA/SAS is 

available for building RAID hard disk systems. USB on the other hand is well suited for connecting 

radio modules (wireless communication like WiFi etc.). 

CompactPCI® PlusIO uses the user I/O pins of the system slot in order to support legacy PCI slots as 

well as slots based on modern serial interconnects. No bridges or switches are required for this. Ethernet 

can be used for multiprocessing. 

Figure 1. CompactPCI PlusIO System Architecture (configuration example) 

System Slot 

CPU 

Hub / I/O Controller 

PCI Express 

PCI Express 

PCI Bus 

SATA 

USB 

Ethernet 

32 bit 

32 bit 

32 bit 

Industrial 

I/O 

Industrial 

I/O 

Graphics 

Ethernet 

Hard 

Drives 

WiFi 

Ethernet 

Peripheral 

CPU 

Peripheral Slots 

2.2 CompactPCI® PlusIO Implementation Rules for Guaranteeing 

Interoperability 

CompactPCI® PlusIO – PICMG 2.30 – supports four PCI Express®, SATA and USB 2.0 interfaces as 

well as two Ethernet interfaces on the backplane. Not every CPU board will use all of the new interfaces 

– e.g. because of the costs. A typical Intel® Atom platform might perhaps only support one Ethernet 

and one PCIe®. It depends on the implementation whether SATA can be used. Four USB interfaces are 

possible if required. In order to guarantee maximum interoperability between CPU boards of different 

manufacturers, the PICMG 2.30 standard clearly defines the sequence in which the interfaces have to be 


"filled". This makes sure, for example, that the only PCIe® interface of one manufacturer does not 

collide with a differing assignment of another manufacturer. 

The prescribed sequence for Ethernet is ascending: 1, 2, for SATA descending: 4, 3, 2, 1; for USB and 

PCI Express® ascending: 1, 2, 3, 4. Except for SATA the interfaces are filled incrementing – why not 

the SATA interfaces? 

A CompactPCI® system using PICMG 2.30 can be equipped with up to four of the new CompactPCI® 

Serial slots on the hybrid backplane. These four slots shall be usable to the maximum even if not all 

interfaces can be supported by a CPU board. With four slots it would be unhandy if all interfaces were 

led to the first slot and none to the last. PCI Express® and USB are implemented concurrently in order 

to enable the use of PCI Express® MiniCards, for example. One slot will often be needed for a hard 

disk or an SSD. As only one interface per slot is needed in this case, the interfaces are filled descending. 

A system based on an Intel® Atom SBC might look like this: Ethernet on the backplane for 

controlling an additional computer, a video input card controlled via PCI Express® is plugged into the 

first peripheral slot, the second slot is equipped with a USB-based RS485 extension, slot 3 supports a 

WiFi interface – also USB – and slot 4 accommodates a SATA hard disk. 

Figure 2. Implementation example for a system based on an SBC with Intel® Atom – a CPU which 

does not support all PICMG 2.30 interfaces 

1x Ethernet 

1x PCIE 

2x SATA 

4x USB 

PCIE 1 

USB 1 USB 2 

SATA 3 

USB 3 

SATA 4 

USB 4 

System slot with PICMG 2.30 – Atom-based 

Peripheral slot – Video input 

Peripheral slot – RS485 

Peripheral slot – WiFi 

User I/O User I/O User I/O 

Peripheral slot – HDD 

User I/O 


2.3 Hybrid Backplanes for CompactPCI® and CompactPCI® PlusIO 

(PICMG 2.30) 

A hybrid system with a CompactPCI PlusIO board at its center can support up to 7 CompactPCI parallel 

peripheral slots (as previously) and up to four CompactPCI Serial peripheral slots. 

Figure 3. CompactPCI® / CompactPCI® PlusIO 8-slot hybrid backplane example 

PICMG 

2.0 

peripheral 

slot 

PICMG 

2.0 

peripheral 

slot 

PICMG 

2.0 

peripheral 

slot 

PICMG 

2.0 & 2.30 

system 

slot 

PICMG 

CPCI-S.0 

peripheral 

slot 

PICMG 

CPCI-S.0 

peripheral 

slot 

PICMG 

CPCI-S.0 

peripheral 

slot 

PICMG 

CPCI-S.0 

peripheral 

slot 

Ethernet (optional) 

Legacy CompactPCI 32 bit 

P2 rear I/O connector (user I/O) 

User I/O User I/O User I/O 

P2 CompactPCI pinout 

PICMG 

PlusIO2.30 

CompactPCI Serial area 

for rear I/O (optional) 

Legacy CompactPCI 32 CompactPCI bit P1 connector 

CompactPCI Serial base connector 

The figure above shows an example of an 8-slot hybrid backplane with the three standard CompactPCI 

peripheral slots and the system slot for the CompactPCI PlusIO CPU board on the left and the maximum 

number of four CompactPCI Serial peripheral slots on the right. The peripheral slots’ small connector 

carries the power supply, the PCIe 1x, SATA and USB (2) signals and - where used - monitoring and 

control lines. The Ethernet signals are carried via a separate connector and can be left unassembled to 

reduce backplane costs when Ethernet signals are not needed. 

Figure 4. Hybrid backplane example with four CompactPCI® Serial peripheral slots 


2.3.1 Recommendations for Backplane Designs 

It is highly recommended to use the following wiring schema (signals in the same row are connected 

together): 

Table 4. Backplane Wiring for Four Peripheral Slots 

System Slot Slot 1 Slot 2 Slot 3 Slot 4 

1_PCIE 1_PCIE 

2_PCIE 

1_PCIE 

3_PCIE 

1_PCIE 

4_PCIE 

1_PCIE 

1_SATA/SAS 1_SATA/SAS 

2_SATA/SAS 

1_SATA/SAS 

3_SATA/SAS 

1_SATA/SAS 

4_SATA/SAS 

1_SATA/SAS 

SATA_GPIO SATA_GPIO SATA_GPIO SATA_GPIO SATA_GPIO 

1_USB2 1_USB2 

2_USB2 

1_USB2 

3_USB2 

1_USB2 

4_USB2 

1_USB2 

1_ETH 1_ETH 

2_ETH 

1_ETH 

2_ETH *) 2_ETH *) 

*) point to point connection between Slot 1 and 2 

Table 5. Backplane Wiring for Three Peripheral Slots 

System Slot Slot 1 Slot 2 Slot 3 

1_PCIE 1_PCIE 

2_PCIE 

1_PCIE 

3_PCIE 

1_PCIE 

4_PCIE 

1_SATA/SAS 


3_SATA/SAS 

1_SATA/SAS 

4_SATA/SAS 

1_SATA/SAS 

SATA_GPIO SATA_GPIO SATA_GPIO SATA_GPIO 

1_USB2 1_USB2 

2_USB2 

1_USB2 

3_USB2 

1_USB2 

4_USB2 

1_ETH 1_ETH 

2_ETH 

1_ETH 

2_ETH *) 2_ETH *) 



Table 6. Backplane Wiring for Two Peripheral Slots 

System Slot Slot 1 Slot 2 

1_PCIE 1_PCIE 

2_PCIE 1_PCIE 

3_PCIE 

1_PCIE 

4_PCIE 

1_PCIE 

1_SATA/SAS 

2_SATA/SAS 


4_SATA/SAS 

1_SATA/SAS 

SATA_GPIO SATA_GPIO SATA_GPIO 

1_USB2 1_USB2 

2_USB2 

1_USB2 

3_USB2 

4_USB2 

1_ETH 1_ETH 

2_ETH 

1_ETH 

2_ETH *) 2_ETH *) 


Table 7. Backplane Wiring for One Peripheral Slot 

System Slot Slot 1 

1_PCIE 1_PCIE 

2_PCIE 1_PCIE 

3_PCIE 1_PCIE 

4_PCIE 1_PCIE 

1_SATA/SAS 

2_SATA/SAS 

3_SATA/SAS 


SATA_GPIO SATA_GPIO 

1_USB2 1_USB2 

2_USB2 

3_USB2 

4_USB2 

1_ETH 1_ETH 

2_ETH 2_ETH 

2.3.2 PCI Express® Configuration Possibilities with CompactPCI® PlusIO 

CompactPCI® PlusIO – PICMG 2.30 – permits to lead a total of four PCI Express® interfaces to the 

backplane. The Ultra Hard Metric connectors on the plug-in board permit data rates of up to 5 Gb/s, 

traditional 2-mm connectors being usable on the backplane. 

These four interfaces (also called links) can be used to control four PCI Express®-based peripheral 

boards. Each interface is equipped with one differential receive pair and a differential transmit pair – a 

lane. The four PCI Express® lines can, e.g., be compatible to CompactPCI® Express or to 

CompactPCI® Serial. 

Each interface reaches data rates of 250 MB/s with PCI Express® Gen1 or 500 MB/s with PCI 

Express® Gen2 per direction. For some applications, however, e.g., for image processing, these data 

rates are still not sufficient. For this reason, the PICMG Standard 2.30 CompactPCI® PlusIO allows to 


"cluster" the four PCI Express® interfaces. This way, the four links with one lane each defined for 

PICMG 2.30 can also be configured as two links with two lanes each or even as one link with four 

lanes. In the last case, theoretical data rates of 1,000 MB/s with PCI Express® Gen1 or 2,000 MB/s for 

Gen2 can be reached, but only with a connected device. Note that clustering is not possible with a 

standard backplane as shown in Figure 4 and with standard CompactPCI Serial peripheral boards as 

described in Chapter 1.2.1. 

The PICMG 2.30 CPU board imports the configuration via four control lines which are also used to 

activate the respective 100 MHz clock which is allocated to a PCI Express® interface. No additional 

lines are necessary. This way, CompactPCI® PlusIO PICMG 2.30 guarantees high flexibility for the 

connection of high-speed peripheral components based on PCI Express® while being 100% compatible 

to the established CompactPCI® standard and without needing additional infrastructure like switches or 

bridges – a future-safe solution. 

Table 8. PCI Express® configuration 

1_PE_CLKE# 2_PE_CLKE# 3_PE_CLKE# 4_PE_CLKE# PCI Express Config. 

open open open open not defined 

GND open open open 1 link with 4 lanes 

open GND open open 2 links with 2 lanes 

GND GND open open 2 links with 2 lanes 

open open GND open 4 links with 1 lane 

GND open GND open 4 links with 1 lane 

open GND GND open 4 links with 1 lane 

GND GND GND open 4 links with 1 lane 

open open open GND 4 links with 1 lane 

GND open open GND 4 links with 1 lane 

open GND open GND 4 links with 1 lane 

GND GND open GND 4 links with 1 lane 

open open GND GND 4 links with 1 lane 

GND open GND GND 4 links with 1 lane 

open GND GND GND 4 links with 1 lane 

GND GND GND GND 4 links with 1 lane 

Figure 5. Four Interfaces with 1 lane each – data rate 250/500 MB/s 

1 lane 

PCI Express I/O 

System slot 

CompactPCI 

PlusIO 

1 lane 

1 lane 



1 lane 



Figure 6. One interface with four lanes – data rate 1000/2000 MB/s 

System slot 

CompactPCI 

PlusIO 

4 lanes 


2.3.3 Power Requirements of Hybrid Systems 

The power requirements for the two parts of a CompactPCI / CompactPCI Serial hybrid system are very 

different, so a single standard PSU may not be enough in many cases. The CompactPCI part of a hybrid 

system always needs +5V supply voltage. Depending on the system configuration, +3.3V, -12V and 

+12V lines may also be necessary. The CompactPCI Serial part relies on a single rail +12V main power 

supply. An additional +5V standby voltage line is optional for certain system configurations. The 

backplane distributes the supply voltages to the front boards. 

2.3.4 Geographical Addressing in Hybrid Systems 

Geographical addressing for the CompactPCI and CompactPCI Serial parts of a hybrid system is 

handled differently and independently. Consult the standard specification for the respective system for 

details. 


3 Appendix: Literature and Web Resources 

www.compactpciserial.net 

The Next Generation CompactPCI®: PICMG 2.30 PlusIO and PICMG CPCI-S.0 (blog) 

http://www.compactpci.org 

Official PICMG 2.30 page

Design Guide: CompactPCI Â® PlusIO - picmg

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