PICMG Specification

PICMG 2.0R3.0: ECN 2.0-3.0-002
PICMG Specification
Engineering Change Notice 2.0-3.0-002
Topic: Self-Describing Slot Geography
Affected Specification: PICMG 2.0 R3.0
Sponsor(s): Software Interoperability Subcommittee
Participants in Final Ballot Group:
Aculab, Artela Systems, Asis, Force Computers, Hybricon, Intel, LynuxWorks,
Matrox, MontaVista Software, National Instruments, Pentair Electronic
Packaging, Pigeon Point Systems, PLX Technology, Rittal/Kaparel, SANMINA,
Spectel, Sun Microsystems, Wind River Systems
Description
The focus of this ECN is to enable hardware-independent software to map between:
o the geographic addresses (or physical slot numbers) that are defined for each
CompactPCI slot and
o the logical PCI addresses (based on the bus, device and function numbers) by
which operating systems and device drivers access the boards in those slots.
The emphasis is on systems containing CompactPCI buses on the backplane. Switch
fabric-based architectures, such as those established by PICMG 2.16 and PICMG 2.17
need to address these issues separately for boards that don’t interface to the CompactPCI
bus on the backplane. Both architectures provide for systems with and without
CompactPCI buses on the backplane.
Justification
Achieving the above mapping is crucial to achieving two higher level goals:
o Enabling application and system software to communicate with an operator about
specific boards in the system by designating them in a simple and precise manner
that is consistent across systems and vendors. The consequences of operator
action on the wrong slot can be severe.
CompactPCI physical slot numbers start at 1 at the top left-most slot and increase
sequentially. CompactPCI backplanes already provide a binary encoded physical
slot number to each slot. Logical PCI addresses are the likeliest alternative board
designators, but can be confusing and error prone for operators.
PCI bus numbers can be different over time in the same system, depending on
board population. Bus numbers in the system are directly affected by the
presence of boards that interface to the CompactPCI bus through transparent PCI-
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PICMG 2.0R3.0: ECN 2.0-3.0-002
to-PCI bridges. PCI bus and device numbers are not intuitive. Two systems can
look very similar and have quite different bus number structures. Device numbers
of CompactPCI boards are typically in the range 9 to 15, but the ordering of
device numbers within the physical slots of a given segment can be arbitrary.
o For systems based on PICMG 2.9, the CompactPCI System Management
specification, enabling integration of information from two critical domains. The
system management domain is based on the Intelligent Platform Management
Interface (IPMI) and inherently uses physical slot numbers to identify boards.
Meanwhile, the operating system domain typically uses PCI logical addresses to
refer to boards on a CompactPCI bus. PICMG 2.9R1.0 does not provide a
mechanism for hardware-independent software to correlate information between
these domains, each of which may contain unique information critical to the
overall management of a system.
In summary: the overall situation regarding geographic addressing in CompactPCI
systems is that backplanes supply a binary encoded geographic address (GA) to each slot,
but there is:
o No requirement that boards do anything with it, except in PICMG 2.9 systems,
where GA is used in the IPMI subsystem but not generically accessible to the PCI
subsystem.
o No hardware-independent means to get the GA of the slot containing a specific
board.
Style
Specific proposed changes are provided in the next section, in the style
described below.
ECN text describing changes in the affected document uses this font.
Text intended for inclusion in the body of the specification uses this font.
Section headers for text intended for inclusion in the body of the specification are
preceded with the notation:
y.z Title
where: x indicates the level of header to be used, and y.z indicates the
anticipated number that would be automatically generated by Microsoft Word by
the inclusion of this new section named Title.
Newly inserted Figure and Table items are assigned numbers in a special series
for this ECN. Figures are numbered E02-Fn, with Tables numbered E02-Tn.
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PICMG 2.0R3.0: ECN 2.0-3.0-002
Concurrent with development of this ECR02 for PICMG 2.0R3.0, ECR01 was
also in progress to add CompactPCI support for PCI-X. Wherever possible, item
numbering in this ECN is chosen to be compatible with the changes proposed in
ECR01. The goal is to minimize the challenges of:
• merging the two ECNs (once both are adopted) into the main
specification and
• concurrently using the two ECNs for development guidance in the
interim before the merge occurs.
Form for Compliance Claims and Requirement References
Consistent with the PICMG Policies and Procedures for Specification
Development, the following form for claims of compliance or requirement
references from other PICMG specifications is recommended:
“[This product complies with…] or [component x shall meet the requirements
of…] PICMG 2.0 R3.0 as amended by ECN 2.0-3.0-002.”
Specific Proposed Changes
Section 1.5 Applicable Documents
Add references to PICMG 2.5, 2.6, 2.7, 2.16, 2.17 and the PCI-to-PCI Bridge
spec.
• PCI-to-PCI Bridge Architecture Specification. PCI Special Interest Group, 5200
N.E. Elam Young Parkway, Hillsboro OR 97124-6497, Phone: (503) 696-2000
http://www.pcisig.com/
• PICMG 2.5, CompactPCI Computer Telephony Specification.
• PICMG 2.6 1 , Bridging Beyond Eight Slots: Common Practices.
• PICMG 2.7, CompactPCI Dual System System Slot Specification.
• PICMG 2.16, CompactPCI Packet Switching Backplane Specification.
• PICMG 2.17 2 , CompactPCI StarFabric Specification.
Minor Update to Section 2.1 Form Factor
Edit the 2 nd paragraph on page 14 (just below Figure 2) to clarify the
requirements on physical slot numbering.
CompactPCI defines slot numbering based on the concept of physical and logical slots.
Physical slot numbers shall start at 1 in the top-left corner of the card cage. All
CompactPCI systems should label all physical slots with their physical slot numbers
1 At this writing, PICMG 2.6 is in development.
2 At this writing, PICMG 2.17 is in development.
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PICMG 2.0R3.0: ECN 2.0-3.0-002
within the compatibility glyphs. Figure 2 illustrates physical slot numbering within the
compatibility glyphs (e.g., 1 ) on a backplane. Similar slot labeling should be applied on
the subrack if necessary to ensure operator visibility. See Section 4.1.9 for further details
on slot labeling and compatibility glyphs.
New Section 2.6 Self-Describing Slot Geography
Add a new section introducing the self-describing slot geography features of
CompactPCI, including the new features introduced by this ECN.
2.6 Self-Describing Slot Geography
The strong modularity of CompactPCI components allows: 1) a wide range of boards to
be installed in a given backplane and 2) the same board (say, a system slot board) to be
installed in a wide range of backplanes. These combinations can produce very different
slot geographies. The slot geography of a segment of CompactPCI slots is the mapping,
for each slot, between:
• the physical slot number of the slot, and
• for peripheral slots, the PCI logical device number by which a board in that slot is
addressed on the CompactPCI bus.
Accurate information about the slot geography of a system is crucial to ensuring that
application and system software can communicate with an operator about specific boards
in the system by designating them with simple and precise physical slot numbers.
Physical slot numbers are far preferable to the likely alternative slot designator: the PCI
logical address by which a slot is referenced on the CompactPCI bus. PCI logical
addresses are typically easy for operating systems and device drivers, but can be cryptic
and confusing to an operator. The consequences of operator action on the wrong slot can
be severe.
This specification’s approach to these challenges has three aspects:
1. Embedded information in backplanes that can electrically self-describe their slot
geographies and a strong recommendation that slot geography data be made
available to software.
Each CompactPCI slot can include dedicated geographic address pins that
electrically identify the physical slot number to a board installed in that slot.
Additional pins in a system slot can describe the PCI geography of the backplane
bus segment created by that slot.
2. A particular mechanism that allows CompactPCI boards (such as system slot
boards) to make this geographic information available to software in a hardware
independent way.
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Leveraging the Vital Product Data feature defined by Revision 2.2 of the PCI
Local Bus Specification, CompactPCI boards can provide access to this
geographic information for hardware-independent software.
3. A strong recommendation that CompactPCI subracks include operator-visible
physical slot number labeling.
Together, these facilities can enable simple and precise communication with an operator
regarding the location of boards in a system.
New Section 3.1.10 Mapping PCI Device Numbers to ADxx Lines on
System Slot Boards
Add a constraint on this mapping to facilitate a simple description of slot
geography for backplane segments. Although this is a new constraint that is not
present in PICMG 2.1R3.0, essentially all existing system slot boards are very
likely to already meet it.
3.1.10 Mapping PCI Device Numbers to ADxx Lines on System Slot
Boards
System Slot boards that create a backplane segment implement a specific mapping from
PCI device numbers to ADxx lines for Type 0 configuration cycles targeting that
segment. For backplane segments that are created by PCI-to-PCI bridges, that mapping
is mandated by the PCI-to-PCI Bridge Architecture specification. For other segments
that are created by PCI host bridges:
•The PCI-to-PCI bridge mapping should be used.
•Otherwise, the mapping shall be of the form “xx = ADxx Constant plus or minus
Device Number” where ADxx Constant is fixed for a particular backplane
segment. For instance, some host bridges use plus and ADxx Constant = 11; for
backplane segments created by such bridges, xx = 11 + Device Number. The
mandated mapping for PCI-to-PCI bridges uses plus and ADxx Constant = 16.
For a sequential mapping like AD31 = Device 0, AD30 = Device 1, …, ADxx
Constant would be 31 and the operator would be minus.
Update to Section 3.2.7.6 Geographic Addressing (GA[4..0])
Insert additional text at the end of this section on page 26 to note the possibility
of providing access to GA data via VPD.
Boards that support Vital Product Data may provide access to this geographic addressing
data via special keywords defined in Chapter 6, Vital Product Data (VPD) Requirements.
For peripheral boards that support a VPD interface in the CompactPCI bus interface
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device, the LC keyword may be implemented to provide a hardware-independent means
for software to identify the physical slot in which the board is installed.
New Section 3.2.7.8 Segment Type (ST[1..0])
Define a new field in system slots that helps to identify the PCI geography of the
backplane segments created by those system slots.
3.2.7.8 Segment Type (ST[1..0])
The ST[1..0] signals should be implemented in each system slot to help identify the PCI
geography of peripheral slots created by those system slots. Boards that use the ST
signals shall pull them up with 10.0 Kohm ±10% resistors.
In a backplane system slot implementing the ST[1..0] signals, the Segment Type created
by that system slot shall be encoded on the backplane by grounding and leaving
unconnected different combinations of pins. Table E02-T1 defines the Segment Types
corresponding to each such combination, with names for specifically assigned types.
Segment Type Unknown indicates that a system slot does not support Segment Type
identification. Subsequent subsections define the Segment Types.
Table E02-T1. Segment Types Identified by ST[1..0]
Segment Type
Name
ST[1] (J2-D21) ST[0] (J2-E21)
Reserved GND GND
Nominal Left GND Open
Nominal Right Open GND
Unknown Open Open
3.2.7.8.1 Definition and Use of Nominal Left and Nominal Right
Segments
In Nominal backplane segments, sequential logical slots (and the associated ADxx
mappings defined in Table 7) occupy sequentially numbered physical slots moving away
from the system slot, either to the right or to the left.
The following properties apply to Nominal Left segments:
• The GA[4..0] field defines the physical slot number of the system slot.
• The closest distinct (not co-located) peripheral slot is immediately to the left of
the system slot that creates it and has a physical slot number one smaller.
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• The IDSEL pin of that closest peripheral slot is connected to the AD31 signal in
accordance with the logical slot #2 definition in Table 7.
• Additional peripheral slots are sequentially further to the left and have physical
slot numbers sequentially smaller.
• The IDSEL pin of each additional peripheral slot is connected to the sequentially
decreasing ADxx signal (AD30, AD29 … AD25) in accordance with sequentially
increasing logical slot #s defined in Table 7.
The following properties apply to Nominal Right segments:
• The GA[4..0] field defines the physical slot number of the system slot.
• The closest distinct (not co-located) peripheral slot is immediately to the right of
the system slot that creates it and has a physical slot number one larger.
• The IDSEL pin of that closest peripheral slot is connected to the AD31 signal in
accordance with the logical slot #2 definition in Table 7.
• Additional peripheral slots are sequentially further to the right and have physical
slot numbers sequentially larger.
• The IDSEL pin of each additional peripheral slot is connected to the sequentially
decreasing ADxx signal (AD30, AD29 … AD25) in accordance with sequentially
increasing logical slot #s defined in Table 7.
PICMG 2.6, Bridging Beyond Eight Slots: Common Practices, introduces a unique type
of system slot board, a pallet bridge. A pallet bridge installs on the back of and parallel
to the backplane. With a pallet bridge on the back of a slot creating the backplane
segment, a peripheral board can be installed in the front position of the same slot. Pallet
bridges are especially valuable for chassis configurations where the number of available
normal peripheral slots needs to be maximized. See PICMG 2.6 for further background
and examples.
When a backplane segment is configured for use with a pallet bridge, long pins are
installed in the P1/P2 zone in the system slot so that a pallet bridge module can be
connected to those pins. These are the same physical pins to which a peripheral board in
that same slot would connect. A peripheral slot that shares the same physical pins on the
backplane with a system slot (where the system slot is typically designed for a rear pallet
bridge) is defined as co-located.
This dual use of the same physical pins constrains the ADxx signal that can be connected
to IDSEL for that co-located peripheral slot. The xx value must be chosen so that the
corresponding assignment of the INTA#-INTD# signals matches the assignment on
system slots, as defined in Table 8. By consistent extension of Table 8, AD24 meets this
requirement. PICMG 2.6 (tentatively) will specify AD24 as the IDSEL signal for such
co-located peripheral slots created by pallet bridges.
The geography of the conventional peripheral-only slots created by a pallet bridge
configuration can be described by any of the defined Segment Types. Those Segment
Types do not cover the PCI geography of the co-located peripheral slot (specifically the
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ADxx signal associated with that peripheral slot). Section 6.3 provides one way to
address the missing data item.
PICMG 2.7, the CompactPCI Dual System Slot Specification, defines 6U system slots
and system slot boards that create two backplane segments. J1/P1 and J2/P2 create one
of the segments. J4/P4 and J5/P5 create the other segment. Consistent with PICMG 2.7,
the ST[1..0] signals in the additional “system slot” on J4/P4 + J5/P5 are assigned to J5,
row 21. Except for that difference in the connector location, other aspects of ST[1..0]
implementation are equivalent for the J4/P4 + J5/P5 system slot, unless stated otherwise.
A dual system slot shall implement GA[4..0] equivalently in both connectors except
when it creates dual Stacked 3U segments, as detailed further in Section 3.2.7.8.2.
A dual system slot may use Nominal Left or Nominal Right segments to implement 6U
backplane segments on either side of the system slot, with backplane segments on either
side created by either P1/P2 or P4/P5.
See Appendix C for examples of backplane configurations with Nominal Left and Right
segments, including dual system slot configurations.
3.2.7.8.2 Stacked 3U Segments
Stacked 3U backplane segments are Nominal segments on the same side of a 6U dual
system slot, with the segment created by P1/P2 below the segment created by P4/P5. The
segments are either: 1) both Nominal Left or 2) both Nominal Right segments.
Two distinct physical slot numbers are provided to the board, one from P5 and the other
from P2. This situation requires special care in the use of these two distinct GA fields:
one is the actual physical slot number of the dual system slot board (denoted GA[4..0], as
usual) and the other is an auxiliary slot number (denoted GA[4..0] A ) used only to derive
the slot numbers of one of the Stacked segments.
For Stacked 3U segments to the left of a 6U dual system slot board:
•The segment type for the top 3U segment created by P4/P5 will be Nominal Left.
GA[4..0] A will be defined in P5.
•Since the dual system slot auxiliary slot number is GA[4..0] A , the adjacent top
rightmost 3U peripheral slot will have the physical slot number GA[4..0] A - 1.
•The segment type for the lower 3U segment created by P1/P2 will be Nominal
Left. The actual physical slot number of the system slot board, GA[4..0] will be
defined in P2.
•Since the physical slot number of the dual system slot is GA[4..0], the adjacent
lower rightmost 3U peripheral slot will have the physical slot number GA[4..0] -
1.
For Stacked 3U segments to the right of a 6U dual system slot board:
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PICMG 2.0R3.0: ECN 2.0-3.0-002
•The segment type for the top 3U segment created by P4/P5 will be Nominal
Right. The actual physical slot number of the system slot board, GA[4..0], will be
defined in P5.
•Since the physical slot number of the dual system slot is GA[4..0], the adjacent
top leftmost 3U peripheral slot will have the physical slot number GA[4..0] + 1.
•The segment type for the lower 3U segment created by P1/P2 will be Nominal
Right. GA[4..0] A will be defined in P2.
•Since the dual system slot auxiliary slot number is GA[4..0] A , the adjacent lower
leftmost 3U peripheral slot will have the physical slot number GA[4..0] A + 1.
See Appendix C for examples of backplane configurations with Stacked 3U segments.
Slot numbering and mechanical requirements defined elsewhere in this specification
effectively prohibit installing a pair of independent 3U system slot boards in a dual
system slot designed for Stacked 3U segments.
3.2.7.8.3 Summary of Backplane Requirements for Segment Type
Implementation
Table E02-T2 summarizes the PCI geography associated with each of the defined
Segment Types. Backplane system slots shall identify their Segment Type and
implement the geography of their associated peripheral slots in accordance with Table
E02-T2. Each segment of a pair of Stacked 3U segments shall individually comply with
the table. Legacy backplane segments and backplane segments that do not implement
one of the other defined Segment Types shall identify themselves as Segment Type
Unknown.
As shown in Table E02-T2, the physical slot number of the system slot (denoted N in the
table) is defined by GA[4..0] for Nominal segments. The physical slot number of the
closest distinct peripheral slot (denoted P in the table) is a function of N. Table E02-T2
also shows the ADxx line that is connected to each peripheral slot’s IDSEL pin.
Table E02-T2. PCI Geography Associated with Nominal Segments
Segment
Type
System/Auxiliary
Slot # (N)
Nominal
Right
N=GA[4..0]
Nominal
Left
ADxx Line Connected to
Each Peripheral Slot’s
IDSEL Pin
Peripheral Slot # as a Function of N,
Starting at the Closest Peripheral Slot #
(P), with Corresponding ADxx line
P=N+1 P+1 P+2 P+3 P+4 P+5 P+6
P=N-1 P-1 P-2 P-3 P-4 P-5 P-6
AD
31
AD
30
AD
29
AD
28
AD
27
AD
26
AD
25
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See Appendix C for examples of backplane configurations illustrating the use of the
Segment Types defined in Table E02-T2.
3.2.7.8.4 Software Access to Slot Geography Information
Slot geography data for backplane segments of a system (such as the GA[4..0] and
ST[1..0] data provided by backplane system slots, including both instances of that data
for dual system slots) should be accessible to software. Furthermore, this information
should be accessible via some hardware-independent mechanism to facilitate its use by
software, including platform-independent software.
One such hardware-independent mechanism makes use of the Vital Product Data (VPD)
feature defined in Revision 2.2 of the PCI Local Bus Specification. Chapter 6 provides
details of this approach. The slot geography of an entire backplane bus segment (if it
implements a defined Segment Type) may be described in VPD on the system slot board
for the segment. This description:
•would use a combination of the Location (LC) and PCI Geography (PG) VPD
keywords that are defined in Chapter 6.
•enables the use of physical slot numbers for peripheral slots and boards in the
segment without dependence on any support on the peripheral boards themselves
for access to geographic data.
The Chassis and Slot Number facilities defined in Chapter 13 of the PCI-to-PCI Bridge
Architecture Specification are motivated by similar goals for hardware-independent
access to PCI slot geography data. These facilities are not applicable to CompactPCI
backplane segments because they require that the first peripheral slot in a backplane
segment be selected by AD17, with sequentially greater slot numbers selected by
sequentially greater ADxx lines. These requirements conflict with the CompactPCI
conventions established by Table 7.
Minor Update to Section 4.1.9 Front Panels
Edit the 4 th paragraph on page 48 to clarify the requirements on physical slot
numbering.
Physical Slot locations within the subrack should be labeled with their physical slot
numbers, such that the labels are visible from the front (and rear if rear panel I/O is
utilized) of the subrack. Physical slot numbers should be placed within the compatibility
glyphs.
Section 5.8 Pin Assignments
In Tables 15 and 16, reallocate pins D21 and E21 in P2/J2 to ST1 and ST0,
respectively (both with note 20). Add Note 20.
Note 20. ST[1..0] in P2 shall identify the Segment Type of the backplane segment
created by this system slot. See Section 3.2.7.8 for details.
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New Chapter 6 Vital Product Data (VPD) Requirements
Add a new chapter for requirements regarding the content and updating of VPD.
6 Vital Product Data (VPD) Requirements
6.1 Overview of VPD
Vital Product Data (VPD) is defined in the PCI Local Bus Specification, Revision 2.2,
Appendix I. VPD provides an optional repository for read-only and/or read-write
information regarding PCI devices, supplementing the information in the Configuration
Space Header. For instance, board serial number and engineering change level can be
recorded.
VPD data (like all PCI data) uses a least significant byte first ordering. When four bytes
of VPD data have been transferred from a particular address in storage to a 32-bit
register, the least significant byte of that register contains the first byte at the designated
address.
VPD data is partitioned between read-only and read-write data. Writes to a read-only
area are implemented as no-ops by the hardware. The read-only area is protected by a
one-byte checksum after all the information fields. The checksum is correct if the sum of
all the bytes in the VPD from VPD address 0 up to and including the checksum byte is
zero.
Information fields in VPD consist of a three-byte header followed by some amount of
data (see Figure E02-F1). The three-byte header contains a two-byte keyword and a onebyte
length.
A keyword is a two-character (ASCII) mnemonic that uniquely identifies the information
in the field. The last byte of the header is binary and represents the length value (in
bytes) of the data that follows.
Keyword Length Data
Byte 0 Byte 1 Byte 2 Bytes 3 through n
Figure E02-F1. Layout of VPD Keywords
Appendix I also defines a specific set of keywords, grouped by whether they cover readonly
data or read-write data.
Later sections of this chapter define additional keywords beyond those defined by the
PCI-SIG, along with the data fields associated with each.
6.2 Slot Geography VPD Keyword Definitions
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6.2.1 “LC”—Board Location Keyword
This keyword identifies the location of a board in three dimensions:
• The slot number (SlotID) within a particular chassis or shelf in which the board is
installed.
• The shelf number (ShelfID) designating that chassis or shelf.
• The position (PosID) of the board within the slot (distinguishing for instance,
whether the board is a front board or a rear transition board).
CompactPCI boards may implement this keyword to make the above information
available to software in a hardware-independent way. If implemented, this keyword shall
be implemented in the read-only area of VPD and shall comply with the data field
definitions in this section. If necessary to comply with those definitions, fields shall be
updated by some board-specific means before the configuration space of a board is
enumerated by the operating system. Section 6.3.1 provides supplementary guidance on
the inputs and results of this update process.
The LC keyword has a minimum data length of 4 bytes and the field layout shown in
Table E02-T3.
Table E02-T3. Data Fields of the LC Keyword
Bits Name Definition
7-0 SlotID This 8-bit field is the system assigned SlotID. This field,
when used with the Shelf ID and Position ID, provides a
unique ID for each board in the system. The value of zero is
reserved for future use and the value of 255 indicates that no
SlotID is available. If there is more than one SlotID available
to this slot (presumably through distinct backplane
connectors), additional fields are available to record them
after the fixed part of this keyword data.
15-8 ShelfID This 8-bit field is the system assigned ShelfID. This field,
when used with the Slot ID and Position ID, provides a
unique ID for each board in the system. A field value of 255
indicates that no ShelfID is available.
18-16 Reserved Return 0 when read.
20-19 NumSlotIDs This 2-bit field indicates the number of supplementary SlotID
fields that follow the fixed part of this keyword data.
00 – indicates that no supplementary SlotID fields are present.
01 – indicates that one supplementary SlotID field is present.
10 – indicates that two supplementary SlotID fields are
present.
11 – Reserved.
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Bits Name Definition
23-21 PosID This 3-bit field indicates which position the board occupies in
the slot.
000 – indicates no Position ID information provided.
001 – indicates that the board is inserted in a front slot.
010 – indicates that the board is inserted in a rear slot.
011 – indicates that the board is inserted in a supplementary
rear slot (e.g. as a pallet bridge).
100 –> 111 – Reserved
31-24 NullCHK This 8-bit field is the 2’s complement of the checksum
difference resulting from any bytes of this keyword that are
updated from the system. This value ensures that the
checksum of the entire read-only portion of the VPD (which
was written to the VPD when the board was manufactured,
reflecting the VPD content at that time) remains valid.
0-2
additional
bytes
SuppSlotIDs
NumSlotIDs bytes, with each byte containing a
supplementary SlotID field, referenced as SuppSlotID1 and
SuppSlotID2, respectively. The interpretation of each of
these fields, if present, is identical to the interpretation of
SlotID.
Dual system slot boards implementing the LC keyword shall set NumSlotIDs = 1 and
include a SuppSlotID1 field. Section 6.3.1 specifies how the GA[4..0] fields in J2 and J5
are used to update the values of SlotID and SuppSlotID1 for the installation site of such
boards. SlotID not equal to SuppSlotID1 after updating indicates that the dual system
slot board is creating a pair of Stacked 3U backplane segments as detailed in section
3.2.7.8.2; the two SlotID fields are interpreted accordingly.
The LC keyword and its data would occur in VPD as the seven or more byte sequence in
Table E02-T4.
Table E02-T4. Byte Layout of LC Keyword and Data
Byte Field
Offset
0 “L” (most significant character of keyword)
1 “C” (least significant character of keyword)
2 0x04 + NumSlotIDs (length of data)
3 Bits 7-0 (SlotID)
4 Bits 15-8 (ShelfID)
5 Bits 23-16 (PosID, NumSlotIDs and Reserved
fields)
6 Bits 31-24 (NullCHK)
7 0-2 supplementary SlotIDs
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See Appendix C for example system configurations with corresponding concrete
instances of the LC keyword and its data.
Single system slot boards shall implement the NumSlotIDs field in the LC keyword with
a value of 0 and allocate no supplementary SlotID fields in the keyword data. Dual
system slot boards shall implement the NumSlotIDs field with a value of 1 and allocate
one supplementary SlotID field at the end of the keyword data.
6.2.2 “PG”—PCI Geography Keyword
This keyword defines the PCI geography of one or more segments of physical
CompactPCI slots created by the board on which the VPD is implemented.
Each segment of slots is bussed together and referenced by a single PCI logical bus
number. The combination of the logical bus number and the logical device number
uniquely identifies a specific CompactPCI board on a logical PCI bus (which may have
multiple bus segments, some of them implementing physical slots).
System slot boards may implement this keyword so that the slot geography of the
backplane segment(s) they create is accessible to software in a hardware-independent
way. If implemented, this keyword shall be implemented in the read-only area of VPD
and shall comply with the data field definitions in this section. If necessary to comply
with those definitions, fields shall be updated by some board-specific means before the
configuration space of a board is enumerated by the operating system. Section 6.3.2
provides supplementary guidance on the inputs and results of this update process.
The data area of this keyword begins with a NullCHK field to allow checksum correction
for any updates to other fields of the keyword to reflect the actual installation site of the
board. One or more Segment Descriptors follow the NullCHK field, each providing
geography data for one physical bus segment.
Table E02-T5 shows the overall layout of the data area for the PG keyword, which may
include multiple Segment Descriptors (each composed of an SD Header and an SD
Body). Table E02-T6 defines the fields of the 1-byte SD Header. A field in the Header
identifies the SD Type. One such SD Type is CompactPCI Backplane. Table E02-T7
defines the data fields of the 3-byte CompactPCI Backplane SD Body.
Table E02-T5. Overall Layout of Data Area for PG Keyword
Byte Name Description
Offset
0 NullCHK This 8-bit field is the 2’s complement of the checksum
difference resulting from any bytes of this keyword that are
updated from the system. Updates to partial byte fields must
be scaled according to their bit position for this calculation.
This value ensures that the checksum of the entire read-only
ADOPTED January 23, 2002 14

PICMG 2.0R3.0: ECN 2.0-3.0-002
1 SD Header
1
2 thru SD Body 1
4 + N
5 + N SD Header
2
6 + N thru SD Body 2
8 + N + M
portion of the VPD (which was written to the VPD when the
board was manufactured, reflecting the VPD content at that
time) remains valid.
The header byte for the first Segment Descriptor in this
keyword. See Table E02-T6 for details on this byte.
The body of the first Segment Descriptor in this keyword,
including an N-byte Slot Path following the 3-byte fixed size
area for a CompactPCI backplane SD Body. See Table E02-
T7 for details.
The header byte for the second Segment Descriptor in this
keyword. See Table E02-T6 for details on this byte.
The body of the second Segment Descriptor in this keyword,
including an M-byte Slot Path following the 3-byte fixed
size area for a CompactPCI backplane SD Body. See Table
E02-T7 for details.
9 + N + M … Additional Segment Descriptors if present.
Table E02-T6. Data Fields of an SD Header in a PG Keyword
Bits Name Description
0 AS Actual Segment – This 1-bit field indicates whether the
segment of physical slots associated with this Descriptor
actually exists (AS=1) or not (AS=0).
3-1 SDT Segment Descriptor Type – This 3-bit field indicates the
type of this Segment Descriptor. Each Segment Descriptor
Type has an associated SD Body definition with additional
fields appropriate to that type.
000 – CompactPCI Backplane segment. The corresponding
SD Body definition is provided in Table E02-T7.
001-111 – > Reserved.
7-4 SDS Segment Descriptor Size – This 4-bit field indicates the total
number of bytes in this Segment Descriptor, including this
header byte.
Table E02-T7. Data Fields of a CompactPCI Backplane SD Body
Bits Name Description
1-0 ST Segment Type – If AS=1, this 2-bit field indicates the type of a
CompactPCI backplane segment, based on the ST[1..0] field in
its system slot, as detailed in Section 3.2.7.8. The xxb values
of the two-pin ST[1..0] backplane field are directly mapped
into this 2-bit VPD field.
00 –Reserved.
01 – indicates a Nominal Left segment.
10 – indicates a Nominal Right segment.
11 – indicates an Unknown segment.
ADOPTED January 23, 2002 15

PICMG 2.0R3.0: ECN 2.0-3.0-002
Bits Name Description
2 Reserved Read as zero.
7-3 AC ADxx Constant – This 5-bit field provides the constant that is
combined with the PCI device number to determine xx and
thereby the ADxx line used to select a device on this segment.
8 AO ADxx Operator – This 1-bit field indicates whether a PCI
device number is added to (AO=1) or subtracted from (AO=0)
the ADxx Constant to determine xx on this segment. That is,
ADxx Operator determines “oper” in xx = ADxx Constant
oper Device Number.
10-9 SPS Slot Path Size – This 2-bit field indicates the number of levels
of PCI to PCI bridging that must be traversed to find the bus
that creates the physical slots and therefore the length of the
Slot Path that identifies that bus. The Slot Path, if present,
starts at offset 4 in this Segment Descriptor, immediately after
the first 4 bytes. The origin of the Slot Path is indicated by the
Host-Based (HB) field and is either the host of the on-board
PCI tree or the bridge associated with this VPD keyword.
00 – indicates that no bridging is required and no Slot Path is
present.
01 – indicates that one level of bridging occurs and a 1-byte
Slot Path provides the device / function number (5 bits /
3 bits respectively) for the bridge.
10 – indicates that two levels of bridging occur and a 2-byte
Slot Path provides the device / function number (5 bits /
3 bits respectively) for each bridge.
11 – indicates that three levels of bridging occur and a 3-byte
Slot Path provides the device / function number (5 bits / 3 bits
respectively) for each bridge.
11 HB Host-Based – This 1-bit field indicates whether the Slot Path
(if present) is relative to the local device (HR=0) or to the host
of the on-board PCI tree (HR=1). A Host-Based Slot Path is
typically used if VPD accessed from one bridge device
includes PCI geography data for a set of slots created by a peer
PCI bridge. A non-Host-Based Slot Path is typically used if the
bridge associated with this VPD keyword is a PCI parent of the
bridge that creates the physical slots.
13-12 CS Corresponding SlotID – This 2-bit field indicates the SlotID in
the LC keyword data to which this Segment Descriptor
corresponds.
00 – indicates the initial SlotID in the fixed LC keyword data.
01 – indicates the first supplementary SlotID (following the
fixed LC keyword data).
10 – indicates the second supplementary SlotID (following the
fixed LC keyword data).
11 – Reserved.
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PICMG 2.0R3.0: ECN 2.0-3.0-002
Bits Name Description
15-14 Reserved Read as zero.
20-16 CPD Co-located Peripheral Device – This 5-bit field provides a PCI
logical device number for a peripheral device co-located with
the system slot (that is, sharing the same physical slot), if this
backplane segment includes such a device. A value of 31
indicates that there is no such device on this segment. The
corresponding ADxx line selecting the co-located peripheral
slot is determined by the values of the AC and AO fields.
23-21 Reserved Read as zero.
Zero or
more
subsequent
bytes
SP
Slot Path – These bytes are only present if the SPS field
indicates a non-zero slot path size. Each byte identifies a PCI
to PCI bridge device by encoding the device number and
function number by which that bridge is accessed on its
primary bus. The device number is in bits 7..3. The function
number is in bits 2..0. Successive bytes identify bridges
successively further from the root of the PCI tree and closer to
a leaf bridge.
The PG keyword and its data would occur in VPD as the multi-byte sequence in Table
E02-T8.
Table E02-T8. Byte Layout of the PG Keyword and Data with a Single
CompactPCI Backplane Segment Descriptor
Byte Field
Offset
0 “P” (most significant character of keyword)
1 “G” (least significant character of keyword)
2 0x0X (length of data; 5 + additional bytes, if any)
3 NullCHK field for data in this keyword
4 SD Header (Segment Descriptor Size, Segment
Descriptor Type and Actual Segment fields)
5 SD Body Bits 7-0 (Segment Type, ADxx Constant
and Reserved fields)
6 SD Body Bits 15-8 (ADxx Operator, Host-Based,
Slot Path Size Corresponding SlotID and Reserved
fields)
7 SD Body Bits 23-16 (Co-located Peripheral
Device and Reserved fields)
8 & Slot Path if non-zero Slot Path Size.
following
ADOPTED January 23, 2002 17

PICMG 2.0R3.0: ECN 2.0-3.0-002
See Appendix C for example system configurations with corresponding concrete
instances of the PG keyword and its data.
6.3 Updating VPD Data to Reflect Board Installation Site
The PCI specification does not define the implementation of the VPD store, only the
configuration space interface. The implementation details of updating data in slotgeography-related
VPD keywords (based on the actual installation site of a board) are
inherently device-dependent. Appendix D sketches some possible approaches.
This section focuses on the content of VPD data updates, ignoring how those updates are
physically realized. The VPD keyword field values that are written into the VPD store
when a board is manufactured are considered static values, in contrast with the updated
values reflecting the actual installation site of the board.
Tables in this section provide the following types of guidance for each field of
geographic keyword data:
• Updated Field Value Based on Board Install Site − This item is a suggested
arithmetic or logical expression providing an updated value for the field. If
the result of the expression is “NO-UPDATE”, the assumed static value is not
updated at all.
The updated value of the NullCHK field for a keyword can be affected by any
updates to static field values for that keyword. NullCHK is calculated to
exactly offset the impacts of updates, if any, to the static content of the other
data fields of that keyword. This is necessary to preserve the correctness of
the checksum for the overall VPD read-only area that is calculated and written
at the end of the read-only area based on the static field values.
The update expressions for the NullCHK field have the form: “-(…)[7..0]”,
which means “the least significant 8 bits of the two’s complement of the
expression in the parentheses”.
• Assumed Static Value − If the static value of a field is different from the
assumed value, then other aspects of the update guidance may need to change
accordingly. For simplicity in expressing NullCHK calculation guidance in
the tables of this section, fields that are likely to be updated have an assumed
static value of 0.
• Notes − Supplementary comments, where appropriate.
6.3.1 Updating LC Keyword Data
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PICMG 2.0R3.0: ECN 2.0-3.0-002
Typically, the SlotID, SuppSlotID1 (for a dual system slot board) and possibly the
ShelfID can be determined from the backplane slot in which the board is installed. These
VPD fields have more bits than the corresponding currently defined backplane fields.
The extra bits allow wider backplane fields to be defined in the future without impacting
software that processes the VPD data.
PosID can typically be determined statically, based on the intrinsic design of the board.
In the table below, all numbers are decimal numbers.
Table E02-T9. LC Keyword Data—Update Guidance
Field Updated Field Value Based on
Board Install Site
Notes Assumed Static
Value
SlotID IF GA[4..0] J2 = 31 THEN 255 1 0
ELSE GA[4..0] J2
ShelfID For boards with SGA DEFINED:
IF (SGA[4..0] ≠ 31) THEN
SGA[4..0] ELSE 255
For boards with SGA not
DEFINED: NO-UPDATE
2 For boards with
SGA
DEFINED: 0
For boards with
SGA not
DEFINED: 255
PosID No update necessary Set to final
NullCHK For boards with SGA DEFINED:
- (SlotID + ShelfID +
SuppSlotID1)[7..0]
For boards with SGA not
DEFINED:
- (SlotID + SuppSlotID1)[7..0]
SuppSlotID1 IF GA[4..0] J5 = 31 THEN 255
ELSE GA[4..0] J5
value
3 0
1, 4 0
Notes:
1. The special value 31 defined by Section 3.2.7.6 for the 5-bit GA[4..0] field is
translated to the 8-bit SlotID field as 255.
2. It is assumed that a board is intrinsically designed for slots that define SGA[4..0] pins
or not. Therefore, whether the ShelfID field should be updated from SGA[4..0] is
DEFINED (or known at the time a board is designed). Among the types of slots that
define SGA[4..0] pins are PICMG 2.5 Computer Telephony slots, PICMG 2.16
Fabric Slots, and PICMG 2.17 Fabric & Node slots. If SGA[4..0] is not DEFINED or
SGA[4..0]=31, the ShelfID field must have a value of 255, which indicates that no
ShelfID is available. System integrators are responsible for addressing the potential
confusion when ShelfID is not available to distinguish between two boards in the
same physical slot number of distinct shelves or chassis.
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PICMG 2.0R3.0: ECN 2.0-3.0-002
3. Assumes that the static values of SlotID and ShelfID are zero and that PosID is: 1)
static and 2) not updated at board install time. If SGA is not DEFINED, ShelfID is
omitted from the NullCHK calculation. On single system slot boards, SuppSlotID1 is
not defined; therefore it must be excluded from the NullCHK calculation.
4. The SuppSlotID1 field always exists on a dual system slot board. Its updated value is
based on the GA field in J5, using effectively the same update expression as for the
GA field in J2. When implemented, SuppSlotID1 is included in the NullCHK
calculation; otherwise, it is excluded from that calculation.
6.3.2 Updating PG Keyword Data
The Actual Segment (AS) field probably needs to be updated to reflect the actual system
slot. AS should only be set to 1 in a Segment Descriptor that corresponds to an actual
physical segment. When a system slot capable board is installed in a peripheral slot or a
slot that doesn’t implement the CompactPCI bus, AS should have a value of 0. PICMG
2.16, CompactPCI Packet Switching Backplane Specification, and PICMG 2.17
CompactPCI StarFabric Specification provide for installing boards that implement a
CompactPCI bus on J1 + J2 into backplanes that don’t implement that bus. A special
signal, PCI_PRESENT#, indicates to the board that a CompactPCI bus is implemented on
the slot in which it is installed. CompactPCI system slots assert the SYSEN# signal,
while peripheral slots do not assert SYSEN#. The PCI_PRESENT# and SYSEN#
signals should be used to update AS appropriately.
Table E02-T10 provides specific guidance for updating the above fields. All numbers in
the table are decimal numbers unless specifically indicated otherwise.
There is only one NullCHK field for each PG keyword, even if that keyword contains
more than one Segment Descriptor. That single NullCHK field must compensate for
checksum impacts of all the Segment Descriptors in a keyword that are updated from
their static values.
Table E02-T10. PG Keyword Data—Update Guidance
Field Update Based on Board Install Site Notes Assumed
Static
Value
NullCHK - (AS + ST)[7..0] 1 0
Actual PCI_PRESENT# AND SYSEN# 2 0
Segment (AS)
Segment Type IF SYSEN# THEN ST[1..0] ELSE 3 0
(ST)
11b
ADxx
Constant (AC)
Fixed by the implementation of the
system slot board and therefore static,
16
ADxx
Operator (AO)
usually 16; see Section 3.1.10
Fixed by the implementation of the
system slot board and therefore static,
1
ADOPTED January 23, 2002 20

PICMG 2.0R3.0: ECN 2.0-3.0-002
Field Update Based on Board Install Site Notes Assumed
Static
Value
usually 1; see Section 3.1.10
Slot Path Size
(SPS)
No update necessary 4 Set to
final value
Host-Based
(HB)
No update necessary 4 Set to
final value
Corresponding No update necessary 5 Set to
SlotID (CS)
Co-located
Peripheral
Device (CPD)
final value
No update necessary 6 Set to
final value
Slot Path (SP) No update necessary 4 Set to
final value
Notes:
1. Assumes static values of zero for AS and ST, with no other fields changed from their
static values. Also assumes that this PG keyword has only a single Segment
Descriptor. For PG keywords that have multiple Segment Descriptors, the update
expression for NullCHK will likely need to include multiple instances of fields such
as AS and ST.
2. The pin assigned to PCI_PRESENT# is defined as GND in R3.0 and earlier revisions
of this specification, so this signal defaults to an active value for backplanes that predate
the definition of this signal.
3. If the installation site is a system slot, the value of the ST[1..0] backplane field can go
directly into the ST field of the SD Body. Otherwise, the ST field in the SD Body is
set to 11b.
4. Slot path properties associated with the bridge that creates the backplane segment are
inherent properties of the system slot board’s design; no update at board install time is
applicable.
5. CS statically identifies the backplane segment created by the board that is specified
by this Segment Descriptor. When CS=0, it is the segment created by J1/J2. When
CS=1 (which only occurs on dual system slot boards), it is the segment created by
J4/J5. References to backplane fields (ST[1..0], PCI_PRESENT#, or SYSEN#) in the
update expressions of this table refer to J1/J2 if CS=0 and to J4/J5 if CS=1.
6. The system slot board (say, a pallet bridge) that creates the co-located peripheral slot
determines what ADxx signal is routed to IDSEL of the peripheral slot and the AC
and AO fields determine how the CPD value in this field maps to ADxx. No update
at board install time is applicable.
Add New Appendix C. Self-Describing Geography Examples
This appendix provides several examples of backplane configurations and how
Segment Types in system slots and VPD Keywords implemented on system slot
ADOPTED January 23, 2002 21

PICMG 2.0R3.0: ECN 2.0-3.0-002
boards can be used to describe the geography of the backplane segments in
these configurations.
Appendix C. Self-Describing Geography Examples
This section applies this specification to example backplane and system slot board
definitions to clarify implementation issues.
C.1 Backplane Examples
The following examples graphically represent the slots in a CompactPCI backplane, with
system slots indicating the geographic address and segment type reported by the GA[4..0]
and ST[1..0] pins, respectively. The table under the slot designators provides the binary
form of the geographic address and indicates the ADxx line that is connected to the
IDSEL pin for each peripheral slot.
The first six examples are applicable to either 3U or 6U slots/boards. The first two of
those show 8-slot backplanes with the system slots on the right and left, respectively.
1 2 3 4 5 6 7 8
00001
AD25
00010
AD26
00011
AD27
00100
AD28
00101
AD29
Nominal Left Segment
00110
AD30
00111
AD31
GA 01000 ST 01
P2
Figure E02-F2. 8-Slot Backplane with System Slot on Right
1
2 3 4 5 6 7
8
00010
AD31
00011
AD30
00100
AD29
00101
AD28
00110
AD27
00111
AD26
01000
AD25
P2
ST 10
GA 00001
Nominal Right Segment
Figure E02-F3. 8-Slot Backplane with System Slot on Left
The next two examples show smaller slot count backplanes, again with the system slots
on the right and left, respectively.
ADOPTED January 23, 2002 22

PICMG 2.0R3.0: ECN 2.0-3.0-002
1
2 3 4
5
00001
AD28
00010
AD29
00011
AD30
00100
AD31
Nominal Left Segment
GA 00101 ST 01
P2
Figure E02-F4. 5-Slot Backplane with System Slot on Right
1
P2
ST 10
2 3 4
00010
AD31
00011
AD30
GA 00001
00100
AD29
Nominal Right Segment
Figure E02-F5. 4-Slot Backplane with System Slot on Left
The next two examples cover configurations addressed in PICMG 2.6. The first example,
Figure E02-F6, implements a 14-slot backplane with two segments. The second segment
(with physical slot number 9 as the system slot) is intended to be created by a two-slot
front bridge board set. One of the boards in the set occupies slot 8 as a peripheral slot
board. The other board in the set occupies slot 9 as a system slot board. The two boards
are connected by some proprietary means and one of them includes a PCI-to-PCI bridge.
Figure E02-F7 shows how this set would install into the backplane. See PICMG 2.6 for
additional background and details.
1
2 3 4 5
6 7 8 9 10 11 12 13
14
00010
AD31
00011
AD30
00100
AD29
00101
AD28
00110
AD27
00111
AD26
01000
AD25
01001
01010
AD31
01011
AD30
01100
AD29
01101
AD28
01110
AD27
P2
ST 10
Nominal Right Segment
GA 00001
P2
P2
Nominal Right Segment
ST 10
GA 01001
Figure E02-F6. 14-Slot Backplane with System Slot on Left and Front-Bridged Extension
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PICMG 2.0R3.0: ECN 2.0-3.0-002
Figure E02-F7. Top View of Two-Board Front Bridge Assembly (Left) and Backplane Slots (Right)
The second example motivated by PICMG 2.6, Figure E02-F8, also implements a 2-
segment, 14-slot backplane, but bridging between the segments is accomplished via a
pallet bridge module that installs on the rear of the backplane. Slot 8 implements a colocated
peripheral slot, with the system slot function provided by a pallet bridge module
on the rear of the backplane. Figure E02-F9 shows the top and rear view of this
installation. See PICMG 2.6 for additional background and detail.
1
2 3 4 5
6 7 8 9 10 11 12 13
14
00010
AD31
00011
AD30
00100
AD29
00101
AD28
00110
AD27
00111
AD26
01000
AD24
01001
AD31
01010
AD30
01011
AD29
01100
AD28
01101
AD27
01110
AD26
Nominal Right Segment
Nominal Right Segment
P2
ST 10
GA 00001
Connection for
Rear Pallet Bridge
P2
ST 10
GA 01000
Figure E02-F8. 14-Slot Backplane with System Slot on Left and Pallet-Bridged Extension
ADOPTED January 23, 2002 24

PICMG 2.0R3.0: ECN 2.0-3.0-002
Figure E02-F9. Top View (Above) and Rear View (Below) of Installed Pallet Bridge
The next example shows a 15-slot backplane in which a dual system slot creates
backplane segments to its left and right.
Nominal Left
Segment
GA 01000
ST 01
P5
. . .
GA 01000
ST 10
Nominal Right
Segment
00001
AD25
00010
AD26
00011
AD27
00100
AD28
00101
AD29
00110
AD30
00111
AD31
P2
01001
AD31
01010
AD30
01011
AD29
01100
AD28
01101
AD27
01110
AD26
01111
AD25
1 2 3 4 5 6 7 8
9 10 11 12 13 14
15
Figure E02-F10. Dual 6U Segment Backplane
The next three examples show backplanes that implement two 3U segments one above
the other. In the first two examples, the segments are Stacked 3U segments created by a
dual system slot (on the right and the left, respectively). The third example has two
independent 3U segments, where each segment has a separate 3U system slot.
ADOPTED January 23, 2002 25

PICMG 2.0R3.0: ECN 2.0-3.0-002
Nominal Left
Segment
Nominal Left
Segment
1
00001
AD25
01000
AD25
8
2 3 4 5 6 7
00010
AD26
01001
AD26
00011
AD27
01010
AD27
00100
AD28
01011
AD28
00101
AD29
01100
AD29
00110
AD30
01101
AD30
00111
AD31
01110
AD31
9 10 11 12 13 14
15
P5
. . .
P2
GA A 01000
ST 01
GA 01111
ST 01
Figure E02-F11. Dual Stacked 3U Segments with Single 6U System Slot on Right
GA 00001
ST 10
GA A 01000
ST 10
P5
. . .
P2
1
2 3 4 5 6 7 8
00010
AD31
01001
AD31
00011
AD30
01010
AD30
00100
AD29
01011
AD29
00101
AD28
01100
AD28
00110
AD27
01101
AD27
00111
AD26
01110
AD26
9 10 11 12 13 14
01000
AD25
01111
AD25
15
Nominal Right
Segment
Nominal Right
Segment
Figure E02-F12. Dual Stacked 3U Segments with Single 6U System Slot on Left
GA 00001
ST 10
GA 01001
ST 10
P5
. . .
P2
1
9
2 3 4 5 6 7 8
00010
AD31
01010
AD31
00011
AD30
01011
AD30
00100
AD29
01100
AD29
00101
AD28
01101
AD28
00110
AD27
01110
AD27
00111
AD26
01111
AD26
10 11 12 13 14 15
01000
AD25
10000
AD25
16
Nominal Right
Segment
Nominal Right
Segment
Figure E02-F13. Independent 3U Segments with Two 3U System Slots on Left
C.2 System Slot Board Examples
The following figures sketch specific system slot boards and show the corresponding slot
geography data that would be stored in LC and PG keywords in VPD when the board is
manufactured (that is, the static VPD data). Each figure contains three areas. On the left
are the fields for the Location and PCI Geography keywords with their decimal values.
On the upper right is a diagram that represents the board layout and location of the VPD
ADOPTED January 23, 2002 26

PICMG 2.0R3.0: ECN 2.0-3.0-002
data store (denoted by “VPD+” because it includes both the VPD store and any necessary
additional logic to update VPD for the board install site). PCI device numbers of PCI-to-
PCI bridges are shown when needed, in decimal. The area on the bottom right is the
static VPD data for the LC and PG keywords in hexadecimal. Dual system slot boards
have a Segment Descriptor (SD) for each backplane segment, with the static fields for the
J1/J2 SD and J4/J5 SD on the left and right, as indicated by the labels.
The example boards include:
• A typical system slot board that can create one backplane segment through J1/J2.
This board could be implemented in either a 3U or 6U size.
• Several dual system slot boards that can create a backplane segment through each
of J1/J2 and J4/J5. The example boards vary in how the on-board bridging and
associated VPD stores are implemented.
A table follows each figure. Each row of the table indicates the updated slot geography
data that results when the board in the figure above is installed in various slot positions in
the example backplanes (with the backplane identified by figure number). The updated
values of the individual fields are shown in unsigned decimal, along with a hexadecimal
representation of the updated slot geography data as it would be read from an installed
board.
The example system slot boards are designed for chassis in which Shelf Geographic
Address support is not available. As a result, all ShelfID fields have a static value of 255.
ADOPTED January 23, 2002 27

PICMG 2.0R3.0: ECN 2.0-3.0-002
LC
PG
SlotID 0
ShelfID 255
PosID 1
NumSlotIDs 0
NullCHK 0
NullCHK 0
AS 0
SDT 0
SDS 4
ST 0
AC 16
AO 1
ST 0
SPS 0
HB 0
CS 0
CPD 31
SP
CPU
PCI Host Bridge
P2P
VPD+
ST
GA
Board Boundary
for 3U Boards
Static VPD (Single)
4C 43 04 00 FF 20 00 50 47 05 00 40 80 01 1F
Figure E02-F14. Single System Slot Board (6U or 3U Size)
Table E02-T11. Updated Single System Slot Board VPD
Install Site
Figure E02-F2,
slot 8
Figure E02-F3,
slot 1
Figure E02-F4,
slot 5
Figure E02-F5,
slot 1
Figure E02-F6,
slot 1
Figure E02-F6,
slot 9
Figure E02-F8,
slot 1
Figure E02-F13,
slot 1
Figure E02-F13,
slot 9
Updated LC
Keyword
Fields
Slot
ID
Null
CHK
Updated PG Keyword
Fields
Null
CHK
Segment
Descriptor
AS ST
8 248 254 1 1
1 255 253 1 2
5 251 254 1 1
1 255 253 1 2
1 255 253 1 2
9 247 253 1 2
1 255 253 1 2
1 255 253 1 2
9 247 253 1 2
Updated VPD for LC and PG
Keywords
4C 43 04 08 FF 20 F8 50
47 05 FE 41 81 01 1F
4C 43 04 01 FF 20 FF 50
47 05 FD 41 82 01 1F
4C 43 04 05 FF 20 FB 50
47 05 FE 41 81 01 1F
4C 43 04 01 FF 20 FF 50
47 05 FD 41 82 01 1F
4C 43 04 01 FF 20 FF 50
47 05 FD 41 82 01 1F
4C 43 04 09 FF 20 F7 50
47 05 FD 41 82 01 1F
4C 43 04 01 FF 20 FF 50
47 05 FD 41 82 01 1F
4C 43 04 01 FF 20 FF 50
47 05 FD 41 82 01 1F
4C 43 04 09 FF 20 F7 50
47 05 FD 41 82 01 1F
ADOPTED January 23, 2002 28

PICMG 2.0R3.0: ECN 2.0-3.0-002
LC
PG
SlotID 0
ShelfID 255
PosID 1
NumSlotIDs 1
NullCHK 0
SuppSlotID1 0
NullCHK 0
AS 0 AS 0
SDT 0 SDT 0
SDS 4 SDS 5
ST 0 ST 0
AC 16 AC 16
AO 1 AO 1
SPS 0 SPS 1
HB 0 HB 1
CS 0 CS 1
CPD 31 CPD 31
SP SP 88
J1/J2 SD
J4/J5 SD
CPU
PCI Host Bridge
Dev 8
P2P
ST J2
VPD+
GA J2 GA J5 ST J5
Dev 11
P2P
Static VPD (Single)
4C 43 05 00 FF 28 00 00 50 47 0A 00 40 80 01
1F 50 80 1B 1F 58
Figure E02-F15. Dual System Slot, Single VPD
Table E02-T12. Updated Dual System Slot, Single VPD
Install Site
Figure E02-
F10, slot 8
Figure E02-
F11, slot 15
Figure E02-
F12, slot 1
Updated LC Keyword
Fields
Slot
ID
SuppSlot
ID1
Null
CHK
Null
CHK
Updated PG Keyword Fields
J2 Segment
Descriptor
J5 Segment
Descriptor
AS ST AS ST
8 8 240 251 1 1 1 2
15 8 233 252 1 1 1 1
8 1 247 250 1 2 1 2
Updated VPD for LC and
PG Keywords
4C 43 05 08 FF 28 F0
08 50 47 0A FB 41 81
01 1F 51 82 1B 1F 58
4C 43 05 0F FF 28 E9
08 50 47 0A FC 41 81
01 1F 51 81 1B 1F 58
4C 43 05 08 FF 28 F7
01 50 47 0A FA 41 82
01 1F 51 82 1B 1F 58
ADOPTED January 23, 2002 29

PICMG 2.0R3.0: ECN 2.0-3.0-002
LC
PG
SlotID 0
ShelfID 255
PosID 1
NumSlotIDs 1
NullCHK 0
SuppSlotID1 0
NullCHK 0
AS 0
SDT 0
SDS 4
ST 0
AC 16
AO 1
SPS 0
HB 0
CS 0
CPD 31
SP
J1/J2 SD
NullCHK 0
AS 0
SDT 0
SDS 4
ST 0
AC 16
AO 1
SPS 0
HB 0
CS 1
CPD 31
SP
J4/J5 SD
CPU
PCI Host Bridge
Dev 8
P2P
VPD+
VPD+
ST J2 GA J2 GA J5 ST J5
Dev 11
P2P
Static VPD (Dual; J5 PG Keyword Separate)
4C 43 05 00 FF 28 00 00 50 47 05 00 40 80 01 1F
50 47 05 00 40 80 11 1F
Figure E02-F16. Dual System Slot Board, Dual VPD w/ Separate J5 PG Keyword
Table E02-T13. Updated Dual System Slot Board, Dual VPD
Install Site
Figure E02-
F10, slot 8
Figure E02-
F11, slot 15
Figure E02-
F12, slot 1
Updated LC Keyword
Fields
Slot
ID
SuppSlot
ID1
Null
CHK
8 8 240
15 8 233
8 1 247
Null
CHK
254
253
254
254
253
253
Updated PG Keyword Fields
J2 Segment
Descriptor
J5 Segment
Descriptor
AS ST AS ST
1 1 1 2
1 1 1 1
1 2 1 2
Updated VPD for LC and PG
Keywords (w/ PG Keyword
for J5 Separate)
4C 43 05 08 FF 28 F0
08 50 47 05 FE 41 81
01 1F
50 47 05 FD 41 82 11
1F
4C 43 05 0F FF 28 E9
08 50 47 05 FE 41 81
01 1F
50 47 05 FE 41 81 11
1F
4C 43 05 08 FF 28 F7
01 50 47 05 FD 41 82
01 1F
50 47 05 FD 41 82 11
1F
ADOPTED January 23, 2002 30

PICMG 2.0R3.0: ECN 2.0-3.0-002
LC
PG
SlotID 0
ShelfID 255
PosID 1
NumSlotIDs 0
NullCHK 0
SuppSlotID1 1
NullCHK 0
AS 0 AS 0
SDT 0 SDT 0
SDS 5 SDS 5
ST 0 ST 0
AC 16 AC 16
AO 1 AO 1
SPS 2 SPS 2
HB 1 HB 1
CS 0 CS 1
CPD 31 CPD 31
SP 160 SP 160
64
J1/J2 SD
88
J4/J5 SD
CPU
Dev 8
Dev 20
P2P
PCI Host Bridge
P2P
VPD+
ST J2 GA J2 GA J5 ST J5
P2P
Static VPD (Single)
Dev 11
4C 43 05 00 FF 28 00 00 50 47 0D 00 20 80 0D
1F A0 40 20 80 1D 1F A0 58
Figure E02-F17. Dual System Slot, Single VPD on Parent Bridge
Table E02-T14. Updated Dual System Slot, Single VPD on Parent Bridge
Install Site
Figure E02-
F10, slot 8
Figure E02-
F11, slot 15
Figure E02-
F12, slot 1
Updated LC Keyword
Fields
Slot
ID
SuppSlot
ID1
Null
CHK
Null
CHK
Updated PG Keyword Fields
J2 Segment
Descriptor
J5 Segment
Descriptor
AS ST AS ST
8 8 240 251 1 1 1 2
15 8 232 252 1 1 1 1
8 1 246 250 1 2 1 2
Updated VPD for LC and PG
Keywords
4C 43 05 08 FF 28 F0
08 50 47 0D FB 21 81
0D 1F A0 40 21 82 1D
1F A0 58
4C 43 05 0F FF 28 E9
08 50 47 0D FC 21 81
0D 1F A0 40 21 81 1D
1F A0 58
4C 43 05 08 F0 28 F7
01 50 47 0D FA 21 82
0D 1F A0 40 21 82 1D
1F A0 58
ADOPTED January 23, 2002 31

PICMG 2.0R3.0: ECN 2.0-3.0-002
LC
PG
SlotID 0
ShelfID 255
PosID 3
NumSlotIDs 0
NullCHK 0
NullCHK 0
AS 0
SDT 0
SDS 4
ST 0
AC 16
AO 1
SPS 0
HB 0
CS 0
CPD 8
SP
Connections to rear of P1/P2
Primary Bus
P2P
Static VPD (Single)
VPD+
Secondary
Bus
4C 43 04 00 FF 60 00 50 47 05 00 40 78 01 08
GA
ST
Figure E02-F18. Pallet Bridge
Table E02-T15. Updated Pallet Bridge VPD
Install Site
Figure E02-F8,
slot 8
Updated LC
Keyword
Fields
Slot
ID
Null
CHK
Updated PG
Keyword Fields
Null
CHK
Segment
Descriptor
AS ST
8 248 253 1 2
Updated VPD for LC and PG
Keywords
4C 43 04 08 FF 60 F8 50
47 05 FD 41 82 01 08
Add New Appendix D. Example Implementations of Updating Onboard
VPD Keyword Data Based on Backplane Information.
This appendix provides example implementations of ways to update VPD
keyword data, based on data detected by a board from the backplane after it is
powered up.
Appendix D. Example Implementations of Updating VPD Keyword
Data
The PCI specification leaves the implementation details of the VPD store up to the PCI
device developer, defining only the registers in PCI configuration space through which
VPD data is accessed. Typical VPD implementations use a serial EEPROM
(SEEPROM) as the VPD store. Each PCI device that supports VPD in this way typically
requires a specific SEEPROM interface.
Some PCI bridges with VPD support, such as the Tundra Semiconductor Corp.’s Tsi320
and Tsi85x (see www.tundra.com), for example, use an I 2 C-accessed SEEPROM. Other
VPD-aware PCI bridges, such as HiNT Corporation’s HBx (see www.hintcorp.com),
ADOPTED January 23, 2002 32

PICMG 2.0R3.0: ECN 2.0-3.0-002
Intel Corporation’s 2155x (see www.intel.com) and StarGen, Inc.’s SG2010 (see
www.stargen.com) devices, use the Serial Peripheral Interface (SPI). One company that
produces SEEPROMs with either I 2 C- or SPI-based interfaces is Microchip Technology
Inc. (see www.microchip.com).
The details of how the geography-related keyword data VPD could be updated based on
the installation site of a board are entirely implementation specific. This appendix
sketches two implementation approaches, one for I 2 C-accessed SEEPROMs and the other
for SPI-accessed SEEPROMs. For simplicity, the sketches cover only updates to the LC
(Board Location) keyword fields. Updates to the PG (PCI Geography) keyword fields
can be handled in a similar fashion.
A.1 Implementation Sketch: Updating VPD Data in I 2 C-accessed
SEEPROMs
Consider a system slot board that:
•Creates a backplane segment via a PCI bridge that accesses its VPD store via I 2 C.
•Also includes an I 2 C-capable Management Controller (MC) as described in
PICMG 2.9.
In addition to its primary function of facilitating manageability of the board, the MC
could also support updates of the VPD store to reflect backplane specifics with minimal
incremental cost.
Assume that the VPD SEEPROM is accessible via a private I 2 C bus from the MC and
that the MC can temporarily hold off initialization of the PCI bridge. Further assume that
the MC has access to the geography-related fields in the backplane: GA[4..0], ST[1..0]
and SGA[4..0] if defined. (In PICMG 2.9, the MC already uses GA[4...0] to establish its
slave address on the Intelligent Platform Management Bus (IPMB).)
At board startup, while the PCI bridge is held off, the MC could retrieve geography data
from the backplane, then access the SEEPROM via I 2 C to update the appropriate fields of
the location information stored there. Any access to VPD via the PCI bridge after it
comes out of reset would retrieve the updated information. In fact, a single MC could
perform this service for multiple VPD SEEPROMs on the board if necessary.
A.2 Implementation Sketch: Updating VPD Data in SPI-accessed
SEEPROMs
Another potential implementation could use a special CPLD interposed between the PCI
bridge that creates the peripheral slots and an SPI-based SEEPROM that implements the
bridge’s VPD store. The CPLD could substitute updated location information when the
LC keyword data in the read-only VPD space is accessed from the bridge. Figure E02-
F19 shows a simple schematic.
ADOPTED January 23, 2002 33

PICMG 2.0R3.0: ECN 2.0-3.0-002
Figure E02-F19. Potential Implementation for VPD Content Update with SPI
SEEPROM
This design could potentially be applied to any PCI bridge that uses the Serial Peripheral
Interface (SPI) SEEPROM bus interface for its VPD store. The CPLD accesses the
backplane pins that indicate the specific slot number and shelf number in which this
system slot board is installed. For PICMG 2.0, PICMG 2.5, PICMG 2.16 and PICMG
2.17 backplanes, these are the 5-pin GA and SGA fields, shown as inputs to the CPLD
from the right.
The CPLD intercepts the serial bit stream of the SEEPROM and updates the location
information in the VPD with the geographical data from the backplane in the bit stream
provided to the PCI bridge. In this example, we assume that the PosID field in VPD is
set statically because a particular board in CompactPCI works only in one of the defined
positions. Therefore, only the SlotID, ShelfID and NullCHK bytes (the first, second and
fourth bytes of the LC keyword data) need to be updated.
The CPLD makes the following assumptions and implements the following
functionality/features:
Assumptions:
o The 3 bytes of location information in the SEEPROM that will be updated have
static values of zero.
o The address in the SEEPROM of the location keyword is known.
Features:
o Interprets Serial Peripheral Interface (SPI) bus traffic.
ADOPTED January 23, 2002 34

PICMG 2.0R3.0: ECN 2.0-3.0-002
o Implements an 8-bit instruction register.
o Implements a 16-bit address register/counter.
o Keeps track of the current address.
o Updates the LC keyword data with 10 bits of data based on the GA and SGA
inputs (5 bits each, placed appropriately in two 8-bit fields).
o Generates the 8-bit NullCHK value that is used to adjust the checksum that covers
the read-only portion of VPD. The NullCHK value is the 2’s complement of the
sum of the two updated bytes of location information.
The CPLD only drives SDO when the SEEPROM is being read. Otherwise, the CPLD
tri-states its SDO pin. The CPLD tracks all accesses to the SEEPROM (reads and
writes).
Here is a walk through of a read access:
1. The PCI bridge accesses the SEEPROM, which is indicated by the assertion of
chip select.
2. The CPLD loads its 8-bit instruction register.
3. The CPLD loads its 16-bit address register/counter.
4. If the address does not match the address of the location information, the CPLD
passes the serial data from the SEEPROM to the PCI bridge.
If the address matches the address of the location information, the CPLD replaces the
location information coming out of the SEEPROM with updated data based on the GA
and SGA inputs, plus the appropriate NullCHK data.
###
ADOPTED January 23, 2002 35