Dark Energy Survey - Department of Physics - The Chinese ...

Design of Emulator for Testing the Image Acquisition from the
520 Megapixel CCD Camera in Dark Energy Survey
Cheuk-yui Leung
2 nd September 2006
1) Introduction
In the project dark Energy survey, a 520 megapixel Charged-Coupled device (CCD)
camera will be built at Cerro Tololo Inter-American Observatory. University of Illinois
designs and builds the data acquisition system while Lawrence Berkeley National
laboratory (LBNL) designs CCDs. The image acquisition system is to be tested and
debugged before LBML CCDs are ready. Hence, Circuit boards with field
programmable gate array (FPGA) called emulators are designed to emulate CCDs.
2) Background
2.1) Data transferring mode from CCDs
Fig.1 shows a CCD schematically. Each CCD consists of 2048 x 4096 pixels. There is
one line of horizontal shift register at the bottom of the CCD board. The CCD is divided
into two parts. The right half named ‘lower’ and the left named ‘higher’. There are
output gates at the bottom right (lower output) and left (upper output) of the CCD
alternatively.
When the pulses representing the vertical shift command are sent to the CCD board, the
pulse signals will be checked. The correct sequence of pulse is show in Fig.2. If the
signals are correct, the memory stored in the lowest row of pixels will be shifted to the
horizontal shift register. Memory stored in the second lowest row will be shifted to the
lowest row, etc.
When the pulses representing the horizontal shift command are sent to the ‘upper’
horizontal input of CCD board, the pulse signals will be checked. The correct sequence
of pulse is shown in Fig.3. If the signals are correct, the most left memory bit of the
horizontal shift register in ‘upper’ will be shifted to the detector on the left. The
information of that memory will then be transmitted away. The second most left
memory will shift left, etc. ‘Lower’ also works in the same way except the memories in
the shift register are shifted right.
Vertical signals and horizontal signals are inputted alternatively until all information
stored in the CCD is transmitted away.

3) Programming of FPGA
3.1) Some facts about the emulator
Altera Cyclone II chips are used in the circuit for the emulator and the software Quantus
II is used to program the chips. Each chip contains 64 x 64 points of memory. By
repeating it over and over, we can emulate the whole 2048 x 4096 pixels CCD. That
means if we program the database of emulator like the star in Fig 15, we expect to
emulate the CCD like Fig 16, with Fig 15 repeat over and over.
Hence, the address of each emulated pixel is assigned with 12 bits, while the first 6 bits
represent the row number and the last 6 bits represent the column number. 8 bits of
memory are assigned to each pixel.
The program is mainly divided into input of pulse, checking of pulse and output of data.
The outlook is shown in Fig 4, 5 and 6 respectively.
The vertical shift checking system is clocked with period of 100.0ns. Both the upper
and lower horizontal shift checking systems are clocked with period of 10.0ns.
3.2) The idea of checking pulse
When the pulses representing a vertical shift or horizontal shift are being input, the
signal is checked.
There are 5 inputs of pulses for the vertical shift, which are TG, V1, V2, V3, TRIGOUT
respectively. There are also 5 inputs for the Horizontal inputs respectively, which are RG,
H1, H2, H3, SW respectively. Please refer to Fig 2 and 3 for the correct sequence of
input pulses.
The pulses are checked at the edges where their signals are changed. Take the V1 input
of the vertical shift input as example. The signal changes at 60.4us and 121.2us. To
ensure the input signal change at 60.4us, we use an AND gate to check if the signal at
58.0us (signal = 1) and the inverse of signal at 62.0us (the signal = 0, the inverse should
be 1) are the same. All other edges of pulses are checked in the same way. If the signals
in V1, Y2, V3, TRIGOUT are correct, the signal of the output GOOD VERTICAL will
be changed from 0 into 1 until the next set of pulses are being input.
The same procedure also applies to the checking system of upper and lower horizontal
shift. The only difference is that the names of the output are GOOD UPPER
HORIZONTAL and GOOD LOWER HORIZONTAL. And the outputs will become
high only for 20 ns. At this 20ns, data will be read from the database and will become

the output. A state machine is used to control the checking of signals.
3.3) Output of the program
Please refer to Fig 6 for the program interface specifying the output. There are address
counters outputting the vertical (lpm_counter2), upper horizontal and lower horizontal
(lpm_counter1) address of the data respectively. When checking is performed, the
address counter would automatically increase the address output by 1 no matter the
pulses are checked to be good or not. The address is then sent to the database
(lpm_rom0 and lpm_rom1). Corresponding data are then sent to another logic element
called MUX. The outputs of GOOD VERTICAL, GOOD UPPER HORIZONTAL and
GOOD LOWER HORIZONTAL are also sent to MUX. If the input pulses passed all the
checks, the corresponding data will then be the output of MUX. Otherwise, another
assigned number will be sent out. The assigned number is 171 for the upper system and
205 for the lower system. Hence, we would know the input is incorrect if these two
numbers are generated.
3.4) Pin assignment
Since the pins on the circuit board are fixed, it is necessary to ensure that the inputs and
outputs are assigned to fixed pins on the chip. Hence, the circuit board still can function
well even the program inside the FPGA is changed. The pin assignment table is shown
in Fig 7.
4) Testing of the program
The first few columns and rows of the emulated database are shown in table 1.
Table 1: A part of the emulated database
Address 0 1 2 3
0 0 1 2 3
1 64 65 66 67
The initial value of the horizontal address and vertical address are both 64. Hence, the
values of them will be 0 after the first checking of vertical and horizontal input signals.
And the first data output will be the one with position (0,0).
In Fig 8, RGU, H1U, H2U, H3U, SWU represent the upper horizontal shift input signals.
RGL, H1L, H2L, H3L, SWL represent the lower horizontal shift input signals. TG, V1,
V2, V3 represent the vertical shift input signal. OUTL [0]-[7] represent the outputs of
the lower system and OUTU [0]-[7] represent the outputs of the upper system.
The output of upper system and lower system will only be transferred when clk_dac_u

and clk_dac_l are high respectively. The period is 20ns as stated before.
4.1) Testing of vertical shift input signal
4.1.1) The result of correct input signals
In Fig 9, a set of correct vertical shift pulses was inputted. When there are correct
horizontal shift pulses come later, the system gives out data from the database.
4.1.2) The result of incorrect signals
In Fig 10, a set of incorrect vertical shift pulses was inputted. The system does not give
out data from the database even there are correct horizontal shift pulses inputted.
4.2) Testing of horizontal shift input signal
In this case, the system is checked with the first row of data in table 1. That means right
after the first set of vertical input signal is being inputted.
4.2.1) The result of correct input signals
Three sets of correct signals are input in sequence. In Fig 11, 12 and 13, the correct
outputs 00000000, 00000001, 00000010 are given out respectively.
4.2.2) The result of incorrect signals
In Fig 14, the H1U input of the second group pulses is incorrect. Hence, the output
would remain at the value 171 when clk_dac_u is high. This number indicates that the
input pulses are not correct.
5) Conclusion and future development
The project dark energy survey is aimed at investigating the dark energy in the universe.
A 520 megapixel Charged-Coupled device (CCD) camera telescope will be built for this
purpose. UIUC is to build the data acquisition system of the telescope. The emulator is
designed to simulate the CCD output for testing.
This report mainly concerns the programming of Altera Cyclone II chips.
In the future, printed circuit board containing Altera Cyclone II chips will be designed.
And these emulators will be used to test the data acquisition system.
6) Acknowledgement
I would like to thank professor John Thaler and professor Mats Selen of University of
Illinois at Urbana-Champaign for letting me to join their research group and work under
their guidance.

I would also like to thank the physics department of The Chinese university of Hong
Kong for giving me a chance to UIUC for a summer exchange.
7) References
- E.L. Dagless, J.O. Reilly; Electronics: A System Approach; Addison- Wesley
Publishing Company; 1992
- Proposal to NOAO for the dark energy Survey. Retrieved 12/6/2006 from
http://cosmology.uiuc.edu/DES/Documents/A_Proposal_to_NOAO.pdf

Appendix:
Fig.1 A CCD of the camera
Fig 2. Correct sequence of input pulses for a vertical shift commend
Fig 3. Correct sequence of input pulses for a horizontal shift commend

Fig. 4 Interface of program for input of pulses
Fig. 5 Interface of program for checking of pulses

Fig. 6 Interface of program for output of Data
Fig. 7 Location of the chip pins assigned to the inputs and outputs

Fig. 8 Inputs and output names during the simulation of program
Fig. 9 Output with correct input of vertical shift signals. The red square contains the
input of vertical shift signals. The blue square contains the output.

Fig. 10 Output with incorrect input of vertical shift signals. The red square contains the
input of vertical shift signals. The green square contains the input of horizontal shift
pulses. The blue square contains the output.
Fig.11 Output after the first input of correct horizontal shift signals. The red square
contains the output of the upper system. The blue square contains the output of lower
system

Fig.12 Output after the second input of correct horizontal shift signals. The red square
contains the output of the upper system. The blue square contains the output of lower
system
Fig.13 Output after the third input of correct horizontal shift signals. The red square
contains the output of the upper system. The blue square contains the output of lower
system

Fig.14 Output after the input of correct and incorrect horizontal shift signals. The red
square contains the input and output with correct input pulses. The blue square contains
the input and output with incorrect input pulses. The green squares indicate where the
input signals are incorrect.
Fig.15 The database of the emulator programmed with the information of a star
Fig.16 The expected outlook of the CCD emulated with information in Fig. 16