Xilinx UG475 7 Series FPGAs Packaging and Pinout Advance ...
Xilinx UG475 7 Series FPGAs Packaging and Pinout Advance ...
Xilinx UG475 7 Series FPGAs Packaging and Pinout Advance ...
You also want an ePaper? Increase the reach of your titles
YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.
7 <strong>Series</strong> <strong>FPGAs</strong><br />
<strong>Packaging</strong> <strong>and</strong> <strong>Pinout</strong><br />
<strong>Advance</strong> Specification<br />
<strong>UG475</strong> (v1.4) October 17, 2011<br />
www.BDTIC.com/XILINX
The information disclosed to you hereunder (the "Materials") is provided solely for the selection <strong>and</strong> use of <strong>Xilinx</strong> products. To the maximum<br />
extent permitted by applicable law: (1) Materials are made available "AS IS" <strong>and</strong> with all faults, <strong>Xilinx</strong> hereby DISCLAIMS ALL<br />
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF<br />
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; <strong>and</strong> (2) <strong>Xilinx</strong> shall not be liable (whether<br />
in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising<br />
under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or<br />
consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action<br />
brought by a third party) even if such damage or loss was reasonably foreseeable or <strong>Xilinx</strong> had been advised of the possibility of the same.<br />
<strong>Xilinx</strong> assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update. You may not<br />
reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms <strong>and</strong><br />
conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty <strong>and</strong><br />
support terms contained in a license issued to you by <strong>Xilinx</strong>. <strong>Xilinx</strong> products are not designed or intended to be fail-safe or for use in any<br />
application requiring fail-safe performance; you assume sole risk <strong>and</strong> liability for use of <strong>Xilinx</strong> products in Critical Applications:<br />
http://www.xilinx.com/warranty.htm#critapps.<br />
AUTOMOTIVE APPLICATIONS DISCLAIMER<br />
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING<br />
FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A<br />
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE<br />
XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES<br />
THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF<br />
XILINX PRODUCTS IN SUCH APPLICATIONS.<br />
© Copyright 2011 <strong>Xilinx</strong>, Inc. XILINX, the <strong>Xilinx</strong> logo, Virtex, Kintex, Artix, Zynq, Spartan, ISE, <strong>and</strong> other designated br<strong>and</strong>s included herein<br />
are trademarks of <strong>Xilinx</strong> in the United States <strong>and</strong> other countries. All other trademarks are the property of their respective owners.<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com <strong>UG475</strong> (v1.4) October 17, 2011
Revision History<br />
The following table shows the revision history for this document.<br />
Date Version Revision<br />
03/01/11 1.0 Initial <strong>Xilinx</strong> release.<br />
04/06/11 1.1 Removed the SBG324 package from the entire document. Added three Kintex-7 devices:<br />
XC7K355T, XC7K420T, <strong>and</strong> XC7K480T.<br />
Updated disclaimer <strong>and</strong> copyright on page 2. Updated package size of FF1156 in<br />
Table 1-1. Updated DXP_0, DXN_0 in Table 1-9.<br />
The Table 2-2 single ASCII device files have been updated for both the XC7K70T <strong>and</strong><br />
XC7K160T. All ASCII TXT files <strong>and</strong> the overall ZIP file have been updated on the web.<br />
Updated the XC7K70TFBG676 figures: Figure 3-13, Figure 3-14, Figure 3-15, <strong>and</strong><br />
Figure 3-16.<br />
Added information to Chapter 4, Mechanical Drawings, Chapter 5, Thermal<br />
Specifications, <strong>and</strong> Chapter 6, Package Marking.<br />
06/14/11 1.2 Added Virtex-7 device information including updating Table 1-1, adding Table 1-5,<br />
Table 1-8, Table 2-3, <strong>and</strong> Table 3-3. In Table 1-9, updated Note 3, the Configuration Pins<br />
section, <strong>and</strong> the Analog to Digital Converter (XADC) Pins section.<br />
Updated Figure 3-11, Figure 3-12, Figure 3-15, Figure 3-16, Figure 3-19, Figure 3-20,<br />
Figure 3-23, Figure 3-24, Figure 3-27, Figure 3-28, Figure 3-31, <strong>and</strong> Figure 3-32. Added<br />
Figure 3-33 through Figure 3-88.<br />
Added Figure 4-7 the mechanical drawing for the Kintex-7 devices FFG1156 package.<br />
Also added some Virtex-7 device mechanical drawings in Figure 4-8 through<br />
Figure 4-11.<br />
Added thermal resistance data to Table 5-1.<br />
10/03/11 1.3 Added Artix-7 device information including updating Table 1-1, adding Table 1-3,<br />
Table 1-6, Table 2-1, <strong>and</strong> Table 3-1.<br />
Clarified the interposer in Figure 1-12 <strong>and</strong> Figure 1-13. Revised horizontal center for the<br />
XC7VX415T in Figure 1-15. Updated the DXP_0/DXN_0 description <strong>and</strong> notes in<br />
Table 1-9. Added devices to the Die Level Bank Numbering Overview section. Clarified<br />
the I/O banks summary: section.<br />
Added Artix-7 device diagrams in the CSG324 package: Figure 3-1 through Figure 3-8.<br />
Added XC7V585T device diagrams Figure 3-53 through Figure 3-60.<br />
Moved AD4P/N, AD12P/N, <strong>and</strong> AD5P/N pins from [IO_L2P_T0_35:IO_L4N_T0_35] to<br />
[IO_L1P_T0_35:IO_L3N_T0_35] in Figure 3-61, Figure 3-65, Figure 3-69, Figure 3-73,<br />
Figure 3-77, Figure 3-81, <strong>and</strong> Figure 3-85.<br />
Fixed the labeling for EMCCLK in Figure 3-37, Figure 3-41, Figure 3-45, Figure 3-49,<br />
Figure 3-53, Figure 3-61, Figure 3-65, Figure 3-69, Figure 3-73, Figure 3-77, Figure 3-81,<br />
<strong>and</strong> Figure 3-85.<br />
Updated the mechanical drawings for Figure 4-9 <strong>and</strong> Figure 4-11.<br />
Updated thermal resistance data in Table 5-1.<br />
Updated Chapter 6, Package Marking.<br />
10/17/11 1.4 Revised the FBG484 Package section describing XC7K160T Banks.<br />
Added the mechanical drawings: Figure 4-10 <strong>and</strong> Figure 4-12. Updated Figure 4-11 to<br />
include the FF(G)1928 package.<br />
Added thermal resistance data to Table 5-1.<br />
www.BDTIC.com/XILINX<br />
<strong>UG475</strong> (v1.4) October 17, 2011 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong>
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com <strong>UG475</strong> (v1.4) October 17, 2011
Table of Contents<br />
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3<br />
Preface: About This Guide<br />
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9<br />
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9<br />
Chapter 1: <strong>Packaging</strong> Overview<br />
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11<br />
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11<br />
Device/Package Combinations <strong>and</strong> Maximum I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . 12<br />
Serial Transceiver Channels by Device/Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13<br />
Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18<br />
Die Level Bank Numbering Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22<br />
Banking <strong>and</strong> Clocking Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22<br />
XC7A8 or XC7A15 Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23<br />
CSG324 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23<br />
XC7A30T or XC7A50T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23<br />
CSG324 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23<br />
XC7A100T Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24<br />
CSG324 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24<br />
XC7K70T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25<br />
FBG484 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25<br />
FBG676 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25<br />
XC7K160T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26<br />
FBG484 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26<br />
FBG676 <strong>and</strong> FFG676 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26<br />
XC7K325T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27<br />
FBG676 <strong>and</strong> FFG676 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27<br />
FBG900 <strong>and</strong> FFG900 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27<br />
XC7K355T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28<br />
FFG901 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28<br />
XC7K410T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29<br />
FBG676 <strong>and</strong> FFG676 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29<br />
FBG900 <strong>and</strong> FFG900 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29<br />
XC7K420T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30<br />
FFG901 <strong>and</strong> FFG1156 Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30<br />
XC7K480T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31<br />
FFG901 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31<br />
FFG1156 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31<br />
XC7V585T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32<br />
FFG1157 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32<br />
FFG1761 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32<br />
XC7V1500T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33<br />
FLG1761 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33<br />
XC7V2000T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 5<br />
<strong>UG475</strong> (v1.4) October 17, 2011
FHG1761 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34<br />
FLG1925 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34<br />
XC7VX330T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36<br />
FFG1157 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36<br />
FFG1761 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36<br />
XC7VX415T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37<br />
FFG1157 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37<br />
FFG1158 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37<br />
FFG1927 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37<br />
XC7VX485T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38<br />
FFG1157 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38<br />
FFG1158 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38<br />
FFG1761 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38<br />
FFG1927 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38<br />
FFG1930 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38<br />
XC7VX550T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40<br />
FFG1158 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40<br />
FFG1927 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40<br />
XC7VX690T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41<br />
FFG1157 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41<br />
FFG1158 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41<br />
FFG1761 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41<br />
FFG1926 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41<br />
FFG1927 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41<br />
FFG1930 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41<br />
XC7VX980T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43<br />
FFG1926 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43<br />
FFG1928 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43<br />
FFG1930 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43<br />
XC7VX1140T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45<br />
FLG1928 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45<br />
FLG1930 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45<br />
Chapter 2: 7 <strong>Series</strong> <strong>FPGAs</strong> Package Files<br />
About ASCII Package Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47<br />
ASCII <strong>Pinout</strong> Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48<br />
Chapter 3: Device Diagrams<br />
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51<br />
Artix-7 <strong>FPGAs</strong> Device Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52<br />
CSG324 Package—XC7A8 <strong>and</strong> XC7A15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52<br />
CSG324 Package—XC7A30T, XC7A50T, <strong>and</strong> XC7A100T . . . . . . . . . . . . . . . . . . . . . . . 55<br />
Kintex-7 <strong>FPGAs</strong> Device Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57<br />
FBG484 Package—XC7K70T <strong>and</strong> XC7K160T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57<br />
FBG676 Package—XC7K70T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60<br />
FBG676 Package—XC7K160T, XC7K325T, <strong>and</strong> XC7K410T . . . . . . . . . . . . . . . . . . . . . . 63<br />
FBG900 Package—XC7K325T <strong>and</strong> XC7K410T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66<br />
FFG676 Package—XC7K160T, XC7K325T, <strong>and</strong> XC7K410T . . . . . . . . . . . . . . . . . . . . . . 70<br />
FFG900 Package—XC7K325T <strong>and</strong> XC7K410T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73<br />
FFG901 Package—XC7K355T. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77<br />
FFG901 Package—XC7K420T. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81<br />
www.BDTIC.com/XILINX<br />
6 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
FFG901 Package—XC7K480T. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85<br />
FFG1156 Package—XC7K420T. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89<br />
FFG1156 Package—XC7K480T. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93<br />
Virtex-7 <strong>FPGAs</strong> Device Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97<br />
FFG1157 Package—XC7V585T. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98<br />
FFG1761 Package—XC7V585T. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102<br />
FLG1925 Package—XC7V2000T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106<br />
FHG1761 Package—XC7V2000T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110<br />
FFG1157 Package—XC7VX485T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114<br />
FFG1158 Package—XC7VX485T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118<br />
FFG1761 Package—XC7VX485T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122<br />
FFG1927 Package—XC7VX485T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126<br />
FFG1930 Package—XC7VX485T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130<br />
Chapter 4: Mechanical Drawings<br />
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135<br />
FB(G)484 Flip-Chip Bare-Die BGA (Kintex-7 <strong>FPGAs</strong>)<br />
(1.0 mm Pitch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136<br />
FB(G)676 Flip-Chip Bare-Die BGA (Kintex-7 <strong>FPGAs</strong>)<br />
(1.0 mm Pitch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137<br />
FB(G)900 Flip-Chip Bare-Die BGA (Kintex-7 <strong>FPGAs</strong>)<br />
(1.0 mm Pitch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138<br />
FF(G)676 Flip-Chip BGA (Kintex-7 <strong>FPGAs</strong>)<br />
(1.0 mm Pitch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139<br />
FF(G)900 Flip-Chip BGA (Kintex-7 <strong>FPGAs</strong>)<br />
(1.0 mm Pitch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140<br />
FF(G)901 Flip-Chip BGA (Kintex-7 <strong>FPGAs</strong>)<br />
(1.0 mm Pitch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141<br />
FF(G)1156 Flip-Chip BGA (Kintex-7 <strong>FPGAs</strong>)<br />
(1.0 mm Pitch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142<br />
FF(G)1157 <strong>and</strong> FF(G)1158 Flip-Chip BGA (Virtex-7 <strong>FPGAs</strong>)<br />
(1.0 mm Pitch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143<br />
FF(G)1761 Flip-Chip BGA (Virtex-7 <strong>FPGAs</strong>)<br />
(1.0 mm Pitch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144<br />
FH(G)1761 Flip-Chip BGA (Virtex-7 <strong>FPGAs</strong>)<br />
(1.0 mm Pitch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145<br />
FF(G)1926, FF(G)1927, FF(G)1928, <strong>and</strong> FF(G)1930 Flip-Chip BGA<br />
(Virtex-7 <strong>FPGAs</strong>) (1.0 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146<br />
FL(G)1925, FL(G)1928, <strong>and</strong> FL(G)1930 Flip-Chip BGA<br />
(Virtex-7 <strong>FPGAs</strong>) (1.0 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147<br />
Chapter 5: Thermal Specifications<br />
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149<br />
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149<br />
Power Management Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153<br />
Some Thermal Management Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155<br />
Support for Compact Thermal Models (CTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 7<br />
<strong>UG475</strong> (v1.4) October 17, 2011
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157<br />
Chapter 6: Package Marking<br />
Appendix A: Recommended PCB Design Rules for BGA Packages<br />
www.BDTIC.com/XILINX<br />
8 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Preface<br />
About This Guide<br />
Guide Contents<br />
Additional Resources<br />
<strong>Xilinx</strong>® 7 series <strong>FPGAs</strong> include three unified FPGA families that are all designed for<br />
lowest power to enable a common design to scale across families for optimal power,<br />
performance, <strong>and</strong> cost. The Artix-7 family is optimized for lowest cost <strong>and</strong> absolute<br />
power for the highest volume applications. The Virtex®-7 family is optimized for highest<br />
system performance <strong>and</strong> capacity. The Kintex-7 family is an innovative class of <strong>FPGAs</strong><br />
optimized for the best price-performance. This guide serves as a technical reference<br />
describing the 7 series packaging <strong>and</strong> pinout specifications.<br />
This 7 series packaging <strong>and</strong> pinout specification, part of an overall set of documentation on<br />
the 7 series <strong>FPGAs</strong>, is available on the <strong>Xilinx</strong> website at www.xilinx.com/7.<br />
This manual contains the following chapters:<br />
• Chapter 1, <strong>Packaging</strong> Overview<br />
• Chapter 2, 7 <strong>Series</strong> <strong>FPGAs</strong> Package Files<br />
• Chapter 3, Device Diagrams<br />
• Chapter 4, Mechanical Drawings<br />
• Chapter 5, Thermal Specifications<br />
• Chapter 6, Package Marking<br />
• Appendix A, Recommended PCB Design Rules for BGA Packages<br />
To find additional documentation, see the <strong>Xilinx</strong> website at:<br />
http://www.xilinx.com/support/documentation/index.htm.<br />
To search the Answer Database of silicon, software, <strong>and</strong> IP questions <strong>and</strong> answers, or to<br />
create a technical support WebCase, see the <strong>Xilinx</strong> website at:<br />
http://www.xilinx.com/support.<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 9<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Preface: About This Guide<br />
www.BDTIC.com/XILINX<br />
10 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 1<br />
<strong>Packaging</strong> Overview<br />
Summary<br />
Introduction<br />
This chapter covers the following topics:<br />
• Introduction<br />
• Device/Package Combinations <strong>and</strong> Maximum I/Os<br />
• Pin Definitions<br />
• Die Level Bank Numbering Overview<br />
This section describes the pinouts for the 7 series <strong>FPGAs</strong> in 0.5 mm chip-scale, 0.8 mm chip<br />
scale, <strong>and</strong> 1.0 mm in various fine pitch <strong>and</strong> flip-chip BGA packages.<br />
Artix-7 <strong>and</strong> Kintex-7 devices are offered in low-cost, space-saving packages that are<br />
optimally designed for the maximum number of user I/Os.<br />
Virtex®-7 <strong>and</strong> Virtex-7X devices are offered exclusively in high performance flip-chip BGA<br />
packages that are optimally designed for improved signal integrity <strong>and</strong> jitter.<br />
Package inductance is minimized as a result of optimal placement <strong>and</strong> even distribution as<br />
well as an increased number of Power <strong>and</strong> GND pins.<br />
All packages are available as Pb-free (G) with selected packages including a Pb-only<br />
option.<br />
All of the 7 series devices supported in a particular package are pinout compatible <strong>and</strong> are<br />
listed in the same table (one table per package). Pins that are not available for the smaller<br />
devices are listed as “No Connects”.<br />
Each device is split into I/O banks to allow for flexibility in the choice of I/O st<strong>and</strong>ards<br />
(see UG471, 7 <strong>Series</strong> <strong>FPGAs</strong> SelectIO Resources User Guide). Global pins, including JTAG,<br />
configuration, <strong>and</strong> power/ground pins, are listed at the end of each table. Table 1-9<br />
provides definitions for all pin types.<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 11<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 1: <strong>Packaging</strong> Overview<br />
Device/Package Combinations <strong>and</strong> Maximum I/Os<br />
Table 1-1:<br />
Packages (1)<br />
Table 1-1 shows the maximum number of user I/Os possible in the 7 series <strong>FPGAs</strong> BGA<br />
packages. Some devices are available in both Pb <strong>and</strong> Pb-free (additional G) packages as<br />
st<strong>and</strong>ard ordering options.<br />
7 <strong>Series</strong> <strong>FPGAs</strong> Package Specifications<br />
Description<br />
Package Specifications<br />
Package Type Pitch (mm) Size (mm) Maximum I/Os (2)<br />
CPG236<br />
BGA 0.5 10 x 10 140<br />
CSG225 Wire-bond chip-scale<br />
BGA 0.8 12 x 12 100<br />
CSG324 BGA 0.8 15 x 15 210<br />
FTG256<br />
BGA 1.0 17 x 17 170<br />
FGG484 Wire-bond fine-pitch<br />
BGA 1.0 23 x 23 285<br />
FGG676 BGA 1.0 27 x 27 300<br />
FB(G)484<br />
BGA 1.0 23 x 23 285<br />
FB(G)676 Flip-chip bare-die<br />
BGA 1.0 27 x 27 400<br />
FB(G)900 BGA 1.0 31 x 31 500<br />
FF(G)676<br />
BGA 1.0 27 x 27 400<br />
FF(G)900 BGA 1.0 31 x 31 500<br />
FF(G)901 BGA 1.0 31 x 31 380<br />
FF(G)1156 BGA 1.0 35 x 35 600<br />
FF(G)1157 BGA 1.0 35 x 35 600<br />
FF(G)1158 BGA 1.0 35 x 35 350<br />
FF(G)1761 BGA 1.0 42.5 x 42.5 850<br />
FF(G)1926 BGA 1.0 45 x 45 720<br />
Flip-chip fine-pitch<br />
FF(G)1927 BGA 1.0 45 x 45 600<br />
FF(G)1928 BGA 1.0 45 x 45 480<br />
FF(G)1930 BGA 1.0 45 x 45 1000<br />
FL(G)1761 BGA 1.0 42.5 x 42.5 850<br />
FL(G)1925 BGA 1.0 45 x 45 1200<br />
FL(G)1928 BGA 1.0 45 x 45 480<br />
FL(G)1930 BGA 1.0 45 x 45 1100<br />
FH(G)1761 BGA 1.0 45 x 45 850<br />
Notes:<br />
1. Leaded package options (FFxxx/FBxxx) are available for the Kintex-7 XC7K160T, XC7K325T, XC7K355T, XC7K410T, XC7K420T, <strong>and</strong><br />
XC7K480Tdevices.<br />
2. The maximum I/O numbers do not include pins in the configuration Bank 0 (Table 1-2) or the GTX serial transceivers.<br />
www.BDTIC.com/XILINX<br />
12 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Device/Package Combinations <strong>and</strong> Maximum I/Os<br />
Table 1-2:<br />
Table 1-2 lists the 21 dedicated I/O pins.<br />
7 series <strong>FPGAs</strong> I/O Pins in the Dedicated Configuration Bank (Bank0)<br />
DXP_0 VCCBATT_0 INIT_B_0 M0_0 TDO_0 TDI_0 GNDADC_0<br />
DXN_0 DONE_0 VN_0 M1_0 TCK_0 VREFN_0 VCCADC_0<br />
PROGRAM_B_0 CCLK_0 VP_0 M2_0 TMS_0 VREFP_0 CFGBVS_0<br />
Serial Transceiver Channels by Device/Package<br />
Table 1-3 lists the quantity of GTP serial transceiver channels for the Artix-7 <strong>FPGAs</strong>.<br />
Table 1-4 lists the quantity of GTX serial transceiver channels for the Kintex-7 <strong>FPGAs</strong>.<br />
Table 1-5 lists the quantity of GTX <strong>and</strong> GTH serial transceiver channels for the Virtex-7<br />
<strong>FPGAs</strong>. In all devices, a serial transceiver channel is one set of MGTRXP, MGTRXN,<br />
MGTTXP, <strong>and</strong> MGTTXN pins.<br />
Table 1-3:<br />
Device<br />
Serial Transceiver Channels (GTPs) by Device/Package (Artix-7 <strong>FPGAs</strong>)<br />
GTP Channels by Package<br />
CPG236 CSG225 CSG324 FTG256 FGG484 FGG676 FBG484 FBG676 FFG1156<br />
XC7A8 0 0 0 – – – – – –<br />
XC7A15 0 0 0 – – – – – –<br />
XC7A30T – 4 0 0 4 – – – –<br />
XC7A50T – 4 0 0 4 – – – –<br />
XC7A100T – – 0 0 4 8 – – –<br />
XC7A200T – – – – – – 4 8 16<br />
XC7A350T – – – – – – 4 8 16<br />
Table 1-4:<br />
Device<br />
Serial Transceiver Channels (GTXs) by Device/Package (Kintex-7 <strong>FPGAs</strong>)<br />
GTX Channels by Package<br />
FBG484 FBG676 FBG900 FFG676 FFG900 FFG901 FFG1156<br />
XC7K70T 4 8 – – – – –<br />
XC7K160T 4 8 – 8 – – –<br />
XC7K325T – 8 16 8 16 – –<br />
XC7K355T – – – – – 24 –<br />
XC7K410T – 8 16 8 16 – –<br />
XC7K420T – – – – – 28 28<br />
XC7K480T – – – – – 28 32<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 13<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 1: <strong>Packaging</strong> Overview<br />
Table 1-5:<br />
Device<br />
Serial Transceiver Channels (GTX/GTH) by Device/Package (Virtex-7 <strong>FPGAs</strong>)<br />
GTX or GTH Channels by Package<br />
FFG FFG FFG FFG FFG FFG FFG FLG FLG FLG FLG FHG<br />
1157 1158 1761 1926 1927 1928 1930 1761 1925 1928 1930s 1761<br />
XC7V585T 20 0 – 36 0 – – – – – – – – – –<br />
XC7V1500T – – – – – – – 36 0 – – – – –<br />
XC7V2000T – – – – – – – – 16 0 – – 36 0<br />
XC7VX330T 0 20 – 0 28 – – – – – – – – –<br />
XC7VX415T 0 20 0 48 – – 0 48 – – – – – – –<br />
XC7VX485T 20 0 48 0 28 0 – 56 0 – 24 0 – – – – –<br />
XC7VX550T – 0 48 – – 0 64 – – – – – – –<br />
XC7VX690T 0 20 0 48 0 36 0 64 0 80 – 0 24 – – – – –<br />
XC7VX980T – – – 0 64 – 0 72 0 24 – – – – –<br />
XC7VX1140T – – – – – – – – – 0 96 0 24 –<br />
www.BDTIC.com/XILINX<br />
14 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Device/Package Combinations <strong>and</strong> Maximum I/Os<br />
Table 1-6 shows the number of available I/Os <strong>and</strong> the number of differential I/Os for each<br />
Artix-7 device/package combination. Table 1-7 shows the number of available I/Os <strong>and</strong><br />
the number of differential I/Os for each Kintex-7 device/package combination. Table 1-8<br />
shows the number of available I/Os <strong>and</strong> the number of differential I/Os for each Virtex-7<br />
device/package combination. When applicable, it also lists the number of user I/Os in the<br />
3.3V-capable high-range (HR) banks <strong>and</strong> the number of 1.8V-capable high-performance<br />
(HP) banks.<br />
Table 1-6:<br />
Artix-7<br />
Devices<br />
XC7A8<br />
XC7A15<br />
XC7A30T<br />
XC7A50T<br />
XC7A100T<br />
XC7A200T<br />
XC7A350T<br />
Available I/O Pin/Device/Package Combinations for Artix-7 <strong>FPGAs</strong><br />
User I/O<br />
Pins<br />
Artix-7 Packages: HR I/O Banks Only<br />
CPG236 CSG225 CSG324 FTG256 FGG484 FGG676 FBG484 FBG676 FFG1156<br />
User I/O 140 – 200 170 – – – – –<br />
Differential – 192 – – – – –<br />
User I/O 140 – 200 170 – – – – –<br />
Differential – 192 – – – – –<br />
User I/O – 100 210 170 250 – – – –<br />
Differential – 202 – – – –<br />
User I/O – 100 210 170 250 – – – –<br />
Differential – 202 – – – –<br />
User I/O – – 210 170 285 300 – – –<br />
Differential – – 202 – – –<br />
User I/O – – – – – – 285 400 500<br />
Differential – – – – – –<br />
User I/O – – – – – – 285 400 600<br />
Differential – – – – – –<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 15<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 1: <strong>Packaging</strong> Overview<br />
Table 1-7:<br />
Kintex-7<br />
Devices<br />
XC7K70T<br />
XC7K160T<br />
XC7K325T<br />
XC7K355T<br />
XC7K410T<br />
XC7K420T<br />
XC7K480T<br />
Available I/O Pin/Device/Package Combinations for Kintex-7 <strong>FPGAs</strong><br />
User I/O<br />
Pins<br />
Kintex-7 Packages: HR <strong>and</strong> HP I/O Banks<br />
FBG484 FBG676 FBG900 FFG676 FFG900 FFG901 FFG1156<br />
HP HR HP HR HP HR HP HR HP HR HP HR HP HR<br />
User I/O 100 185 100 200 – – – – – – – – – –<br />
Differential 96 179 96 192 – – – – – – – – – –<br />
User I/O 100 185 150 250 – – 150 250 – – – – – –<br />
Differential 96 179 144 240 – – 144 240 – – – – – –<br />
User I/O – – 150 250 150 350 150 250 150 350 – – – –<br />
Differential – – 144 240 144 336 144 240 144 336 – – – –<br />
User I/O – – – – – – – – – – 0 300 – –<br />
Differential – – – – – – – – – – 0 288 – –<br />
User I/O – – 150 250 150 350 150 250 150 350 – – – –<br />
Differential – – 144 240 144 336 144 240 144 336 – – – –<br />
User I/O – – – – – – – – – – 0 350 0 350<br />
Differential – – – – – – – – – – 0 336 0 366<br />
User I/O – – – – – – – – – – 0 380 0 400<br />
Differential – – – – – – – – – – 0 366 0 384<br />
www.BDTIC.com/XILINX<br />
16 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Device/Package Combinations <strong>and</strong> Maximum I/Os<br />
Table 1-8:<br />
User<br />
Virtex-7<br />
I/O<br />
Devices<br />
Pins<br />
Available I/O Pin/Device/Package Combinations for Virtex-7 <strong>FPGAs</strong><br />
Virtex-7 Packages: HR <strong>and</strong> HP I/O Banks<br />
FFG FFG FFG FFG FFG FFG FFG FLG FLG FLG FLG FHG<br />
1157 1158 1761 1926 1927 1928 1930 1761 1925 1928 1930 1761<br />
HP HR HP HR HP HR HP HR HP HR HP HR HP HR HP HR HP HR HP HR HP HR HP HR<br />
XC7V<br />
585T<br />
XC7V<br />
1500T<br />
XC7V<br />
2000T<br />
XC7VX<br />
330T<br />
XC7VX<br />
415T<br />
XC7VX<br />
485T<br />
XC7VX<br />
550T<br />
XC7VX<br />
690T<br />
XC7VX<br />
980T<br />
XC7VX<br />
1140T<br />
User 600 0 – 750 100 – – – – – – – – –<br />
Diff 576 0 – 720 96 – – – – – – – – –<br />
User – – – – – – – 850 0 – – – –<br />
Diff – – – – – – – 816 0 – – – –<br />
User – – – – – – – – 1200 0 – – 850 0<br />
Diff – – – – – – – – 1152 0 – – 816 0<br />
User 600 0 – 650 50 – – – – – – – – –<br />
Diff 576 0 – 624 48 – – – – – – – – –<br />
User 600 0 350 0 – – 600 0 – – – – – – –<br />
Diff 576 0 336 0 – – 576 0 – – – – – – –<br />
User 600 0 350 0 700 0 – 600 0 – 700 0 – – – – –<br />
Diff 576 0 336 0 672 0 – 576 0 – 672 0 – – – – –<br />
User – 350 0 – – 600 0 – – – – – – –<br />
Diff – 336 0 – – 576 0 – – – – – – –<br />
User 600 0 350 0 850 0 720 0 600 0 – 1000 0 – – – – –<br />
Diff 576 0 336 0 816 0 690 0 576 0 – 960 0 – – – – –<br />
User – – – 720 0 – 480 0 900 0 – – – – –<br />
Diff – – – 690 0 – 460 0 864 0 – – – – –<br />
User – – – – – – – – – 480 0 1100 0 –<br />
Diff – – – – – – – – – 460 0 1056 0 –<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 17<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 1: <strong>Packaging</strong> Overview<br />
Pin Definitions<br />
Table 1-9:<br />
User I/O Pins<br />
Table 1-9 lists the pin definitions used in 7 series <strong>FPGAs</strong> packages.<br />
Note: There are dedicated general purpose user I/O pins listed separately in Table 1-9. There are<br />
also multi-function pins where the pin names start with either IO_LXXY_ZZZ_# or IO_XX_ZZZ_#,<br />
where ZZZ represents one or more functions in addition to being general purpose user I/O. If not used<br />
for their special function, these pins can be user I/O.<br />
7 series <strong>FPGAs</strong> Pin Definitions<br />
Pin Name Type Direction Description<br />
IO_LXXY_#<br />
IO_XX_#<br />
Dedicated<br />
Input/<br />
Output<br />
Most user I/O pins are capable of differential signaling <strong>and</strong><br />
can be implemented as pairs. The top <strong>and</strong> bottom I/O pins<br />
are always single ended. Each user I/O is labeled<br />
IO_LXXY_#, where:<br />
• IO indicates a user I/O pin.<br />
• L indicates a differential pair, with XX a unique pair in<br />
the bank <strong>and</strong> Y = [P|N] for the positive/negative sides<br />
of the differential pair.<br />
• # indicates a bank number.<br />
Configuration Pins<br />
For more information, see the Configuration Pin Definitions table in UG470, 7 <strong>Series</strong> <strong>FPGAs</strong> Configuration User Guide.<br />
CCLK_0 Dedicated (1) Input/<br />
Output<br />
DONE_0 Dedicated (1) Bidirectional<br />
INIT_B_0 Dedicated (1) Bidirectional<br />
(open-drain)<br />
Configuration clock. Output in Master mode or input in<br />
Slave mode.<br />
Active High, DONE indicates successful completion of<br />
configuration.<br />
Active Low, indicates initialization of configuration memory.<br />
M0_0, M1_0, or M2_0 Dedicated (1) Input Configuration mode selection<br />
PROGRAM_B_0 Dedicated (1) Input Active Low, asynchronous reset to configuration logic.<br />
TCK_0 Dedicated (1) Input JTAG clock.<br />
TDI_0 Dedicated (1) Input JTAG data input.<br />
TDO_0 Dedicated (1) Output JTAG data output.<br />
TMS_0 Dedicated (1) Input JTAG mode select.<br />
CFGBVS_0 Dedicated (1) Input<br />
This pin selects the preconfiguration I/O st<strong>and</strong>ard type for<br />
the dedicated <strong>and</strong> multi-function configuration banks 0, 14,<br />
<strong>and</strong> 15. If the V CCO for banks 0, 14, or 15 is 2.5V or 3.3V, then<br />
this pin must be connect to V CCO_0 . If the V CCO for banks 0,<br />
14, <strong>and</strong> 15 are less than or equal to 1.8V, then this pin should<br />
be connected to GND.<br />
Note: To avoid device damage, this pin must be connected<br />
correctly. See the Configuration Bank Voltage Select section in<br />
UG470: 7 <strong>Series</strong> <strong>FPGAs</strong> Configuration User Guide for more<br />
information.<br />
D00 through D31 Multi-function Bidirectional Configuration data pins.<br />
www.BDTIC.com/XILINX<br />
18 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Pin Definitions<br />
Table 1-9: 7 series <strong>FPGAs</strong> Pin Definitions (Cont’d)<br />
Pin Name Type Direction Description<br />
ADV_B Multi-function Output BPI Flash address valid output<br />
A00 through A28 Multi-function Output Address A00–A28 BPI address output.<br />
RS0 or RS1 Multi-function Output RS0 <strong>and</strong> RS1 revision select output.<br />
FCS_B Multi-function Output BPI <strong>and</strong> SPI flash chip select.<br />
FOE_B Multi-function Output BPI flash output enable.<br />
MOSI Multi-function Output<br />
SPI flash comm<strong>and</strong> output. Also known as the SPI bus<br />
master output, slave input signal.<br />
FWE_B Multi-function Output BPI flash write enable.<br />
DOUT Multi-function Output Data output for serial daisy-chain configuration.<br />
CSO_B Multi-function Output Active Low chip-select output for parallel daisy-chain.<br />
CSI_B Multi-function Input SelectMAP active Low chip-select input.<br />
PUDC_B Multi-function Input<br />
RDWR_B Multi-function Input<br />
Active Low input enables internal pull-ups during<br />
configuration on all SelectIO pins:<br />
0 = Weak preconfiguration I/O pull-up resistors enabled<br />
1 = Weak preconfiguration I/O pull-up resistors disabled<br />
SelectMAP data bus direction control signal for reading or<br />
writing configuration data.<br />
EMCCLK Multi-function Input External master configuration clock.<br />
Power/Ground Pins<br />
GND Dedicated N/A Ground.<br />
VCCAUX Dedicated N/A 1.8V power-supply pins for auxiliary circuits.<br />
VCCAUX_IO_G# (2) Dedicated N/A 1.8V/2.0V power-supply pins for auxiliary I/O circuits.<br />
VCCINT Dedicated N/A 0.9V/1.0V power-supply pins for the internal core logic.<br />
VCCO_# (3) Dedicated N/A Power-supply pins for the output drivers (per bank).<br />
VCCBRAM Dedicated N/A 1.0V power-supply pins for the FPGA logic block RAM.<br />
VCCBATT_0 Dedicated N/A<br />
VREF Multi-function N/A<br />
Decryptor key memory backup supply; this pin should be<br />
tied to the appropriate V CC or GND when not used. (4)<br />
These are input threshold voltage pins. They become user I/<br />
Os when an external threshold voltage is not needed (per<br />
bank).<br />
Analog to Digital Converter (XADC) Pins<br />
For more information, see the XADC Package Pins table in UG480, 7 <strong>Series</strong> <strong>FPGAs</strong> XADC User Guide.<br />
VCCADC_0 (5) Dedicated N/A XADC analog positive supply voltage.<br />
GNDADC_0 (5) Dedicated N/A XADC analog ground reference.<br />
VP_0 (5) Dedicated Input XADC dedicated differential analog input (positive side).<br />
VN_0 (5) Dedicated Input XADC dedicated differential analog input (negative side).<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 19<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 1: <strong>Packaging</strong> Overview<br />
Table 1-9:<br />
7 series <strong>FPGAs</strong> Pin Definitions (Cont’d)<br />
Pin Name Type Direction Description<br />
VREFP_0 (5) Dedicated N/A 1.25V reference input.<br />
VREFN_ 0 (5) Dedicated N/A 1.25V reference GND reference.<br />
XADC (analog-to-digital converter) differential auxiliary<br />
AD0P through AD15P<br />
AD0N through AD15N Multi-function Input analog inputs 0–15.<br />
Auxiliary channels 6, 7, 13, 14, <strong>and</strong> 15 are not supported on<br />
Kintex-7 devices.<br />
Multi-gigabit Serial Transceiver Pins (GTXE2 <strong>and</strong> GTHE2)<br />
For more information on the GTXE2 pins see the Pin Description <strong>and</strong> Design Guidelines section in UG476, 7 <strong>Series</strong> <strong>FPGAs</strong><br />
GTX Transceivers User Guide.<br />
MGTXRXP[0:3] Dedicated Input Positive differential receive port GTX Quad.<br />
MGTXRXN[0:3] Dedicated Input Negative differential receive port GTX Quad.<br />
MGTXTXP[0:3] Dedicated Output Positive differential transmit port GTX Quad.<br />
MGTXTXN[0:3] Dedicated Output Negative differential transmit port GTX Quad.<br />
MGTHRXP[0:3] Dedicated Input Positive differential receive port GTH Quad.<br />
MGTHRXN[0:3] Dedicated Input Negative differential receive port GTH Quad.<br />
MGTHTXP[0:3] Dedicated Output Positive differential transmit port GTH Quad.<br />
MGTHTXN[0:3] Dedicated Output Negative differential transmit port GTH Quad.<br />
MGTAVCC_G# Dedicated Input<br />
1.0V analog power-supply pin for the receiver <strong>and</strong><br />
transmitter internal circuits.<br />
MGTAVTT_G# Dedicated Input 1.2V analog power-supply pin for the transmit driver.<br />
MGTVCCAUX_G# Dedicated Input<br />
1.8V auxiliary analog Quad PLL (QPLL) voltage supply for<br />
the transceivers.<br />
MGTREFCLK0/1P Dedicated Input Positive differential reference clock for the transceivers.<br />
MGTREFCLK0/1N Dedicated Input Negative differential reference clock for the transceivers.<br />
MGTAVTTRCAL Dedicated N/A<br />
MGTRREF Dedicated Input<br />
Precision reference resistor pin for internal calibration<br />
termination. Not used for Artix-7 devices.<br />
Precision reference resistor pin for internal calibration<br />
termination.<br />
Other Pins<br />
RSVD Dedicated N/A Reserved. No Connection; leave floating.<br />
MRCC Multi-function Input<br />
These are the clock capable I/Os driving BUFRs, BUFIOs,<br />
BUFGs, <strong>and</strong> MMCMs/PLLs. In addition, these pins can drive<br />
the BUFMR for multi-region BUFIO <strong>and</strong> BUFR support.<br />
These pins become regular user I/Os when not needed as a<br />
clock. When connecting a single-ended clock to the<br />
differential CC pair of pins, it must be connected to the<br />
positive (P) side of the pair. The MRCC (multi-region) pins,<br />
when used as single region resource, can drive four BUFIOs<br />
<strong>and</strong> four BUFR in a single bank.<br />
www.BDTIC.com/XILINX<br />
20 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Pin Definitions<br />
Table 1-9:<br />
7 series <strong>FPGAs</strong> Pin Definitions (Cont’d)<br />
Pin Name Type Direction Description<br />
SRCC Multi-function Input<br />
VRN (6) Multi-function N/A<br />
VRP (6) Multi-function N/A<br />
DXP_0, DXN_0 Dedicated Input<br />
These are the clock capable I/Os driving BUFRs, BUFIOs,<br />
<strong>and</strong> MMCMs/PLLs. These pins become regular user I/Os<br />
when not needed for clocks. When connecting a single-ended<br />
clock to the differential CC pair of pins, it must be connected<br />
to the positive (P) side of the pair. The SRCC (single region)<br />
pins can drive four BUFIOs <strong>and</strong> four BUFRs in a single bank.<br />
This pin is for the DCI voltage reference resistor of N<br />
transistor (per bank, to be pulled High with reference<br />
resistor).<br />
This pin is for the DCI voltage reference resistor of P<br />
transistor (per bank, to be pulled Low with reference<br />
resistor).<br />
Temperature-sensing diode pins (Anode: DXP; Cathode:<br />
DXN). The thermal diode is accessed by using the DXP <strong>and</strong><br />
DXN pins in bank 0. When not used, tie to GND.<br />
To use the thermal diode an appropriate external thermal<br />
monitoring IC must be added. Consult the external thermal<br />
monitoring IC data sheet for usage guidelines.<br />
The recommended temperature monitoring solution for<br />
7 series <strong>FPGAs</strong> uses the temperature sensor in the XADC<br />
block.<br />
T0, T1, T2, or T3 Multi-function Input This pin belongs to the memory byte group 0-3.<br />
T0_DQS, T1_DQS,<br />
T2_DQS, or T3_DQS<br />
Multi-function<br />
Input<br />
The DDR DQS strobe pin that belongs to the memory byte<br />
group T0–T3.<br />
Notes:<br />
1. All dedicated pins (JTAG <strong>and</strong> configuration) are powered by V CCO_0 .<br />
2. For devices that do not include VCCAUX_IO_G# pins, auxiliary I/O circuits are powered by VCCAUX pins.<br />
3. V CCO pins in unbonded banks must be connected to the V CCO for that bank for package migration. Do NOT connect unbonded<br />
V CCO pins to different supplies. Without a package migration requirement, V CCO pins in unbonded banks can be tied to a common<br />
supply (V CCO or ground).<br />
4. Refer to the data sheet for V CCBATT_0 specifications.<br />
5. See UG480, 7 <strong>Series</strong> <strong>FPGAs</strong> XADC User Guide for the default connections required to support on-chip monitoring.<br />
6. The DCI guidelines in the 7 series <strong>FPGAs</strong> are different from previous Virtex device DCI guidelines. See the DCI sections in UG471:<br />
7 <strong>Series</strong> <strong>FPGAs</strong> SelectIO Resources User Guide for more information on the VRN/VRP pins.<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 21<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 1: <strong>Packaging</strong> Overview<br />
Die Level Bank Numbering Overview<br />
Banking <strong>and</strong> Clocking Summary<br />
• The center clocking backbone contains all vertical clock tracks <strong>and</strong> clock buffer<br />
connectivity.<br />
• The CMT backbone contains all vertical CMT connectivity <strong>and</strong> is located in the CMT<br />
column.<br />
• Not all banks are bonded out in every part/package combination.<br />
• GTP/GTX/GTH columns summary:<br />
• One bank = One GT Quad = Four transceivers = Four GTPE2s or GTXE2s or<br />
GTHE2 primitives.<br />
• Not all GT Quads are bonded out in every package.<br />
• I/O banks summary:<br />
• Each bank has four pairs of clock capable (CC) inputs for four differential or four<br />
single ended clock inputs.<br />
- Can connect to the CMT in the same region <strong>and</strong> the region above <strong>and</strong> below<br />
(with restrictions).<br />
- Two MRCC pairs can connect to the BUFRs <strong>and</strong> BUFIOs in the same region/<br />
banks <strong>and</strong> the regions/banks above <strong>and</strong> below.<br />
- Two SRCCs pairs can only connect to the BUFRs <strong>and</strong> BUFIOs in the same<br />
region/bank.<br />
- There are no global clock pins (GC pins) in the 7 series <strong>FPGAs</strong>.<br />
• Each user I/O bank has 50 single-ended I/Os or 24 differential pairs (48<br />
differential I/Os). The top <strong>and</strong> bottom I/O pin are always single ended. All 50<br />
pads of a bank are not always bonded out to pins.<br />
• Bank locations of dedicated <strong>and</strong> dual-purpose pins:<br />
• In most devices, banks 14 <strong>and</strong> 15 always contain the dual-purpose configuration<br />
pins. Bank 15 <strong>and</strong> 35 contains the XADC auxiliary inputs; however, in Kintex-7<br />
devices, the auxiliary inputs are only in bank 15. Bank 0 contains the dedicated<br />
configuration pins.<br />
• In the XC7V1500T <strong>and</strong> XC7V2000T devices, banks 11 <strong>and</strong> 12 contain the<br />
dual-purpose configuration pins. Bank 12 <strong>and</strong> 32 contains the XADC auxiliary<br />
inputs. Bank 0 contains the dedicated configuration pins.<br />
• All dedicated configuration I/Os (bank 0) are 3.3V capable<br />
• The physical XY locations for each IDELAYCTRL start at X0Y0 in the bottom left-most<br />
bank <strong>and</strong> are then increment by one starting with the lowest bank number in each<br />
column in the vertical Y direction <strong>and</strong> by one for each column in the horizontal X<br />
direction. IDELAYCTRLs are located in each of the HROWs.<br />
Figure 1-1 through Figure 1-20 visually describe a die view of the FPGA bank numbering.<br />
Note: The figures for some Artix-7 <strong>and</strong> Virtex-7 <strong>FPGAs</strong> are in development.<br />
www.BDTIC.com/XILINX<br />
22 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Die Level Bank Numbering Overview<br />
XC7A8 or XC7A15 Banks<br />
Figure 1-4 shows the I/O banks for the XC7A8 <strong>and</strong> XC7A15. These devices do not include<br />
transceiver banks.<br />
CSG324 Package<br />
• All HR banks are fully bonded out.<br />
X-Ref Target - Figure 1-1<br />
Left I/O<br />
Column<br />
Banks<br />
Bank 15<br />
HR<br />
Bank 14<br />
HR<br />
HROW<br />
PLL11<br />
CMT<br />
MMCM11<br />
Right I/O<br />
Column<br />
Banks<br />
Bank 35<br />
HR<br />
16 BUFGs<br />
Horizontal Center<br />
16 BUFGs<br />
PLL10<br />
CMT<br />
Bank 34 Bank<br />
MMCM10<br />
HR 50 I/Os<br />
Clocking<br />
Backbone<br />
CMT<br />
Backbone<br />
<strong>UG475</strong>_c1_01_082411<br />
Figure 1-1:<br />
XC7A8 <strong>and</strong> XC7A15 Banks<br />
XC7A30T or XC7A50T Banks<br />
Figure 1-2 shows the I/O <strong>and</strong> transceiver banks for the XC7A30T or XC7A50T.<br />
CSG324 Package<br />
• HR bank 16 is partially bonded out.<br />
• The GTX Quad bank 116 is not bonded out.<br />
X-Ref Target - Figure 1-2<br />
Left I/O<br />
Column<br />
Banks<br />
Right I/O<br />
Column<br />
Banks<br />
Bank 16<br />
HR<br />
PLL02<br />
CMT<br />
MMCM02<br />
HROW<br />
GTP Quad 116<br />
Quad<br />
GTP<br />
Bank 15<br />
HR<br />
Bank 14<br />
HR<br />
PLL01<br />
CMT<br />
MMCM01<br />
PLL00<br />
CMT<br />
MMCM00<br />
16 BUFGs<br />
16 BUFGs<br />
PLL11<br />
CMT<br />
MMCM11<br />
PLL10<br />
CMT<br />
MMCM10<br />
Bank 35<br />
HR<br />
Bank 34<br />
HR<br />
Horizontal Center<br />
Bank<br />
50 I/Os<br />
CMT<br />
Backbone<br />
Clocking<br />
Backbone<br />
CMT<br />
Backbone<br />
<strong>UG475</strong>_c1_02_081211<br />
Figure 1-2:<br />
XC7A30T <strong>and</strong> XC7A50T Banks<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 23<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 1: <strong>Packaging</strong> Overview<br />
XC7A100T Bank<br />
Figure 1-3 shows the I/O <strong>and</strong> transceiver banks for the XC7A100T.<br />
CSG324 Package<br />
• HR bank 13 is not bonded out.<br />
• HR bank 16 is partially bonded out.<br />
• The GTX Quad bank 116 is not bonded out.<br />
X-Ref Target - Figure 1-3<br />
Left I/O<br />
Column<br />
Banks<br />
Right I/O<br />
Column<br />
Banks<br />
Bank 16<br />
HR<br />
PLL03<br />
CMT<br />
MMCM03<br />
GTP Quad 116<br />
Quad<br />
GTP<br />
Bank 15<br />
HR<br />
Bank 14<br />
HR<br />
PLL02<br />
CMT<br />
MMCM02<br />
PLL01<br />
CMT<br />
MMCM01<br />
16 BUFGs<br />
16 BUFGs<br />
PLL11<br />
CMT<br />
MMCM11<br />
PLL10<br />
CMT<br />
MMCM10<br />
Bank 35<br />
HR<br />
Bank 34<br />
HR<br />
Horizontal Center<br />
Bank<br />
50 I/Os<br />
Bank 13<br />
HR<br />
PLL00<br />
CMT<br />
MMCM00<br />
HROW<br />
GTP Quad 113<br />
CMT<br />
Backbone<br />
Clocking<br />
Backbone<br />
CMT<br />
Backbone<br />
<strong>UG475</strong>_c1_03_081211<br />
Figure 1-3:<br />
XC7A100T Banks<br />
www.BDTIC.com/XILINX<br />
24 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Die Level Bank Numbering Overview<br />
XC7K70T Banks<br />
Figure 1-4 shows the I/O <strong>and</strong> transceiver banks for the XC7K70T.<br />
FBG484 Package<br />
• HR bank 16 is partially bonded out.<br />
• All HP banks are fully bonded out.<br />
• The GTX Quad bank 116 is not bonded out.<br />
FBG676 Package<br />
• All HR <strong>and</strong> HP banks <strong>and</strong> the GTX Quads are fully bonded out in this package.<br />
X-Ref Target - Figure 1-4<br />
Left I/O<br />
Column<br />
Banks<br />
Right I/O<br />
Column<br />
Banks<br />
Bank 16<br />
HR<br />
PLL03<br />
CMT<br />
MMCM03<br />
GTX Quad 116<br />
Quad<br />
GTX<br />
Bank 15<br />
HR<br />
Bank 14<br />
HR<br />
Bank 13<br />
HR<br />
PLL02<br />
CMT<br />
MMCM02<br />
PLL01<br />
CMT<br />
MMCM01<br />
PLL00<br />
CMT<br />
MMCM00<br />
HROW<br />
16 BUFGs<br />
16 BUFGs<br />
GTX Quad 115<br />
PLL11<br />
CMT<br />
MMCM11<br />
PLL10<br />
CMT<br />
MMCM10<br />
Bank 34<br />
HP<br />
Bank 33<br />
HP<br />
Horizontal<br />
Center<br />
Bank<br />
50 I/Os<br />
CMT<br />
Backbone<br />
Clocking<br />
Backbone<br />
CMT<br />
Backbone<br />
<strong>UG475</strong>_c1_08_081211<br />
Figure 1-4:<br />
XC7K70T Banks<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 25<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 1: <strong>Packaging</strong> Overview<br />
XC7K160T Banks<br />
Figure 1-5 shows the I/O <strong>and</strong> transceiver banks for the XC7K160T.<br />
FBG484 Package<br />
• HR bank 12 is not bonded out <strong>and</strong> bank 16 is partially bonded out.<br />
• HP bank 32 is not bonded out.<br />
• The GTX Quad bank 116 is not bonded out.<br />
FBG676 <strong>and</strong> FFG676 Packages<br />
• All HR <strong>and</strong> HP banks <strong>and</strong> the GTX Quads are fully bonded out in these packages.<br />
X-Ref Target - Figure 1-5<br />
Left I/O<br />
Column<br />
Banks<br />
Right I/O<br />
Column<br />
Banks<br />
Bank 16<br />
HR<br />
PLL04<br />
CMT<br />
MMCM04<br />
GTX Quad 116<br />
Quad<br />
GTX<br />
Bank 15<br />
HR<br />
Bank 14<br />
HR<br />
PLL03<br />
CMT<br />
MMCM03<br />
PLL02<br />
CMT<br />
MMCM02<br />
16 BUFGs<br />
16 BUFGs<br />
GTX Quad 115<br />
PLL12<br />
CMT<br />
MMCM12<br />
Bank 34<br />
HP<br />
Horizontal<br />
Center<br />
Bank 13<br />
HR<br />
PLL01<br />
CMT<br />
MMCM01<br />
PLL11<br />
CMT<br />
MMCM11<br />
Bank 33<br />
HP<br />
Bank 12<br />
HR<br />
PLL00<br />
CMT<br />
MMCM00<br />
HROW<br />
PLL10<br />
CMT<br />
MMCM10<br />
Bank 32<br />
HP<br />
Bank<br />
50 I/Os<br />
CMT<br />
Backbone<br />
Clocking<br />
Backbone<br />
CMT<br />
Backbone<br />
<strong>UG475</strong>_c1_09_081211<br />
Figure 1-5:<br />
XC7K160T Banks<br />
www.BDTIC.com/XILINX<br />
26 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Die Level Bank Numbering Overview<br />
XC7K325T Banks<br />
Figure 1-6 shows the I/O <strong>and</strong> transceiver banks for the XC7K325T.<br />
FBG676 <strong>and</strong> FFG676 Packages<br />
• HR banks 17 <strong>and</strong> 18 are not bonded out.<br />
• All HP banks are fully bonded out.<br />
• GTX Quads 117 <strong>and</strong> 118 are not bonded out.<br />
FBG900 <strong>and</strong> FFG900 Packages<br />
All HR <strong>and</strong> HP banks <strong>and</strong> the GTX Quads are fully bonded out in these packages.<br />
X-Ref Target - Figure 1-6<br />
Left I/O<br />
Column<br />
Banks<br />
Right I/O<br />
Column<br />
Banks<br />
Bank 18<br />
HR<br />
PLL06<br />
CMT<br />
MMCM06<br />
GTX Quad 118<br />
Quad<br />
GTX<br />
Bank 17<br />
HR<br />
PLL05<br />
CMT<br />
MMCM05<br />
GTX Quad 117<br />
Bank 16<br />
HR<br />
Bank 15<br />
HR<br />
PLL04<br />
CMT<br />
MMCM04<br />
PLL03<br />
CMT<br />
MMCM03<br />
16 BUFGs<br />
16 BUFGs<br />
GTX Quad 116<br />
GTX Quad 115<br />
Horizontal<br />
Center<br />
Bank 14<br />
HR<br />
PLL02<br />
CMT<br />
MMCM02<br />
PLL12<br />
CMT<br />
MMCM12<br />
Bank 34<br />
HP<br />
Bank 13<br />
HR<br />
PLL01<br />
CMT<br />
MMCM01<br />
PLL11<br />
CMT<br />
MMCM11<br />
Bank 33<br />
HP<br />
Bank 12<br />
HR<br />
PLL0<br />
CMT<br />
MMCM00<br />
HROW<br />
PLL10<br />
CMT<br />
MMCM10<br />
Bank 32<br />
HP<br />
Bank<br />
50 I/Os<br />
CMT<br />
Backbone<br />
Clocking<br />
Backbone<br />
CMT<br />
Backbone<br />
<strong>UG475</strong>_c1_10_081211<br />
Figure 1-6:<br />
XC7K325T Banks<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 27<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 1: <strong>Packaging</strong> Overview<br />
XC7K355T Banks<br />
Figure 1-7 shows the I/O <strong>and</strong> transceiver banks for the XC7K355T.<br />
FFG901 Package<br />
All HR banks <strong>and</strong> the GTX Quads are fully bonded out in this package.<br />
X-Ref Target - Figure 1-7<br />
Left I/O<br />
Column<br />
Banks<br />
Bank 17<br />
HR<br />
PLL04<br />
CMT<br />
MMCM05<br />
GTX Quad 117<br />
Quad<br />
GTX<br />
Bank 16<br />
HR<br />
PLL04<br />
CMT<br />
MMCM04<br />
GTX Quad 116<br />
Bank 15<br />
HR<br />
Bank 14<br />
HR<br />
PLL03<br />
CMT<br />
MMCM03<br />
PLL02<br />
CMT<br />
MMCM02<br />
16 BUFGs<br />
16 BUFGs<br />
GTX Quad 115<br />
GTX Quad 114<br />
Horizontal<br />
Center<br />
Bank 13<br />
HR<br />
PLL01<br />
CMT<br />
MMCM01<br />
GTX Quad 113<br />
Bank 12<br />
HR<br />
PLL00<br />
CMT<br />
MMCM00<br />
HROW<br />
GTX Quad 112<br />
CMT<br />
Backbone<br />
Clocking<br />
Backbone<br />
<strong>UG475</strong>_c1_11_060711<br />
Figure 1-7:<br />
XC7K355T Banks<br />
www.BDTIC.com/XILINX<br />
28 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Die Level Bank Numbering Overview<br />
XC7K410T Banks<br />
Figure 1-8 shows the I/O <strong>and</strong> transceiver banks for the XC7K410T.<br />
FBG676 <strong>and</strong> FFG676 Packages<br />
• HR banks 17 <strong>and</strong> 18 are not bonded out.<br />
• All HP banks are fully bonded out.<br />
• GTX Quads 117 <strong>and</strong> 118 are not bonded out.<br />
FBG900 <strong>and</strong> FFG900 Packages<br />
All HR <strong>and</strong> HP banks <strong>and</strong> the GTX Quads are fully bonded out in these packages.<br />
X-Ref Target - Figure 1-8<br />
Left I/O<br />
Column<br />
Banks<br />
Right I/O<br />
Column<br />
Banks<br />
Bank 18<br />
HR<br />
PLL06<br />
CMT<br />
MMCM06<br />
GTX Quad 118<br />
Quad<br />
GTX<br />
Bank 17<br />
HR<br />
PLL05<br />
CMT<br />
MMCM05<br />
GTX Quad 117<br />
Bank 16<br />
HR<br />
Bank 15<br />
HR<br />
PLL04<br />
CMT<br />
MMCM04<br />
PLL03<br />
CMT<br />
MMCM03<br />
16 BUFGs<br />
16 BUFGs<br />
GTX Quad 116<br />
GTX Quad 115<br />
Horizontal<br />
Center<br />
Bank 14<br />
HR<br />
PLL02<br />
CMT<br />
MMCM02<br />
PLL12<br />
CMT<br />
MMCM12<br />
Bank 34<br />
HP<br />
Bank 13<br />
HR<br />
PLL01<br />
CMT<br />
MMCM01<br />
PLL11<br />
CMT<br />
MMCM11<br />
Bank 33<br />
HP<br />
Bank 12<br />
HR<br />
PLL0<br />
CMT<br />
MMCM00<br />
HROW<br />
PLL10<br />
CMT<br />
MMCM10<br />
Bank 32<br />
HP<br />
Bank<br />
50 I/Os<br />
CMT<br />
Backbone<br />
Clocking<br />
Backbone<br />
CMT<br />
Backbone<br />
<strong>UG475</strong>_c1_12_081211<br />
Figure 1-8:<br />
XC7K410T Banks<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 29<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 1: <strong>Packaging</strong> Overview<br />
XC7K420T Banks<br />
Figure 1-9 shows the I/O <strong>and</strong> transceiver banks for the XC7K420T.<br />
FFG901 <strong>and</strong> FFG1156 Packages<br />
• All HR banks <strong>and</strong> the GTX Quads are fully bonded out in these packages.<br />
X-Ref Target - Figure 1-9<br />
Left I/O<br />
Column<br />
Banks<br />
Bank 17<br />
HR<br />
PLL06<br />
CMT<br />
MMCM06<br />
GTX Quad 117<br />
Quad<br />
GTX<br />
Bank 16<br />
HR<br />
PLL05<br />
CMT<br />
MMCM05<br />
GTX Quad 116<br />
Bank 15<br />
HR<br />
Bank 14<br />
HR<br />
PLL04<br />
CMT<br />
MMCM04<br />
PLL03<br />
CMT<br />
MMCM03<br />
16 BUFGs<br />
16 BUFGs<br />
GTX Quad 115<br />
GTX Quad 114<br />
Horizontal<br />
Center<br />
Bank 13<br />
HR<br />
PLL02<br />
CMT<br />
MMCM02<br />
GTX Quad 113<br />
Bank 12<br />
HR<br />
PLL01<br />
CMT<br />
MMCM01<br />
GTX Quad 112<br />
Bank 11<br />
HR<br />
PLL0<br />
CMT<br />
MMCM00<br />
HROW<br />
GTX Quad 111<br />
I/O Clocking<br />
Backbone<br />
CMT<br />
Backbone<br />
Clocking<br />
Backbone<br />
<strong>UG475</strong>_c1_13_060711<br />
Figure 1-9:<br />
XC7K420T Banks<br />
www.BDTIC.com/XILINX<br />
30 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Die Level Bank Numbering Overview<br />
XC7K480T Banks<br />
Figure 1-10 shows the I/O <strong>and</strong> transceiver banks for the XC7K480T.<br />
FFG901 Package<br />
• HR bank 18 is not fully bonded out.<br />
• GTX Quad bank 118 is not bonded out.<br />
FFG1156 Package<br />
All HR banks <strong>and</strong> the GTX Quads are fully bonded out in this package.<br />
X-Ref Target - Figure 1-10<br />
Left I/O<br />
Column<br />
Banks<br />
Bank 18<br />
HR<br />
PLL07<br />
CMT<br />
MMCM07<br />
GTX Quad 118<br />
Quad<br />
GTX<br />
Bank 17<br />
HR<br />
PLL06<br />
CMT<br />
MMCM06<br />
GTX Quad 117<br />
Bank 16<br />
HR<br />
PLL05<br />
CMT<br />
MMCM05<br />
GTX Quad 116<br />
Bank 15<br />
HR<br />
Bank 14<br />
HR<br />
PLL04<br />
CMT<br />
MMCM04<br />
PLL03<br />
CMT<br />
MMCM03<br />
16 BUFGs<br />
16 BUFGs<br />
GTX Quad 115<br />
GTX Quad 114<br />
Horizontal<br />
Center<br />
Bank 13<br />
HR<br />
PLL02<br />
CMT<br />
MMCM02<br />
GTX Quad 113<br />
Bank 12<br />
HR<br />
PLL01<br />
CMT<br />
MMCM01<br />
GTX Quad 112<br />
Bank 11<br />
HR<br />
PLL0<br />
CMT<br />
MMCM00<br />
HROW<br />
GTX<br />
I/O Clocking<br />
Quad 111<br />
Backbone<br />
CMT<br />
Backbone<br />
Clocking<br />
Backbone<br />
<strong>UG475</strong>_c1_14_060711<br />
Figure 1-10:<br />
XC7K480T Banks<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 31<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 1: <strong>Packaging</strong> Overview<br />
XC7V585T Banks<br />
Figure 1-11 shows the I/O <strong>and</strong> transceiver banks for the XC7V585T.<br />
FFG1157 Package<br />
• All HR banks (11, 12, <strong>and</strong> 13) are not bonded out.<br />
• HP banks 31, 32, <strong>and</strong> 33 are not bonded out.<br />
• GTX Quads 111, 112, 113, <strong>and</strong> 119 are not bonded out.<br />
FFG1761 Package<br />
• HR bank 11 is not bonded out.<br />
• All HP banks <strong>and</strong> the GTX Quads are fully bonded out in this package.<br />
X-Ref Target - Figure 1-11<br />
Left I/O<br />
Column<br />
Banks<br />
Right I/O<br />
Column<br />
Banks<br />
Bank 19<br />
HP<br />
PLL08<br />
CMT<br />
MMCM08<br />
PLL18<br />
CMT<br />
MMCM18<br />
Bank 39<br />
HP<br />
GTX Quad 119<br />
Bank 18<br />
HP<br />
PLL07<br />
CMT<br />
MMCM07<br />
PLL17<br />
CMT<br />
MMCM17<br />
Bank 38<br />
HP<br />
GTX Quad 118<br />
Bank 17<br />
HP<br />
PLL06<br />
CMT<br />
MMCM06<br />
PLL16<br />
CMT<br />
MMCM16<br />
Bank 37<br />
HP<br />
GTX Quad 117<br />
Bank 16<br />
HP<br />
PLL05<br />
CMT<br />
MMCM05<br />
16 BUFGs<br />
PLL15<br />
CMT<br />
MMCM15<br />
Bank 36<br />
HP<br />
GTX Quad 116<br />
Bank 15<br />
HP<br />
PLL04<br />
CMT<br />
MMCM04<br />
16 BUFGs<br />
PLL14<br />
CMT<br />
MMCM14<br />
Bank 35<br />
HP<br />
GTX Quad 115<br />
Bank 14<br />
HP<br />
PLL03<br />
CMT<br />
MMCM03<br />
PLL13<br />
CMT<br />
MMCM13<br />
Bank 34<br />
HP<br />
GTX Quad 114<br />
Bank 13<br />
HR<br />
PLL02<br />
CMT<br />
MMCM02<br />
PLL12<br />
CMT<br />
MMCM12<br />
Bank 33<br />
HP<br />
GTX Quad 113<br />
Bank<br />
50 I/Os<br />
Bank 12<br />
HR<br />
PLL01<br />
CMT<br />
MMCM01<br />
PLL11<br />
CMT<br />
MMCM11<br />
Bank 32<br />
HP<br />
GTX Quad 112<br />
Bank 11<br />
HR<br />
PLL00<br />
CMT<br />
MMCM00<br />
HROW<br />
PLL10<br />
CMT<br />
MMCM10<br />
Bank 31<br />
HP<br />
GTX Quad 111<br />
Clocking<br />
Backbone<br />
Figure 1-11:<br />
CMT<br />
Backbone<br />
XC7V585T Banks<br />
Horizontal Center<br />
<strong>UG475</strong>_c1_15_060711<br />
www.BDTIC.com/XILINX<br />
32 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Die Level Bank Numbering Overview<br />
XC7V1500T Banks<br />
Figure 1-12 shows the I/O <strong>and</strong> transceiver banks for the XC7V1500T.<br />
FLG1761 Package<br />
• HP bank 11 is not bonded out.<br />
• All the GTX Quads are fully bonded out in this package.<br />
X-Ref Target - Figure 1-12<br />
Left I/O<br />
Column<br />
Banks<br />
Right I/O<br />
Column<br />
Banks<br />
Bank 19<br />
HP<br />
PLL08<br />
CMT<br />
MMCM08<br />
BUFGs<br />
PLL18<br />
CMT<br />
MMCM18<br />
Bank 39<br />
HP<br />
GTX Quad 119<br />
Super Logic<br />
Region 2<br />
Bank 18<br />
HP<br />
PLL07<br />
CMT<br />
MMCM07<br />
BUFGs<br />
PLL17<br />
CMT<br />
MMCM17<br />
Bank 38<br />
HP<br />
GTX Quad 118<br />
Bank 17<br />
HP<br />
Bank 16<br />
HP<br />
PLL06<br />
CMT<br />
MMCM06<br />
PLL05<br />
CMT<br />
MMCM05<br />
BUFGs<br />
PLL16<br />
CMT<br />
MMCM16<br />
Interposer<br />
PLL15<br />
CMT<br />
MMCM15<br />
Bank 37<br />
HP<br />
Bank 36<br />
HP<br />
GTX Quad 117<br />
GTX Quad 116<br />
Super Logic<br />
Region 1<br />
Bank 15<br />
HP<br />
PLL04<br />
CMT<br />
MMCM04<br />
BUFGs<br />
PLL14<br />
CMT<br />
MMCM14<br />
Bank 35<br />
HP<br />
GTX Quad 115<br />
Bank 14<br />
HP<br />
Bank 13<br />
HP<br />
PLL03<br />
CMT<br />
MMCM03<br />
PLL02<br />
CMT<br />
MMCM02<br />
BUFGs<br />
PLL13<br />
CMT<br />
MMCM13<br />
Interposer<br />
PLL12<br />
CMT<br />
MMCM12<br />
Bank 34<br />
HP<br />
Bank 33<br />
HP<br />
GTX Quad 114<br />
GTX Quad 113<br />
Super Logic<br />
Region 0<br />
Bank 12<br />
HP<br />
PLL01<br />
CMT<br />
MMCM01<br />
BUFGs<br />
PLL11<br />
CMT<br />
MMCM11<br />
Bank 32<br />
HP<br />
GTX Quad 112<br />
Bank 11<br />
HP<br />
PLL00<br />
CMT<br />
MMCM00<br />
HROW<br />
PLL10<br />
CMT<br />
MMCM10<br />
Bank 31<br />
HP<br />
GTX Quad 111<br />
Clocking<br />
Backbone<br />
Figure 1-12:<br />
CMT<br />
Backbone<br />
XC7V1500T Banks<br />
Horizontal Center<br />
<strong>UG475</strong>_c1_16_090511<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 33<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 1: <strong>Packaging</strong> Overview<br />
XC7V2000T Banks<br />
Figure 1-13 shows the I/O <strong>and</strong> transceiver banks for the XC7V2000T.<br />
FHG1761 Package<br />
• HP banks 11, 20, 21, 22, 40, 41, <strong>and</strong> 42 are not bonded out.<br />
• GTX Quads 120, 121, <strong>and</strong> 122 are not bonded out.<br />
FLG1925 Package<br />
• All HP banks are fully bonded out in this package.<br />
• GTX Quads 111, 116, 117, 118, 119, 120, 121, <strong>and</strong> 122 are not bonded out.<br />
www.BDTIC.com/XILINX<br />
34 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Die Level Bank Numbering Overview<br />
X-Ref Target - Figure 1-13<br />
Left I/O<br />
Column<br />
Banks<br />
Right I/O<br />
Column<br />
Banks<br />
Bank 22<br />
HP<br />
PLL01<br />
CMT<br />
MMCM11<br />
BUFGs<br />
PLL11<br />
CMT<br />
MMCM111<br />
Bank 42<br />
HP<br />
GTX Quad 122<br />
Super Logic<br />
Region 3<br />
Bank 21<br />
HP<br />
PLL01<br />
CMT<br />
MMCM10<br />
BUFGs<br />
PLL11<br />
CMT<br />
MMCM110<br />
Bank 41<br />
HP<br />
GTX Quad 121<br />
Bank 20<br />
HP<br />
Bank 19<br />
HP<br />
PLL9<br />
CMT<br />
MMCM09<br />
PLL08<br />
CMT<br />
MMCM08<br />
Interposer<br />
BUFGs<br />
PLL19<br />
CMT<br />
MMCM19<br />
PLL18<br />
CMT<br />
MMCM18<br />
Bank 40<br />
HP<br />
Bank 39<br />
HP<br />
GTX Quad 120<br />
GTX Quad 119<br />
Super Logic<br />
Region 2<br />
Bank 18<br />
HP<br />
PLL07<br />
CMT<br />
MMCM07<br />
BUFGs<br />
PLL17<br />
CMT<br />
MMCM17<br />
Bank 38<br />
HP<br />
GTX Quad 118<br />
Bank 17<br />
HP<br />
Bank 16<br />
HP<br />
PLL06<br />
CMT<br />
MMCM06<br />
PLL05<br />
CMT<br />
MMCM05<br />
HROW<br />
BUFGs<br />
Interposer<br />
PLL16<br />
CMT<br />
MMCM16<br />
PLL15<br />
CMT<br />
MMCM15<br />
Bank 37<br />
HP<br />
Bank 36<br />
HP<br />
GTX Quad 117<br />
GTX Quad 116<br />
Super Logic<br />
Region 1<br />
Bank 15<br />
HP<br />
PLL04<br />
CMT<br />
MMCM04<br />
BUFGs<br />
PLL14<br />
CMT<br />
MMCM14<br />
Bank 35<br />
HP<br />
GTX Quad 115<br />
Bank 14<br />
HP<br />
Bank 13<br />
HP<br />
PLL03<br />
CMT<br />
MMCM03<br />
PLL02<br />
CMT<br />
MMCM02<br />
Interposer<br />
BUFGs<br />
PLL13<br />
CMT<br />
MMCM13<br />
PLL12<br />
CMT<br />
MMCM12<br />
Bank 34<br />
HP<br />
Bank 33<br />
HP<br />
GTX Quad 114<br />
GTX Quad 113<br />
Super Logic<br />
Region 0<br />
Bank 12<br />
HP<br />
PLL01<br />
CMT<br />
MMCM01<br />
BUFGs<br />
PLL11<br />
CMT<br />
MMCM11<br />
Bank 32<br />
HP<br />
GTX Quad 112<br />
Bank 11<br />
HP<br />
PLL00<br />
CMT<br />
MMCM00<br />
PLL10<br />
CMT<br />
MMCM10<br />
Bank 31<br />
HP<br />
GTX Quad 111<br />
CMT<br />
Backbone<br />
Clocking<br />
Backbone<br />
CMT<br />
Backbone<br />
Horizontal Center<br />
<strong>UG475</strong>_c1_17_090511<br />
Figure 1-13:<br />
XC7V2000T Banks<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 35<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 1: <strong>Packaging</strong> Overview<br />
XC7VX330T Banks<br />
Figure 1-14 shows the I/O <strong>and</strong> transceiver banks for the XC7VX330T.<br />
FFG1157 Package<br />
• HR bank 13 is not bonded out.<br />
• HP bank 33 is not bonded out.<br />
• GTH Quads 113 <strong>and</strong> 119 are not bonded out.<br />
FFG1761 Package<br />
All HR <strong>and</strong> HP banks <strong>and</strong> the GTH Quads are fully bonded out in this package.<br />
X-Ref Target - Figure 1-14<br />
Left I/O<br />
Column<br />
Banks<br />
Right I/O<br />
Column<br />
Banks<br />
Bank 19<br />
HP<br />
PLL06<br />
CMT<br />
MMCM06<br />
PLL16<br />
CMT<br />
MMCM16<br />
Bank 39<br />
HP<br />
GTH Quad 119<br />
Bank 18<br />
HP<br />
PLL05<br />
CMT<br />
MMCM05<br />
PLL15<br />
CMT<br />
MMCM15<br />
Bank 38<br />
HP<br />
GTH Quad 118<br />
Bank 17<br />
HP<br />
Bank 16<br />
HP<br />
PLL04<br />
CMT<br />
MMCM04<br />
PLL03<br />
CMT<br />
MMCM03<br />
16 BUFGs<br />
16 BUFGs<br />
PLL14<br />
CMT<br />
MMCM14<br />
PLL13<br />
CMT<br />
MMCM13<br />
Bank 37<br />
HP<br />
Bank 36<br />
HP<br />
GTH Quad 117<br />
GTH Quad 116<br />
Horizontal<br />
Center<br />
Bank 15<br />
HP<br />
PLL02<br />
CMT<br />
MMCM02<br />
PLL12<br />
CMT<br />
MMCM12<br />
Bank 35<br />
HP<br />
GTH Quad 115<br />
Bank<br />
50 I/Os<br />
Bank 14<br />
HP<br />
PLL01<br />
CMT<br />
MMCM01<br />
PLL11<br />
CMT<br />
MMCM11<br />
Bank 34<br />
HP<br />
GTH Quad 114<br />
Bank 13<br />
HR<br />
PLL00<br />
CMT<br />
MMCM00<br />
HROW<br />
PLL10<br />
CMT<br />
MMCM10<br />
Bank 33<br />
HP<br />
GTH Quad 113<br />
CMT<br />
Backbone<br />
Clocking<br />
Backbone<br />
CMT<br />
Backbone<br />
UG476_c1_18_060711<br />
Figure 1-14:<br />
XC7VX330T Banks<br />
www.BDTIC.com/XILINX<br />
36 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Die Level Bank Numbering Overview<br />
XC7VX415T Banks<br />
Figure 1-15 shows the I/O <strong>and</strong> transceiver banks for the XC7VX415T.<br />
FFG1157 Package<br />
• All HP banks are fully bonded out.<br />
• GTH Quads 119, 214, 215, 216, 217, 218, <strong>and</strong> 219 are not bonded out.<br />
FFG1158 Package<br />
• HP banks 18, 19, 37, 38, <strong>and</strong> 39 are not bonded out.<br />
• GTH Quads are fully bonded out in this package.<br />
FFG1927 Package<br />
All HP banks <strong>and</strong> the GTH Quads are fully bonded out in this package.<br />
X-Ref Target - Figure 1-15<br />
Left I/O<br />
Column<br />
Banks<br />
Right I/O<br />
Column<br />
Banks<br />
GTH Quad 219<br />
Bank 19<br />
HP<br />
PLL05<br />
CMT<br />
MMCM05<br />
PLL15<br />
CMT<br />
MMCM15<br />
Bank 39<br />
HP<br />
GTH Quad 119<br />
GTH Quad 218<br />
Bank 18<br />
HP<br />
PLL04<br />
CMT<br />
MMCM04<br />
HROW<br />
PLL14<br />
CMT<br />
MMCM14<br />
Bank 38<br />
HP<br />
GTH Quad 118<br />
GTH Quad 217<br />
Bank 17<br />
HP<br />
PLL03<br />
CMT<br />
MMCM03<br />
PLL13<br />
CMT<br />
MMCM13<br />
Bank 37<br />
HP<br />
GTH Quad 117<br />
GTH Quad 216<br />
Bank 16<br />
HP<br />
PLL02<br />
CMT<br />
MMCM02<br />
PLL12<br />
CMT<br />
MMCM12<br />
Bank 36<br />
HP<br />
GTH Quad 116<br />
GTH Quad 215<br />
Bank 15<br />
HP<br />
PLL01<br />
CMT<br />
MMCM01<br />
16 BUFGs<br />
PLL11<br />
CMT<br />
MMCM11<br />
Bank 35<br />
HP<br />
GTH Quad 115<br />
GTH Quad 214<br />
Bank 14<br />
HP<br />
PLL00<br />
CMT<br />
MMCM00<br />
16 BUFGs<br />
PLL10<br />
CMT<br />
MMCM10<br />
Bank 34<br />
HP<br />
GTH Quad 114<br />
CMT<br />
Backbone<br />
Clocking<br />
Backbone<br />
CMT<br />
Backbone<br />
Horizontal Center<br />
UG476_c1_19_071411<br />
Figure 1-15:<br />
XC7VX415T Banks<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 37<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 1: <strong>Packaging</strong> Overview<br />
XC7VX485T Banks<br />
Figure 1-16 shows the I/O <strong>and</strong> transceiver banks for the XC7VX485T.<br />
FFG1157 Package<br />
• HP banks 13 <strong>and</strong> 33 are not bonded out.<br />
• GTX Quads 113, 119, 213, 214, 215, 216, 217, 218, <strong>and</strong> 219 are not bonded out.<br />
FFG1158 Package<br />
• HP banks 13, 18, 19, 33, 37, 38, <strong>and</strong> 39 are not bonded out.<br />
• GTX Quads 113 <strong>and</strong> 213 are not bonded out.<br />
FFG1761 Package<br />
• All HP banks are fully bonded out in this package.<br />
• GTX Quads 213, 214, 215, 216, 217, 218, <strong>and</strong> 219 are not bonded out.<br />
FFG1927 Package<br />
• HP banks 13 <strong>and</strong> 33 are not bonded out.<br />
• All the GTX Quads are fully bonded out in this package.<br />
FFG1930 Package<br />
• All HP banks are fully bonded out in this package.<br />
• GTX Quads 119, 213, 214, 215, 216, 217, 218, <strong>and</strong> 219 are not bonded out.<br />
www.BDTIC.com/XILINX<br />
38 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Die Level Bank Numbering Overview<br />
X-Ref Target - Figure 1-16<br />
Left I/O<br />
Column<br />
Banks<br />
Right I/O<br />
Column<br />
Banks<br />
GTX Quad 219<br />
Bank 19<br />
HP<br />
PLL06<br />
CMT<br />
MMCM06<br />
PLL16<br />
CMT<br />
MMCM16<br />
Bank 39<br />
HP<br />
GTX Quad 119<br />
GTX Quad 218<br />
Bank 18<br />
HP<br />
PLL05<br />
CMT<br />
MMCM05<br />
PLL15<br />
CMT<br />
MMCM15<br />
Bank 38<br />
HP<br />
GTX Quad 118<br />
GTX Quad 217<br />
Bank 17<br />
HP<br />
PLL04<br />
CMT<br />
MMCM04<br />
16 BUFGs<br />
PLL14<br />
CMT<br />
MMCM14<br />
Bank 37<br />
HP<br />
GTX Quad 117<br />
GTX Quad 216<br />
Bank 16<br />
HP<br />
PLL03<br />
CMT<br />
MMCM03<br />
16 BUFGs<br />
PLL13<br />
CMT<br />
MMCM13<br />
Bank 36<br />
HP<br />
GTX Quad 116<br />
GTX Quad 215<br />
Bank 15<br />
HP<br />
PLL02<br />
CMT<br />
MMCM02<br />
PLL12<br />
CMT<br />
MMCM12<br />
Bank 35<br />
HP<br />
GTX Quad 115<br />
GTX Quad 214<br />
Bank 14<br />
HP<br />
PLL01<br />
CMT<br />
MMCM01<br />
PLL11<br />
CMT<br />
MMCM11<br />
Bank 34<br />
HP<br />
GTX Quad 114<br />
GTX Quad 213<br />
Bank 13<br />
HP<br />
PLL00<br />
CMT<br />
MMCM00<br />
HROW<br />
PLL10<br />
CMT<br />
MMCM10<br />
Bank 33<br />
HP<br />
GTX Quad 113<br />
CMT<br />
Backbone<br />
Clocking<br />
Backbone<br />
CMT<br />
Backbone<br />
Horizontal Center<br />
UG476_c1_20_060711<br />
Figure 1-16:<br />
XC7VX485T Banks<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 39<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 1: <strong>Packaging</strong> Overview<br />
XC7VX550T Banks<br />
Figure 1-17 shows the I/O <strong>and</strong> transceiver banks for the XC7VX550T.<br />
FFG1158 Package<br />
• HP banks 12, 13, 18, 19, 32, 33, 37, 38, <strong>and</strong> 39 are not bonded out.<br />
• GTH Quads 112, 113, 212, <strong>and</strong> 213 are not bonded out.<br />
FFG1927 Package<br />
• HP banks 12, 13, 32, <strong>and</strong> 33 are not bonded out.<br />
• All GTH Quads are fully bonded out in this package.<br />
X-Ref Target - Figure 1-17<br />
Left I/O<br />
Column<br />
Banks<br />
Right I/O<br />
Column<br />
Banks<br />
GTH Quad 219<br />
Bank 19<br />
HP<br />
PLL05<br />
CMT<br />
MMCM05<br />
PLL15<br />
CMT<br />
MMCM15<br />
Bank 39<br />
HP<br />
GTH Quad 119<br />
GTH Quad 218<br />
Bank 18<br />
HP<br />
PLL04<br />
CMT<br />
MMCM04<br />
PLL14<br />
CMT<br />
MMCM14<br />
Bank 38<br />
HP<br />
GTH Quad 118<br />
GTH Quad 217<br />
Bank 17<br />
HP<br />
PLL05<br />
CMT<br />
MMCM05<br />
PLL15<br />
CMT<br />
MMCM15<br />
Bank 37<br />
HP<br />
GTH Quad 117<br />
GTH Quad 216<br />
Bank 16<br />
HP<br />
PLL04<br />
CMT<br />
MMCM04<br />
PLL14<br />
CMT<br />
MMCM14<br />
Bank 36<br />
HP<br />
GTH Quad 116<br />
GTH Quad 215<br />
Bank 15<br />
HP<br />
PLL03<br />
CMT<br />
MMCM03<br />
16 BUFGs<br />
PLL13<br />
CMT<br />
MMCM13<br />
Bank 35<br />
HP<br />
GTH Quad 115<br />
GTH Quad 214<br />
Bank 14<br />
HP<br />
PLL02<br />
CMT<br />
MMCM02<br />
16 BUFGs<br />
PLL12<br />
CMT<br />
MMCM12<br />
Bank 34<br />
HP<br />
GTH Quad 114<br />
GTH Quad 213<br />
Bank 13<br />
HP<br />
PLL01<br />
CMT<br />
MMCM01<br />
PLL11<br />
CMT<br />
MMCM11<br />
Bank 33<br />
HP<br />
GTH Quad 114<br />
GTH Quad 212<br />
Bank 12<br />
HP<br />
PLL00<br />
CMT<br />
MMCM00<br />
HROW<br />
PLL10<br />
CMT<br />
MMCM10<br />
Bank 32<br />
HP<br />
GTH Quad 112<br />
CMT<br />
Backbone<br />
Clocking<br />
Backbone<br />
CMT<br />
Backbone<br />
Horizontal Center<br />
<strong>UG475</strong>_c1_22_081211<br />
Figure 1-17:<br />
XC7VX550T Banks<br />
www.BDTIC.com/XILINX<br />
40 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Die Level Bank Numbering Overview<br />
XC7VX690T Banks<br />
Figure 1-18 shows the I/O <strong>and</strong> transceiver banks for the XC7VX690T.<br />
FFG1157 Package<br />
• HP banks 10, 11, 12, 13, 30, 31, 32, <strong>and</strong> 33 are not bonded out.<br />
• GTH Quads 110, 111, 112, 113, 119, 210, 211, 212, 213, 214, 215, 216, 217, 218, <strong>and</strong> 219<br />
are not bonded out.<br />
FFG1158 Package<br />
• HP banks 10, 11, 12, 13, 18, 19, 30, 31, 32, 33, 37, 38, <strong>and</strong> 39 are not bonded out.<br />
• GTH Quads 110, 111, 112, 113, 210, 211, 212, <strong>and</strong> 213 are not bonded out.<br />
FFG1761 Package<br />
• HP banks 10, 11, <strong>and</strong> 30 are not bonded out.<br />
• GTH Quads 110, 210, 211, 212, 213, 214, 215, 216, 217, 218, <strong>and</strong> 219 are not bonded out.<br />
FFG1926 Package<br />
• HP bank 17 is partially bonded out.<br />
• HP banks 18, 19, 37, 38, <strong>and</strong> 39 are not bonded out.<br />
• GTH Quads 110, 119, 210, <strong>and</strong> 219 are not bonded out.<br />
FFG1927 Package<br />
• HP banks 10, 11, 12, 13, 30, 31, 32, <strong>and</strong> 33 are not bonded out.<br />
• All GTH Quads are fully bonded out in this package.<br />
FFG1930 Package<br />
• All HP banks are fully bonded out in this package.<br />
• GTH Quads 110, 111, 112, 119, 210, 211, 212, 213, 214, 215, 216, 217, 218, <strong>and</strong> 219 are not<br />
bonded out.<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 41<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 1: <strong>Packaging</strong> Overview<br />
X-Ref Target - Figure 1-18<br />
Left I/O<br />
Column<br />
Banks<br />
Right I/O<br />
Column<br />
Banks<br />
GTH Quad 219<br />
Bank 19<br />
HP<br />
PLL09<br />
CMT<br />
MMCM09<br />
PLL19<br />
CMT<br />
MMCM19<br />
Bank 39<br />
HP<br />
GTH Quad 119<br />
GTH Quad 218<br />
Bank 18<br />
HP<br />
PLL08<br />
CMT<br />
MMCM08<br />
PLL18<br />
CMT<br />
MMCM18<br />
Bank 38<br />
HP<br />
GTH Quad 118<br />
GTH Quad 217<br />
Bank 17<br />
HP<br />
PLL07<br />
CMT<br />
MMCM07<br />
PLL17<br />
CMT<br />
MMCM17<br />
Bank 37<br />
HP<br />
GTH Quad 117<br />
GTH Quad 216<br />
Bank 16<br />
HP<br />
PLL06<br />
CMT<br />
MMCM06<br />
PLL16<br />
CMT<br />
MMCM16<br />
Bank 36<br />
HP<br />
GTH Quad 116<br />
GTH Quad 215<br />
Bank 15<br />
HP<br />
PLL05<br />
CMT<br />
MMCM05<br />
16 BUFGs<br />
PLL15<br />
CMT<br />
MMCM15<br />
Bank 35<br />
HP<br />
GTH Quad 115<br />
GTH Quad 214<br />
Bank 14<br />
HP<br />
PLL04<br />
CMT<br />
MMCM04<br />
16 BUFGs<br />
PLL14<br />
CMT<br />
MMCM14<br />
Bank 34<br />
HP<br />
GTH Quad 114<br />
GTH Quad 213<br />
Bank 13<br />
HP<br />
PLL03<br />
CMT<br />
MMCM03<br />
PLL13<br />
CMT<br />
MMCM13<br />
Bank 33<br />
HP<br />
GTH Quad 113<br />
GTH Quad 212<br />
Bank 12<br />
HP<br />
PLL02<br />
CMT<br />
MMCM02<br />
PLL12<br />
CMT<br />
MMCM12<br />
Bank 32<br />
HP<br />
GTH Quad 112<br />
GTH Quad 211<br />
Bank 11<br />
HP<br />
PLL01<br />
CMT<br />
MMCM01<br />
PLL11<br />
CMT<br />
MMCM11<br />
Bank 31<br />
HP<br />
GTH Quad 111<br />
GTH Quad 210<br />
Bank 10<br />
HP<br />
PLL00<br />
CMT<br />
MMCM00<br />
HROW<br />
PLL10<br />
CMT<br />
MMCM10<br />
Bank 30<br />
HP<br />
GTH Quad 110<br />
CMT<br />
Backbone<br />
Clocking<br />
Backbone<br />
CMT<br />
Backbone<br />
Horizontal Center<br />
<strong>UG475</strong>_c1_22_081211<br />
Figure 1-18:<br />
XC7VX690T Banks<br />
www.BDTIC.com/XILINX<br />
42 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Die Level Bank Numbering Overview<br />
XC7VX980T Banks<br />
Figure 1-19 shows the I/O <strong>and</strong> transceiver banks for the XC7VX980T.<br />
FFG1926 Package<br />
• HP bank 17 is partially bonded out.<br />
• HP banks 18, 37, <strong>and</strong> 38 are not bonded out.<br />
• GTH Quads 110 <strong>and</strong> 210 are not bonded out.<br />
FFG1928 Package<br />
• HP bank 16 is partially bonded out.<br />
• HP banks 10, 11, 12, 17, 18, 30, 31, <strong>and</strong> 32 are not bonded out.<br />
• All GTH Quads are fully bonded out in this package.<br />
FFG1930 Package<br />
• All HP banks are fully bonded out in this package.<br />
• GTH Quads 110, 111, 112, 210, 211, 212, 213, 214, 215, 216, 217, <strong>and</strong> 218 are not bonded<br />
out.<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 43<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 1: <strong>Packaging</strong> Overview<br />
X-Ref Target - Figure 1-19<br />
Left I/O<br />
Column<br />
Banks<br />
Right I/O<br />
Column<br />
Banks<br />
GTH Quad 218<br />
Bank 18<br />
HP<br />
PLL08<br />
CMT<br />
MMCM08<br />
HROW<br />
PLL18<br />
CMT<br />
MMCM18<br />
Bank 38<br />
HP<br />
GTH Quad 118<br />
GTH Quad 217<br />
Bank 17<br />
HP<br />
PLL07<br />
CMT<br />
MMCM07<br />
PLL17<br />
CMT<br />
MMCM17<br />
Bank 37<br />
HP<br />
GTH Quad 117<br />
GTH Quad 216<br />
Bank 16<br />
HP<br />
PLL06<br />
CMT<br />
MMCM06<br />
PLL16<br />
CMT<br />
MMCM16<br />
Bank 36<br />
HP<br />
GTH Quad 116<br />
GTH Quad 215<br />
Bank 15<br />
HP<br />
PLL05<br />
CMT<br />
MMCM05<br />
BUFGs<br />
PLL15<br />
CMT<br />
MMCM15<br />
Bank 35<br />
HP<br />
GTH Quad 115<br />
GTH Quad 214<br />
Bank 14<br />
HP<br />
PLL04<br />
CMT<br />
MMCM04<br />
BUFGs<br />
PLL14<br />
CMT<br />
MMCM14<br />
Bank 34<br />
HP<br />
GTH Quad 114<br />
GTH Quad 213<br />
Bank 13<br />
HP<br />
PLL03<br />
CMT<br />
MMCM03<br />
PLL13<br />
CMT<br />
MMCM13<br />
Bank 33<br />
HP<br />
GTH Quad 113<br />
GTH Quad 212<br />
Bank 12<br />
HP<br />
PLL02<br />
CMT<br />
MMCM02<br />
PLL12<br />
CMT<br />
MMCM12<br />
Bank 32<br />
HP<br />
GTH Quad 112<br />
GTH Quad 211<br />
Bank 11<br />
HP<br />
PLL01<br />
CMT<br />
MMCM01<br />
PLL11<br />
CMT<br />
MMCM11<br />
Bank 31<br />
HP<br />
GTH Quad 111<br />
GTH Quad 210<br />
Bank 10<br />
HP<br />
PLL00<br />
CMT<br />
MMCM00<br />
PLL10<br />
CMT<br />
MMCM10<br />
Bank 30<br />
HP<br />
GTH Quad 110<br />
CMT<br />
Backbone<br />
Clocking<br />
Backbone<br />
CMT<br />
Backbone<br />
Horizontal Center<br />
<strong>UG475</strong>_c1_23_081211<br />
Figure 1-19:<br />
XC7VX980T Banks<br />
www.BDTIC.com/XILINX<br />
44 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Die Level Bank Numbering Overview<br />
XC7VX1140T Banks<br />
Figure 1-20 shows the I/O <strong>and</strong> transceiver banks for the XC7VX1140T.<br />
FLG1928 Package<br />
• HP bank 16 is partially bonded out.<br />
• HP banks 10, 11, 12, 17, 18, 19, 20, 21, 30, 31, 32, 39, 40, <strong>and</strong> 41 are not bonded out.<br />
• All GTH Quads are fully bonded out in this package.<br />
FLG1930 Package<br />
• HP banks 40 <strong>and</strong> 41 are not bonded out.<br />
• GTH Quads 110, 111, 112, 119, 120, 121, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219,<br />
220, <strong>and</strong> 221 are not bonded out.<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 45<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 1: <strong>Packaging</strong> Overview<br />
X-Ref Target - Figure 1-20<br />
Left I/O<br />
Column Banks<br />
Right I/O<br />
Column Banks<br />
GTH Quad 221<br />
Bank 21<br />
HP<br />
PLL08<br />
CMT<br />
MMCM08<br />
BUFGs<br />
HROW<br />
PLL18<br />
CMT<br />
MMCM18<br />
Bank 41<br />
HP<br />
GTH Quad 121<br />
GTH Quad 220<br />
GTH Quad 219<br />
GTH Quad 218<br />
Bank 20<br />
HP<br />
Bank 19<br />
HP<br />
Bank 18<br />
HP<br />
PLL07<br />
CMT<br />
MMCM07<br />
PLL06<br />
CMT<br />
MMCM06<br />
PLL08<br />
CMT<br />
MMCM08<br />
Super<br />
Logic<br />
Region 3<br />
BUFGs<br />
BUFGs<br />
Interposer<br />
PLL17<br />
CMT<br />
MMCM17<br />
PLL16<br />
CMT<br />
MMCM16<br />
PLL18<br />
CMT<br />
MMCM18<br />
Bank 40<br />
HP<br />
Bank 39<br />
HP<br />
Bank 38<br />
HP<br />
GTH Quad 120<br />
GTH Quad 119<br />
GTH Quad 118<br />
GTH Quad 217<br />
GTH Quad 216<br />
GTH Quad 215<br />
Bank 17<br />
HP<br />
Bank 16<br />
HP<br />
Bank 15<br />
HP<br />
PLL07<br />
CMT<br />
MMCM07<br />
PLL06<br />
CMT<br />
MMCM06<br />
PLL05<br />
CMT<br />
MMCM05<br />
Super<br />
Logic<br />
Region 2<br />
BUFGs<br />
BUFGs<br />
Interposer<br />
PLL17<br />
CMT<br />
MMCM17<br />
PLL16<br />
CMT<br />
MMCM16<br />
PLL15<br />
CMT<br />
MMCM15<br />
Bank 37<br />
HP<br />
Bank 36<br />
HP<br />
Bank 35<br />
HP<br />
GTH Quad 117<br />
GTH Quad 116<br />
GTH Quad 115<br />
GTH Quad 214<br />
GTH Quad 213<br />
GTH Quad 212<br />
Bank 14<br />
HP<br />
Bank 13<br />
HP<br />
Bank 12<br />
HP<br />
PLL04<br />
CMT<br />
MMCM04<br />
PLL03<br />
CMT<br />
MMCM03<br />
PLL02<br />
CMT<br />
MMCM02<br />
Super<br />
Logic<br />
Region 1<br />
BUFGs<br />
BUFGs<br />
Interposer<br />
PLL14<br />
CMT<br />
MMCM14<br />
PLL13<br />
CMT<br />
MMCM13<br />
PLL12<br />
CMT<br />
MMCM12<br />
Bank 34<br />
HP<br />
Bank 33<br />
HP<br />
Bank 32<br />
HP<br />
GTH Quad 114<br />
GTH Quad 113<br />
GTH Quad 112<br />
GTH Quad 211<br />
GTH Quad 210<br />
Bank 11<br />
HP<br />
Bank 10<br />
HP<br />
PLL01<br />
CMT<br />
MMCM01<br />
PLL00<br />
CMT<br />
MMCM00<br />
Super<br />
Logic<br />
Region 0<br />
BUFGs<br />
PLL11<br />
CMT<br />
MMCM11<br />
PLL10<br />
CMT<br />
MMCM10<br />
Bank 31<br />
HP<br />
Bank 30<br />
HP<br />
GTH Quad 111<br />
GTH Quad 110<br />
CMT<br />
Backbone<br />
Clocking<br />
Backbone<br />
CMT<br />
Backbone<br />
Horizontal Center<br />
<strong>UG475</strong>_c1_24_090511<br />
Figure 1-20:<br />
XC7VX1140T Banks<br />
Note: The figures for some Virtex-7 <strong>FPGAs</strong> are in development.<br />
www.BDTIC.com/XILINX<br />
46 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 2<br />
7 <strong>Series</strong> <strong>FPGAs</strong> Package Files<br />
About ASCII Package Files<br />
The ASCII files for each package include a comma-separated-values (CSV) version <strong>and</strong> a<br />
text version optimized for a browser or text editor. Each of the files consists of the<br />
following:<br />
• Device/Package name (FPGA Family—Device—Package), date <strong>and</strong> time of creation<br />
• Eight columns containing data for each pin:<br />
• Pin—Pin location on the package.<br />
• Pin Name—The name of the assigned pin.<br />
• Memory Byte Group—Memory byte group between 0 <strong>and</strong> 3. For more<br />
information on the memory byte group, see UG586, 7 <strong>Series</strong> <strong>FPGAs</strong> Memory<br />
Interface Solutions User Guide.<br />
• Bank—Bank number.<br />
• V CCAUX Group—Number corresponding to the V CCAUX_IO power supply for the<br />
given pin. V CCAUX is shown for packages with only one V CCAUX group.<br />
• Super Logic Region—Number corresponding to the super logic region (SLR) in<br />
the devices implemented with stacked silicon interconnect (SSI) technology.<br />
• I/O Type—CONFIG, HR, HP, or GT (GTP, GTX, GTH, GTZ) depending on the<br />
I/O type. For more information on the I/O type, see UG471, 7 <strong>Series</strong> <strong>FPGAs</strong><br />
SelectIO Resources User Guide.<br />
• No-Connect—This list of devices is used for migration between devices that have<br />
the same package size <strong>and</strong> are not connected at that specific pin.<br />
• Total number of pins in the package.<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 47<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 2: 7 <strong>Series</strong> <strong>FPGAs</strong> Package Files<br />
ASCII <strong>Pinout</strong> Files<br />
This chapter includes the pinout information tables for the following device/packages.<br />
Note: All package files are ASCII files in TXT <strong>and</strong> CSV file format.<br />
To download all available Artix-7 <strong>FPGAs</strong> package/device/pinout files click here:<br />
http://www.xilinx.com/support/packagefiles/artix-7-pkgs.htm<br />
Note: Only the available files listed in Table 2-1 are linked <strong>and</strong> consolidated in the above ZIP file.<br />
Table 2-1: Artix-7 <strong>FPGAs</strong> Package/Device <strong>Pinout</strong> Files<br />
Device CPG236 CSG225 CSG324 FTG256 FGG484 FGG676 FBG484 FBG676 FFG1156<br />
XC7A8 CPG236 CSG324 FTG256<br />
XC7A15 CPG236 CSG324 FTG256<br />
XC7A30T CSG225 CSG324 FTG256 FGG484<br />
XC7A50T CSG225 CSG324 FTG256 FGG484<br />
XC7A100T CSG324 FTG256 FGG484 FGG676<br />
XC7A200T FBG484 FBG676<br />
XC7A350T FBG484 FBG676 FFG1156<br />
To download all available Kintex-7 <strong>FPGAs</strong> package/device/pinout files click here:<br />
http://www.xilinx.com/support/packagefiles/kintex-7-pkgs.htm<br />
Table 2-2: Kintex-7 <strong>FPGAs</strong> Package/Device <strong>Pinout</strong> Files<br />
Device FB(G)484 FB(G)676 FB(G)900 FF(G)676 FF(G)900 FF(G)901 FF(G)1156<br />
XC7K70T FBG484 FBG676<br />
XC7K160T<br />
FB484/<br />
FBG484<br />
FB676/<br />
FBG676<br />
FF676/<br />
FFG676<br />
XC7K325T<br />
FB676/<br />
FBG676<br />
FB900/<br />
FBG900<br />
FF676/<br />
FFG676<br />
FF900/<br />
FFG900<br />
XC7K355T<br />
FF901/<br />
FFG901<br />
XC7K410T<br />
FB676/<br />
FBG676<br />
FB900/<br />
FBG900<br />
FF676/<br />
FFG676<br />
FF900/<br />
FFG900<br />
XC7K420T<br />
XC7K480T<br />
FF901/<br />
FFG901<br />
FF901/<br />
FFG901<br />
FF1156/<br />
FFG1156<br />
FF1156/<br />
FFG1156<br />
www.BDTIC.com/XILINX<br />
48 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
ASCII <strong>Pinout</strong> Files<br />
Table 2-3:<br />
Device<br />
To download all available Virtex-7 <strong>FPGAs</strong> package/device/pinout files click here:<br />
http://www.xilinx.com/support/packagefiles/virtex-7-pkgs.htm<br />
Note: Only the available files listed in Table 2-3 are linked <strong>and</strong> consolidated in the above ZIP file.<br />
Virtex-7 <strong>FPGAs</strong> Package/Device <strong>Pinout</strong> Files<br />
FF(G) FF(G) FF(G) FF(G) FF(G) FF(G) FF(G) FL(G) FL(G) FL(G) FL(G) FH(G)<br />
1157 1158 1761 1926 1927 1928 1930 1761 1925 1928 1930 1761<br />
XC7V585T<br />
FF1157/<br />
FFG1157<br />
FF1761/<br />
FFG1761<br />
XC7V1500T<br />
FL1761/<br />
FLG1761<br />
XC7V2000T<br />
FL1925/<br />
FLG1925<br />
FH1761/<br />
FHG1761<br />
XC7VX330T<br />
FF1157/<br />
FFG1157<br />
FF1761/<br />
FFG1761<br />
XC7VX415T<br />
FF1157/<br />
FFG1157<br />
FF1158/<br />
FFG1158<br />
FF1927/<br />
FFG1927<br />
XC7VX485T<br />
FF1157/<br />
FFG1157<br />
FF1158/<br />
FFG1158<br />
FF1761/<br />
FFG1761<br />
FF1927/<br />
FFG1927<br />
FF1930/<br />
FFG1930<br />
XC7VX550T<br />
FF1158/<br />
FFG1158<br />
FF1927/<br />
FFG1927<br />
XC7VX690T<br />
XC7VX980T<br />
FF1157/<br />
FFG1157<br />
FF1158/<br />
FFG1158<br />
FF1761/<br />
FFG1761<br />
FF1926/<br />
FFG1926<br />
FF1926/<br />
FFG1926<br />
FF1927/<br />
FFG1927<br />
FF1928/<br />
FFG1928<br />
FF1930/<br />
FFG1930<br />
FF1930/<br />
FFG1930<br />
XC7VX1140T<br />
FL1928/<br />
FLG1928<br />
FL1930/<br />
FLG1930<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 49<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 2: 7 <strong>Series</strong> <strong>FPGAs</strong> Package Files<br />
www.BDTIC.com/XILINX<br />
50 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3<br />
Device Diagrams<br />
Summary<br />
This chapter provides pinout, I/O bank, high-performance <strong>and</strong> high-range I/O bank,<br />
memory groupings, <strong>and</strong> power <strong>and</strong> ground placement diagrams for each 7 series FPGA<br />
package/device combination. Some figures for Artix-7 <strong>FPGAs</strong> <strong>and</strong> Virtex-7 <strong>FPGAs</strong> are in<br />
development.<br />
• Artix-7 <strong>FPGAs</strong> Device Diagrams Cross-Reference, page 52<br />
• Kintex-7 <strong>FPGAs</strong> Device Diagrams Cross-Reference, page 57<br />
• Virtex-7 <strong>FPGAs</strong> Device Diagrams Cross Reference, page 97<br />
The figures provide a top-view perspective.<br />
The symbols for the multi-function I/O pins are represented by only one of the available<br />
pin functions; with precedence (by functionality) in this order:<br />
• ADV_B, FCS_B, FOE_B, MOSI, FWE_B, DOUT_CSO_B, CSI_B, PUDC_B, or RDWR_B<br />
• RS0–RS1<br />
• AD0P/AD0N–AD15P/AD15N<br />
• EMCCLK<br />
• VRN, VRP, or VREF<br />
• D00–D31<br />
• A00–A28<br />
• DQS, MRCC, or SRCC<br />
For example, a pin description such as IO_L8P_SRCC_12 is represented with a SRCC<br />
symbol, a pin description such as IO_L19N_T3_A09_D25_VREF_14 is represented with a<br />
VREF symbol, <strong>and</strong> a pin description such as IO_L21N_T3_DQS_A06_D22_14 is<br />
represented with a D0–D31 symbol.<br />
Note: The available files are listed in Table 3-1, Table 3-2, <strong>and</strong> Table 3-3 are linked. Figures for<br />
some Artix-7 <strong>FPGAs</strong> <strong>and</strong> Virtex-7 <strong>FPGAs</strong> are in development.<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 51<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
Artix-7 <strong>FPGAs</strong> Device Diagrams<br />
Table 3-1: Artix-7 <strong>FPGAs</strong> Device Diagrams Cross-Reference<br />
Device CPG236 CSG225 CSG324 FTG256 FGG484 FGG676 FBG484 FBG676 FFG1156<br />
XC7A8 page 52<br />
XC7A15 page 52<br />
XC7A30T page 55<br />
XC7A50T page 55<br />
XC7A100T page 55<br />
XC7A200T<br />
XC7A350T<br />
Note: The available files are listed in Table 3-1 are linked. Figures for some Artix-7 <strong>FPGAs</strong> are in<br />
development.<br />
CSG324 Package—XC7A8 <strong>and</strong> XC7A15<br />
X-Ref Target - Figure 3-1<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18<br />
A<br />
n<br />
n<br />
n<br />
A<br />
B<br />
n<br />
n<br />
B<br />
C<br />
n<br />
n<br />
n<br />
C<br />
D<br />
n<br />
n<br />
D<br />
E<br />
C<br />
K<br />
I<br />
M<br />
O<br />
E<br />
F<br />
s<br />
F<br />
G<br />
s<br />
B<br />
G<br />
H<br />
H<br />
J<br />
s<br />
S<br />
S<br />
r<br />
B<br />
B<br />
J<br />
K<br />
s<br />
S<br />
S<br />
r<br />
s<br />
B<br />
K<br />
L<br />
L<br />
J<br />
B<br />
B<br />
L<br />
M<br />
M<br />
N<br />
N<br />
P<br />
Y<br />
P<br />
D<br />
2<br />
0 1<br />
P<br />
R<br />
s<br />
s<br />
U<br />
R<br />
T<br />
B<br />
T<br />
U<br />
s<br />
U<br />
V<br />
B<br />
V<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18<br />
User I/O Pins<br />
Dedicated Pins<br />
Other Pins<br />
IO_LXXY_#<br />
C<br />
CCLK_0<br />
S<br />
VP_0<br />
GND<br />
s<br />
IO_XX_#<br />
CFGBVS_0<br />
S<br />
VN_0<br />
VCCAUX_IO_G#<br />
Multi−Function Pins<br />
D<br />
J<br />
L<br />
DONE_0<br />
DXP_0<br />
DXN_0<br />
S<br />
S<br />
VREFP_0<br />
VREFN_0<br />
VCCAUX<br />
VCCINT<br />
VCCO_#<br />
B<br />
ADV_B<br />
VRN<br />
GNDADC_0<br />
VCCBRAM<br />
B<br />
FCS_B<br />
VRP<br />
Y<br />
INIT_B_0<br />
n<br />
NC<br />
B<br />
FOE_B<br />
VREF<br />
0 M0_0<br />
B<br />
MOSI<br />
D00−D31<br />
1 M1_0<br />
B<br />
FWE_B<br />
A00−A28<br />
2 M2_0<br />
B<br />
DOUT_CSO_B<br />
DQS<br />
P<br />
PROGRAM_B_0<br />
B<br />
CSI_B<br />
MRCC<br />
K<br />
TCK_0<br />
B<br />
PUDC_B<br />
SRCC<br />
I<br />
TDI_0<br />
U<br />
RDWR_B<br />
O<br />
TDO_0<br />
r<br />
RS0−RS1<br />
M<br />
TMS_0<br />
AD0P/AD0N−AD15P/AD15N<br />
VCCADC_0<br />
EMCCLK<br />
VCCBATT_0<br />
ug475_c3_301_090711<br />
Figure 3-1:<br />
CSG324 Package—XC7A8 <strong>and</strong> XC7A15 <strong>Pinout</strong> Diagram<br />
www.BDTIC.com/XILINX<br />
52 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Artix-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-2<br />
1<br />
A 35<br />
K 35 35 34<br />
L 34<br />
34<br />
M 34 34 34 34<br />
N 34 34<br />
R 34 34 34<br />
T 34<br />
U 34 34 34 34<br />
V 34<br />
35 35 35 35<br />
B 35 35 35 35<br />
C 35 35<br />
D<br />
35 35 35 35<br />
35 35 35 35<br />
E 35 35 35<br />
F 35<br />
H 35 35<br />
35 35 35 35<br />
G 35 35 35 35<br />
J<br />
P<br />
1<br />
2<br />
35 35 35 35<br />
34 34<br />
34 34 34<br />
34 34 34<br />
34 34 34 34<br />
34 34 34<br />
34 34 34<br />
2<br />
3<br />
3<br />
4<br />
35 35<br />
34<br />
34 34 34 34<br />
34<br />
35 35<br />
35 35 35<br />
35<br />
35 35 35<br />
4<br />
5<br />
5<br />
6<br />
34 34<br />
15<br />
14 14<br />
14 14 14 14<br />
34 14 14 14<br />
34 34 34 34<br />
6<br />
7<br />
7<br />
8<br />
8<br />
9 10 11 12 13 14 15 16 17 18<br />
15 15 15 15<br />
15<br />
15 15 14 14 K<br />
14 14 14 M<br />
14 14 14 14<br />
14 14<br />
14 14 P<br />
14 14 14 14 R<br />
14 14 14 14<br />
14 14 14 14<br />
34 14 14 14<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
15 15<br />
15<br />
15 15 15 B<br />
14 14 14 14<br />
15 A<br />
15 15 15 15 E<br />
15 15 15 G<br />
15 15 15 15<br />
15 15 15<br />
15 15 D<br />
15 F<br />
15 15<br />
14 T<br />
14 14 14 U<br />
9 10 11 12 13 14 15 16 17 18<br />
ug475_c3_302_081211<br />
C<br />
H<br />
14 14 14 14 14 L<br />
J<br />
N<br />
V<br />
Figure 3-2:<br />
CSG324 Package—XC7A8 <strong>and</strong> XC7A15 I/O Banks<br />
X-Ref Target - Figure 3-3<br />
1<br />
A 35<br />
K 35 35 34<br />
L 34<br />
34<br />
M 34 34 34 34<br />
N 34 34<br />
R 34 34 34<br />
T 34<br />
U 34 34 34 34<br />
V 34<br />
35 35 35 35<br />
B 35 35 35 35<br />
C 35 35<br />
D<br />
35 35 35 35<br />
35 35 35 35<br />
E 35 35 35<br />
F 35<br />
H 35 35<br />
35 35 35 35<br />
G 35 35 35 35<br />
J<br />
P<br />
1<br />
2<br />
35 35 35 35<br />
34 34<br />
34 34 34<br />
34 34 34<br />
34 34 34 34<br />
34 34 34<br />
34 34 34<br />
2<br />
3<br />
3<br />
4<br />
35 35<br />
34<br />
34 34 34 34<br />
34<br />
35 35<br />
35 35 35<br />
35<br />
35 35 35<br />
4<br />
5<br />
5<br />
6<br />
34 34<br />
15<br />
14 14<br />
14 14 14 14<br />
34 14 14 14<br />
34 34 34 34<br />
6<br />
7<br />
7<br />
8<br />
8<br />
9 10 11 12 13 14 15 16 17 18<br />
15 15 15 15<br />
15<br />
15 15 14 14 K<br />
14 14 14 M<br />
14 14 14 14<br />
14 14<br />
14 14 P<br />
14 14 14 14 R<br />
14 14 14 14<br />
14 14 14 14<br />
34 14 14 14<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
15 15<br />
15<br />
15 15 15 B<br />
14 14 14 14<br />
15 A<br />
15 15 15 15 E<br />
15 15 15 G<br />
15 15 15 15<br />
15 15 15<br />
15 15 D<br />
15 F<br />
15 15<br />
14 T<br />
14 14 14 U<br />
9 10 11 12 13 14 15 16 17 18<br />
Memory Groupings Pins<br />
C<br />
H<br />
14 14 14 14 14 L<br />
J<br />
N<br />
V<br />
# HP I/O<br />
# HR I/O<br />
# HP I/O − VCCAUX Group 0<br />
# HP I/O − VCCAUX Group 1<br />
# HP I/O − VCCAUX Group 2<br />
# HP I/O − VCCAUX Group 3<br />
# HP I/O − VCCAUX Group 4<br />
# HP I/O − VCCAUX Group 5<br />
# HP I/O − VCCAUX Group 6<br />
# HP I/O − VCCAUX Group 7<br />
# DQS pin<br />
# DCI pin<br />
# Memory Byte Group 0<br />
# Memory Byte Group 1<br />
# Memory Byte Group 2<br />
# Memory Byte Group 3<br />
# Bank Number<br />
ug475_c3_303_081211<br />
Figure 3-3:<br />
CSG324 Package—XC7A8 <strong>and</strong> XC7A15 Memory Groupings<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 53<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-4<br />
1 2 3 4 5 6 7 8<br />
A<br />
35<br />
B<br />
C 35<br />
D<br />
35<br />
E<br />
F 35<br />
G<br />
35<br />
H<br />
J 35<br />
K<br />
34<br />
L<br />
M<br />
N 34<br />
P<br />
34<br />
R<br />
T 34<br />
U<br />
34<br />
V<br />
34<br />
1 2 3 4 5 6 7 8<br />
9<br />
0<br />
9<br />
10 11 12 13 14 15 16 17 18<br />
15 A<br />
16<br />
B<br />
15<br />
C<br />
15 D<br />
E<br />
F<br />
15<br />
G<br />
15 H<br />
J<br />
15<br />
K<br />
14 L<br />
M<br />
14<br />
N<br />
14 P<br />
R<br />
14<br />
T<br />
14<br />
U<br />
14 V<br />
10 11 12 13 14 15 16 17 18<br />
Power Pins<br />
# VCCO_#<br />
VCCINT<br />
VCCAUX<br />
# VCCAUX_IO_G#<br />
VCCBRAM<br />
VCCBATT_0<br />
VCCADC_0<br />
GNDADC_0<br />
GND<br />
ug475_c3_304_090711<br />
Figure 3-4:<br />
CSG324 Package—XC7A8 <strong>and</strong> XC7A15 Power <strong>and</strong> GND Placement<br />
www.BDTIC.com/XILINX<br />
54 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Artix-7 <strong>FPGAs</strong> Device Diagrams<br />
CSG324 Package—XC7A30T, XC7A50T, <strong>and</strong> XC7A100T<br />
X-Ref Target - Figure 3-5<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18<br />
A<br />
A<br />
B<br />
B<br />
C<br />
C<br />
D<br />
D<br />
E<br />
C<br />
K<br />
I<br />
M<br />
O<br />
E<br />
F<br />
s<br />
F<br />
G<br />
s<br />
B<br />
G<br />
H<br />
H<br />
J<br />
s<br />
S<br />
S<br />
r<br />
B<br />
B<br />
J<br />
K<br />
s<br />
S<br />
S<br />
r<br />
s<br />
B<br />
K<br />
L<br />
L<br />
J<br />
B<br />
B<br />
L<br />
M<br />
M<br />
N<br />
N<br />
P<br />
Y<br />
P<br />
D<br />
2<br />
0 1<br />
P<br />
R<br />
s<br />
s<br />
U<br />
R<br />
T<br />
B<br />
T<br />
U<br />
s<br />
U<br />
V<br />
B<br />
V<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18<br />
User I/O Pins<br />
Dedicated Pins<br />
Other Pins<br />
IO_LXXY_#<br />
C<br />
CCLK_0<br />
S<br />
VP_0<br />
GND<br />
s<br />
IO_XX_#<br />
CFGBVS_0<br />
S<br />
VN_0<br />
VCCAUX_IO_G#<br />
Multi−Function Pins<br />
D<br />
J<br />
L<br />
DONE_0<br />
DXP_0<br />
DXN_0<br />
S<br />
S<br />
VREFP_0<br />
VREFN_0<br />
VCCAUX<br />
VCCINT<br />
VCCO_#<br />
B<br />
ADV_B<br />
VRN<br />
GNDADC_0<br />
VCCBRAM<br />
B<br />
FCS_B<br />
VRP<br />
Y<br />
INIT_B_0<br />
n<br />
NC<br />
B<br />
FOE_B<br />
VREF<br />
0 M0_0<br />
B<br />
MOSI<br />
D00−D31<br />
1 M1_0<br />
B<br />
FWE_B<br />
A00−A28<br />
2 M2_0<br />
B<br />
DOUT_CSO_B<br />
DQS<br />
P<br />
PROGRAM_B_0<br />
B<br />
CSI_B<br />
MRCC<br />
K<br />
TCK_0<br />
B<br />
PUDC_B<br />
SRCC<br />
I<br />
TDI_0<br />
U<br />
RDWR_B<br />
O<br />
TDO_0<br />
r<br />
RS0−RS1<br />
M<br />
TMS_0<br />
AD0P/AD0N−AD15P/AD15N<br />
VCCADC_0<br />
EMCCLK<br />
VCCBATT_0<br />
ug475_c3_305_090711<br />
Figure 3-5:<br />
CSG324 Package—XC7A30T, XC7A50T, <strong>and</strong> XC7A100T <strong>Pinout</strong> Diagram<br />
X-Ref Target - Figure 3-6<br />
A 35<br />
K 35 35 34<br />
L 34<br />
34<br />
M 34 34 34 34<br />
N 34 34<br />
R 34 34 34<br />
T 34<br />
U 34 34 34 34<br />
V 34<br />
35 35 35 35<br />
B 35 35 35 35<br />
C 35 35<br />
D<br />
35 35 35 35<br />
16 16 16 15<br />
35 35 16 16<br />
35 35 35 35<br />
35 35 35 35<br />
E 35 35 35<br />
F 35<br />
G 35 35 35 35<br />
H 35 35<br />
J<br />
P<br />
1<br />
1<br />
2<br />
35 35 35 35<br />
34 34<br />
34 34 34<br />
34 34 34<br />
34 34 34 34<br />
34 34 34<br />
34 34 34<br />
2<br />
3<br />
3<br />
4<br />
35 35 35<br />
35<br />
35 35 35<br />
4<br />
5<br />
34<br />
14 14<br />
14 14 14 14<br />
34 14 14 14<br />
15 15 15 15<br />
16 16 16 15<br />
35 35 16 16<br />
34 34 34 34<br />
5<br />
6<br />
34<br />
34 34 34 34<br />
34 34<br />
6<br />
7<br />
7<br />
8<br />
8<br />
9 10 11 12 13 14 15 16 17 18<br />
15 15 14 14 K<br />
14 14 14 M<br />
14 14 14 14<br />
14 14<br />
14 14 P<br />
14 14 14 14 R<br />
14 14 14 14<br />
14 14 14 14<br />
34 14 14 14<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
15 15<br />
15<br />
15 15 15 B<br />
14 14 14 14<br />
15 A<br />
15 15 15 15 E<br />
15 15 15 G<br />
15 15 15 15<br />
15 15 15<br />
15 15 D<br />
15 F<br />
15 15<br />
14 T<br />
14 14 14 U<br />
9 10 11 12 13 14 15 16 17 18<br />
C<br />
H<br />
14 14 14 14 14 L<br />
J<br />
N<br />
V<br />
ug475_c3_306_081211<br />
Figure 3-6:<br />
CSG324 Package—XC7A30T, XC7A50T, <strong>and</strong> XC7A100T I/O Banks<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 55<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-7<br />
1<br />
A 35<br />
K 35 35 34<br />
L 34<br />
34<br />
M 34 34 34 34<br />
N 34 34<br />
R 34 34 34<br />
T 34<br />
U 34 34 34 34<br />
V 34<br />
35 35 35 35<br />
B 35 35 35 35<br />
C 35 35<br />
D<br />
35 35 35 35<br />
16 16 16 15<br />
35 35 16 16<br />
35 35 35 35<br />
35 35 35 35<br />
E 35 35 35<br />
F 35<br />
G 35 35 35 35<br />
H 35 35<br />
J<br />
P<br />
1<br />
2<br />
35 35 35 35<br />
34 34<br />
34 34 34<br />
34 34 34<br />
34 34 34 34<br />
34 34 34<br />
34 34 34<br />
2<br />
3<br />
3<br />
4<br />
35 35 35<br />
35<br />
35 35 35<br />
4<br />
5<br />
34<br />
14 14<br />
14 14 14 14<br />
34 14 14 14<br />
15 15 15 15<br />
16 16 16 15<br />
35 35 16 16<br />
34 34 34 34<br />
5<br />
6<br />
34<br />
34 34 34 34<br />
34 34<br />
6<br />
7<br />
7<br />
8<br />
8<br />
9 10 11 12 13 14 15 16 17 18<br />
15 15 14 14 K<br />
14 14 14 M<br />
14 14 14 14<br />
14 14<br />
14 14 P<br />
14 14 14 14 R<br />
14 14 14 14<br />
14 14 14 14<br />
34 14 14 14<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
15 15<br />
15<br />
15 15 15 B<br />
14 14 14 14<br />
15 A<br />
15 15 15 15 E<br />
15 15 15 G<br />
15 15 15 15<br />
15 15 15<br />
15 15 D<br />
15 F<br />
15 15<br />
14 T<br />
14 14 14 U<br />
9 10 11 12 13 14 15 16 17 18<br />
Memory Groupings Pins<br />
C<br />
H<br />
14 14 14 14 14 L<br />
J<br />
N<br />
V<br />
# HP I/O<br />
# HR I/O<br />
# HP I/O − VCCAUX Group 0<br />
# HP I/O − VCCAUX Group 1<br />
# HP I/O − VCCAUX Group 2<br />
# HP I/O − VCCAUX Group 3<br />
# HP I/O − VCCAUX Group 4<br />
# HP I/O − VCCAUX Group 5<br />
# HP I/O − VCCAUX Group 6<br />
# HP I/O − VCCAUX Group 7<br />
# DQS pin<br />
# DCI pin<br />
# Memory Byte Group 0<br />
# Memory Byte Group 1<br />
# Memory Byte Group 2<br />
# Memory Byte Group 3<br />
# Bank Number<br />
ug475_c3_307_081211<br />
Figure 3-7:<br />
CSG324 Package—XC7A30T, XC7A50T, <strong>and</strong> XC7A100T Memory Groupings<br />
X-Ref Target - Figure 3-8<br />
1 2 3 4 5 6 7 8<br />
A<br />
35<br />
B<br />
C 35<br />
D<br />
35<br />
E<br />
F 35<br />
G<br />
35<br />
H<br />
J 35<br />
K<br />
34<br />
L<br />
M<br />
N 34<br />
P<br />
34<br />
R<br />
T 34<br />
U<br />
34<br />
V<br />
34<br />
1 2 3 4 5 6 7 8<br />
9<br />
0<br />
9<br />
10 11 12 13 14 15 16 17 18<br />
15 A<br />
16<br />
B<br />
15<br />
C<br />
15 D<br />
E<br />
F<br />
15<br />
G<br />
15 H<br />
J<br />
15<br />
K<br />
14 L<br />
M<br />
14<br />
N<br />
14 P<br />
R<br />
14<br />
T<br />
14<br />
U<br />
14 V<br />
10 11 12 13 14 15 16 17 18<br />
Power Pins<br />
# VCCO_#<br />
VCCINT<br />
VCCAUX<br />
# VCCAUX_IO_G#<br />
VCCBRAM<br />
VCCBATT_0<br />
VCCADC_0<br />
GNDADC_0<br />
GND<br />
ug475_c3_308_090711<br />
Figure 3-8:<br />
CSG324 Package—XC7A30T, XC7A50T, <strong>and</strong> XC7A100T Power <strong>and</strong> GND Placement<br />
www.BDTIC.com/XILINX<br />
56 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Kintex-7 <strong>FPGAs</strong> Device Diagrams<br />
Kintex-7 <strong>FPGAs</strong> Device Diagrams<br />
Table 3-2: Kintex-7 <strong>FPGAs</strong> Device Diagrams Cross-Reference<br />
Device FB(G)484 FB(G)676 FB(G)900 FF(G)676 FF(G)900 FF(G)901 FF(G)1156<br />
XC7K70T page 57 page 60<br />
XC7K160T page 57 page 63 page 70<br />
XC7K325T page 63 page 66 page 70 page 73<br />
XC7K355T page 77<br />
XC7K410T page 63 page 66 page 70 page 73<br />
XC7K420T page 81 page 89<br />
XC7K480T page 85 page 93<br />
FBG484 Package—XC7K70T <strong>and</strong> XC7K160T<br />
X-Ref Target - Figure 3-9<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22<br />
A<br />
V<br />
E<br />
A<br />
B<br />
r<br />
r<br />
B<br />
C<br />
V<br />
E<br />
C<br />
D<br />
s<br />
B<br />
B<br />
D<br />
E<br />
V<br />
E<br />
s<br />
E<br />
F<br />
F<br />
G<br />
V<br />
E<br />
C<br />
B<br />
G<br />
H<br />
V<br />
G<br />
1<br />
0<br />
s<br />
s<br />
B<br />
H<br />
J<br />
V<br />
2<br />
O<br />
J<br />
K<br />
I<br />
K<br />
s<br />
B<br />
B<br />
K<br />
L<br />
M<br />
Y<br />
S<br />
S<br />
B<br />
L<br />
M<br />
P<br />
S<br />
S<br />
s<br />
B<br />
M<br />
N<br />
L<br />
J<br />
U<br />
N<br />
P<br />
D<br />
P<br />
R<br />
R<br />
T<br />
s<br />
T<br />
U<br />
U<br />
V<br />
s<br />
V<br />
W<br />
W<br />
Y<br />
Y<br />
AA<br />
AA<br />
AB<br />
AB<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22<br />
User I/O Pins<br />
Transceiver Pins<br />
Dedicated Pins<br />
Other Pins<br />
IO_LXXY_#<br />
E<br />
MGTAVCC_G#<br />
C<br />
CCLK_0<br />
S<br />
VP_0<br />
GND<br />
s<br />
IO_XX_#<br />
V<br />
MGTAVTT_G#<br />
CFGBVS_0<br />
S<br />
VN_0<br />
VCCAUX_IO_G#<br />
Multi−Function Pins<br />
V<br />
V<br />
MGTVCCAUX_G#<br />
MGTAVTTRCAL<br />
G MGTRREF<br />
D<br />
J<br />
L<br />
DONE_0<br />
DXP_0<br />
DXN_0<br />
S<br />
S<br />
VREFP_0<br />
VREFN_0<br />
VCCAUX<br />
VCCINT<br />
VCCO_#<br />
B<br />
ADV_B<br />
VRN<br />
MGTREFCLK1/0P<br />
GNDADC_0<br />
VCCBRAM<br />
B<br />
FCS_B<br />
VRP<br />
MGTREFCLK1/0N<br />
Y<br />
INIT_B_0<br />
n<br />
NC<br />
B<br />
FOE_B<br />
VREF<br />
MGTXRXP<br />
0 M0_0<br />
B<br />
MOSI<br />
D00−D31<br />
MGTXRXN<br />
1 M1_0<br />
B<br />
FWE_B<br />
A00−A28<br />
MGTXTXP<br />
2 M2_0<br />
B<br />
DOUT_CSO_B<br />
DQS<br />
MGTXTXN<br />
P<br />
PROGRAM_B_0<br />
B<br />
CSI_B<br />
MRCC<br />
E<br />
MGTHAVCC_G#<br />
K<br />
TCK_0<br />
B<br />
PUDC_B<br />
SRCC<br />
V<br />
MGTHAVTT_G#<br />
I<br />
TDI_0<br />
U<br />
RDWR_B<br />
MGTHRXP<br />
O<br />
TDO_0<br />
r<br />
RS0−RS1<br />
MGTHRXN<br />
M<br />
TMS_0<br />
AD0P/AD0N−AD15P/AD15N<br />
MGTHTXP<br />
VCCADC_0<br />
EMCCLK<br />
MGTHTXN<br />
VCCBATT_0<br />
ug475_c3_13_090511<br />
Figure 3-9:<br />
FBG484 Package—XC7K70T <strong>and</strong> XC7K160T <strong>Pinout</strong> Diagram<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 57<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-10<br />
A<br />
1<br />
B 115 115<br />
C<br />
D 115 115<br />
E<br />
F 115 115<br />
G<br />
H 115 115<br />
J<br />
K 34 34 34 34<br />
L 34<br />
M 34 34 34<br />
N<br />
P 34 34<br />
34 34 34<br />
34 34 34 34<br />
R 34 34 34 34<br />
T 34<br />
U 34 34 34<br />
V<br />
W 34 34<br />
Y<br />
AA 34<br />
34<br />
34 34<br />
33 33<br />
34 34 34 33<br />
34 34 34 34<br />
34 34 34<br />
115 115<br />
115 115<br />
115 115<br />
115 115<br />
AB 34 34 34<br />
1<br />
2<br />
2<br />
3<br />
34 34 33 33<br />
34<br />
115 115<br />
115 115<br />
115 115<br />
34 34 33 33<br />
3<br />
4<br />
4<br />
5<br />
16 16 16 16<br />
16<br />
16 16 16<br />
16 16 15 15<br />
16 16 16 15<br />
16 16<br />
16 16 16 16<br />
16<br />
34 33 33 33<br />
33 33 33 33<br />
5<br />
6<br />
16 16 16<br />
33 33 33 33<br />
33 33 33 33<br />
6<br />
7<br />
7<br />
8<br />
15 15 15 15<br />
15 15 15 15<br />
16 16 16 15<br />
16 16 16 16<br />
33 33 33 33<br />
33 33 33 33<br />
33 33 33 33<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22<br />
16 16 15 15<br />
33 33 13 13<br />
33 33 13 13<br />
33 33 33 13<br />
15 15 15 15<br />
15 15 15 15<br />
16 16 16 15<br />
33 33 33 33<br />
33 33 33 33<br />
15 15 15 14<br />
13 13 13 13<br />
13 13 13 13<br />
33 13 13 13<br />
15 14 14 14<br />
14 14 14 14<br />
14<br />
14 14 14<br />
13 14 14 14<br />
13 13 13 13<br />
13 13 13 13<br />
13 13 13 13<br />
13 13 13 13<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
15 15<br />
15 15 15 15 D<br />
15 14 14 14<br />
14 14 14 G<br />
14 14 14 14<br />
14 14 14 14<br />
15 15 15 B<br />
13 13 13 U<br />
13 V<br />
13 13 13 13 W<br />
13 13 13 13<br />
15 C<br />
14 14 E<br />
14 H<br />
14 14 K<br />
14 14 14 M<br />
14 N<br />
14 14 14 14 14 14 P<br />
14 14 R<br />
13 13 Y<br />
13 13 13 AB<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22<br />
A<br />
F<br />
14 14 14 14 J<br />
L<br />
T<br />
AA<br />
ug475_c3_14_011111<br />
Figure 3-10:<br />
FBG484 Package—XC7K70T <strong>and</strong> XC7K160T I/O Banks<br />
X-Ref Target - Figure 3-11<br />
A<br />
B<br />
C<br />
D<br />
E<br />
F<br />
G<br />
H<br />
J<br />
K 34 34 34 34<br />
L 34<br />
M 34 34 34<br />
N<br />
P 34 34<br />
34 34 34<br />
34 34 34 34<br />
R 34 34 34 34<br />
T 34<br />
U 34 34 34<br />
V<br />
W 34 34<br />
Y<br />
1<br />
AA 34<br />
34<br />
34 34<br />
33 33<br />
34 34 34 33<br />
34 34 34 34<br />
34 34 34<br />
AB 34 34 34<br />
1<br />
2<br />
2<br />
3<br />
34 34 33 33<br />
34<br />
34 34 33 33<br />
3<br />
4<br />
4<br />
5<br />
16 16 16 16<br />
16<br />
16 16 16<br />
16 16 15 15<br />
16 16 16 15<br />
16 16<br />
16 16 16 16<br />
16<br />
34 33 33 33<br />
33 33 33 33<br />
5<br />
6<br />
16 16 16<br />
33 33 33 33<br />
33 33 33 33<br />
6<br />
7<br />
7<br />
8<br />
15 15 15 15<br />
15 15 15 15<br />
16 16 16 15<br />
16 16 16 16<br />
33 33 33 33<br />
33 33 33 33<br />
33 33 33 33<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22<br />
16 16 15 15<br />
33 33 13 13<br />
33 33 13 13<br />
33 33 33 13<br />
15 15 15 15<br />
15 15 15 15<br />
16 16 16 15<br />
33 33 33 33<br />
33 33 33 33<br />
15 15 15 14<br />
13 13 13 13<br />
13 13 13 13<br />
33 13 13 13<br />
15 14 14 14<br />
14 14 14 14<br />
14<br />
14 14 14<br />
13 14 14 14<br />
13 13 13 13<br />
13 13 13 13<br />
13 13 13 13<br />
13 13 13 13<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
15 15<br />
15 15 15 15 D<br />
15 14 14 14<br />
14 14 14 G<br />
14 14 14 14<br />
14 14 14 14<br />
15 15 15 B<br />
13 13 13 U<br />
13 V<br />
13 13 13 13 W<br />
13 13 13 13<br />
15 C<br />
14 14 E<br />
14 H<br />
14 14 K<br />
14 14 14 M<br />
14 N<br />
14 14 14 14 14 14 P<br />
14 14 R<br />
13 13 Y<br />
13 13 13 AB<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22<br />
Memory Groupings Pins<br />
A<br />
F<br />
14 14 14 14 J<br />
L<br />
T<br />
AA<br />
# HP I/O<br />
# HR I/O<br />
# HP I/O − VCCAUX Group 0<br />
# HP I/O − VCCAUX Group 1<br />
# HP I/O − VCCAUX Group 2<br />
# HP I/O − VCCAUX Group 3<br />
# HP I/O − VCCAUX Group 4<br />
# HP I/O − VCCAUX Group 5<br />
# HP I/O − VCCAUX Group 6<br />
# HP I/O − VCCAUX Group 7<br />
# DQS pin<br />
# DCI pin<br />
# Memory Byte Group 0<br />
# Memory Byte Group 1<br />
# Memory Byte Group 2<br />
# Memory Byte Group 3<br />
# Bank Number<br />
ug475_c3_15_052311<br />
Figure 3-11:<br />
FBG484 Package—XC7K70T <strong>and</strong> XC7K160T Memory Groupings<br />
www.BDTIC.com/XILINX<br />
58 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Kintex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-12<br />
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22<br />
A<br />
15<br />
A<br />
B<br />
15<br />
B<br />
C<br />
16<br />
15 C<br />
D<br />
16<br />
15<br />
D<br />
E<br />
15<br />
E<br />
F<br />
16<br />
14 F<br />
G<br />
16<br />
14<br />
G<br />
H<br />
15<br />
H<br />
J<br />
0<br />
J<br />
K<br />
14 K<br />
L<br />
14<br />
L<br />
M<br />
34<br />
M<br />
N 34<br />
0<br />
14 N<br />
P<br />
14<br />
P<br />
R<br />
34<br />
R<br />
T 34<br />
33<br />
13 T<br />
U<br />
33<br />
13<br />
U<br />
V<br />
33<br />
13<br />
V<br />
W 34<br />
33<br />
W<br />
Y<br />
33<br />
13 Y<br />
AA<br />
33<br />
13<br />
AA<br />
AB<br />
34<br />
13<br />
AB<br />
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22<br />
Power Pins<br />
# VCCO_#<br />
VCCINT<br />
VCCAUX<br />
# VCCAUX_IO_G#<br />
VCCBRAM<br />
VCCBATT_0<br />
VCCADC_0<br />
GNDADC_0<br />
MGTVCCAUX<br />
# MGTVCCAUX_G# or MGTHVCCAUX_G#<br />
MGTAVCC<br />
# MGTAVCC_G# or MGTHAVCC_G#<br />
MGTAVTT<br />
# MGTAVTT_G# or MGTHAVTT_G#<br />
GND<br />
ug475_c3_16_052311<br />
Figure 3-12:<br />
FBG484 Package—XC7K70T <strong>and</strong> XC7K160T Power <strong>and</strong> GND Placement<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 59<br />
<strong>UG475</strong> (v1.4) October 17, 2011
60 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011<br />
Chapter 3: Device Diagrams<br />
FBG676 Package—XC7K70T<br />
X-Ref Target - Figure 3-13<br />
Figure 3-13:<br />
FBG676 Package—XC7K70T <strong>Pinout</strong> Diagram<br />
User I/O Pins<br />
IO_LXXY_#<br />
s<br />
IO_XX_#<br />
Multi−Function Pins<br />
B<br />
ADV_B<br />
B<br />
FCS_B<br />
B<br />
FOE_B<br />
B<br />
MOSI<br />
B<br />
FWE_B<br />
B<br />
DOUT_CSO_B<br />
B<br />
CSI_B<br />
B<br />
PUDC_B<br />
U<br />
RDWR_B<br />
r<br />
RS0−RS1<br />
AD0P/AD0N−AD15P/AD15N<br />
EMCCLK<br />
VRN<br />
VRP<br />
VREF<br />
D00−D31<br />
A00−A28<br />
DQS<br />
MRCC<br />
SRCC<br />
Transceiver Pins<br />
E<br />
MGTAVCC_G#<br />
V<br />
MGTAVTT_G#<br />
V<br />
MGTVCCAUX_G#<br />
V<br />
MGTAVTTRCAL<br />
G<br />
MGTRREF<br />
MGTREFCLK1/0P<br />
MGTREFCLK1/0N<br />
MGTXRXP<br />
MGTXRXN<br />
MGTXTXP<br />
MGTXTXN<br />
E<br />
MGTHAVCC_G#<br />
V<br />
MGTHAVTT_G#<br />
MGTHRXP<br />
MGTHRXN<br />
MGTHTXP<br />
MGTHTXN<br />
Dedicated Pins<br />
C<br />
CCLK_0<br />
CFGBVS_0<br />
D<br />
DONE_0<br />
J<br />
DXP_0<br />
L<br />
DXN_0<br />
GNDADC_0<br />
Y<br />
INIT_B_0<br />
0 M0_0<br />
1 M1_0<br />
2 M2_0<br />
P<br />
PROGRAM_B_0<br />
K<br />
TCK_0<br />
I<br />
TDI_0<br />
O<br />
TDO_0<br />
M<br />
TMS_0<br />
VCCADC_0<br />
VCCBATT_0<br />
S<br />
VP_0<br />
S<br />
VN_0<br />
S<br />
VREFP_0<br />
S<br />
VREFN_0<br />
Other Pins<br />
GND<br />
VCCAUX_IO_G#<br />
VCCAUX<br />
VCCINT<br />
VCCO_#<br />
VCCBRAM<br />
n<br />
NC<br />
ug475_c3_05_090511<br />
L<br />
J<br />
S<br />
S<br />
S<br />
S<br />
C<br />
K<br />
M<br />
O<br />
I<br />
Y<br />
P<br />
D<br />
2<br />
0<br />
1<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
s<br />
s<br />
s<br />
B<br />
B<br />
B<br />
U<br />
B<br />
B<br />
s<br />
s<br />
B<br />
B<br />
B<br />
r<br />
r<br />
s<br />
s<br />
s<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
V<br />
G<br />
E<br />
E<br />
E<br />
E<br />
E<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
1<br />
1<br />
2<br />
2<br />
3<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
6<br />
7<br />
7<br />
8<br />
8<br />
9<br />
9<br />
10<br />
10<br />
11<br />
11<br />
12<br />
12<br />
13<br />
13<br />
14<br />
14<br />
15<br />
15<br />
16<br />
16<br />
17<br />
17<br />
18<br />
18<br />
19<br />
19<br />
20<br />
20<br />
21<br />
21<br />
22<br />
22<br />
23<br />
23<br />
24<br />
24<br />
25<br />
25<br />
26<br />
26<br />
A<br />
A<br />
B<br />
B<br />
C<br />
C<br />
D<br />
D<br />
E<br />
E<br />
F<br />
F<br />
G<br />
G<br />
H<br />
H<br />
J<br />
J<br />
K<br />
K<br />
L<br />
L<br />
M<br />
M<br />
N<br />
N<br />
P<br />
P<br />
R<br />
R<br />
T<br />
T<br />
U<br />
U<br />
V<br />
V<br />
W<br />
W<br />
Y<br />
Y<br />
AA<br />
AA<br />
AB<br />
AB<br />
AC<br />
AC<br />
AD<br />
AD<br />
AE<br />
AE<br />
AF<br />
AF<br />
www.BDTIC.com/XILINX
Kintex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-14<br />
A<br />
1<br />
B 116 116<br />
C<br />
D 116 116<br />
E<br />
F 116 116<br />
G<br />
H 115 115<br />
J<br />
K 115 115<br />
L<br />
M 115 115<br />
N<br />
P 115 115<br />
R<br />
T<br />
U 34 34<br />
V 34 34 34 34<br />
W 34<br />
Y 34 34 34<br />
AA<br />
AB 34 34<br />
34 34 34<br />
34 34 34 34<br />
34 34 34<br />
AC 34 34 34 34<br />
AD 34<br />
AE 34<br />
AF<br />
1<br />
2<br />
116 116<br />
116 116<br />
116 116<br />
116 116<br />
115 115<br />
115 115<br />
115 115<br />
115 115<br />
116 116<br />
116 116<br />
116 116<br />
115 115<br />
115 115<br />
115 115<br />
34<br />
34<br />
16 16 16<br />
16 16 16 16<br />
16 16 16<br />
16 16<br />
16<br />
16 16<br />
16<br />
16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
33<br />
34 33 33 33<br />
34 34<br />
34 34 34 33<br />
34 34 34 34<br />
34 34 34 34<br />
34 34 34 34<br />
2<br />
3<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
34<br />
16 15 15<br />
16 16 15 15<br />
16 16 16 15<br />
16 16 16 16<br />
16 16<br />
16 16 16 16<br />
33 33<br />
33 33 33 33<br />
33 33 33 33<br />
33 33 33 33<br />
34 33 33 33<br />
6<br />
7<br />
33 33 33 33<br />
33 33<br />
33 33 33 33<br />
33 33 33 33<br />
7<br />
8<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26<br />
33 33 33<br />
13 13 13 13<br />
13<br />
15 15 15 14<br />
15 15 15 15<br />
15 15 15 15<br />
16 15 15 15<br />
16 16 15 15<br />
33 33<br />
33 33<br />
33<br />
33 33 33 33<br />
33 33<br />
15 15 15 15<br />
13 13 13<br />
14 14 13 13<br />
13 13 K<br />
13 13 13 13 13 13 13 M<br />
13 13 13 13<br />
13 13 13 13<br />
13 13<br />
15 14 14 14<br />
15 15 15 14<br />
15 15 15 15<br />
15 15 15 15<br />
15 14 14 14<br />
13 13 13 13 13 N<br />
13 13 13 13<br />
13 13<br />
14 14 14 14<br />
14 14 14 14<br />
15 14 14 14<br />
15 15 14 14<br />
15 15 15 14<br />
15 15 15 15<br />
15 15<br />
14 14 14 B<br />
14 14 14 14 D<br />
14 14 14 14<br />
14 14 14 14<br />
13 13 13 13 P<br />
13 13 13 13<br />
14 C<br />
14 14 E<br />
14 14 14 G<br />
14 H<br />
13 13 R<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26<br />
ug475_c3_06_032911<br />
A<br />
F<br />
14 14 14 14 J<br />
L<br />
T<br />
U<br />
V<br />
W<br />
Y<br />
AA<br />
AB<br />
AC<br />
AD<br />
AE<br />
AF<br />
Figure 3-14:<br />
FBG676 Package—XC7K70T I/O Banks<br />
X-Ref Target - Figure 3-15<br />
A<br />
B<br />
C<br />
D<br />
E<br />
F<br />
G<br />
H<br />
J<br />
K<br />
L<br />
M<br />
N<br />
P<br />
R<br />
T<br />
U 34 34<br />
V 34 34 34 34<br />
W 34<br />
Y 34 34 34<br />
AA<br />
AB 34 34<br />
34 34 34<br />
34 34 34 34<br />
34 34 34<br />
AC 34 34 34 34<br />
AD 34<br />
AE 34<br />
AF<br />
1<br />
1<br />
2<br />
34<br />
34<br />
16 16 16<br />
16 16 16 16<br />
16 16 16<br />
16 16<br />
16<br />
16 16<br />
16<br />
16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
33<br />
34 33 33 33<br />
34 34<br />
34 34 34 33<br />
34 34 34 34<br />
34 34 34 34<br />
34 34 34 34<br />
2<br />
3<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
34<br />
16 15 15<br />
16 16 15 15<br />
16 16 16 15<br />
16 16 16 16<br />
16 16<br />
16 16 16 16<br />
33 33<br />
33 33 33 33<br />
33 33 33 33<br />
33 33 33 33<br />
34 33 33 33<br />
6<br />
7<br />
33 33 33 33<br />
33 33<br />
33 33 33 33<br />
33 33 33 33<br />
7<br />
8<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26<br />
33 33 33<br />
13 13 13 13<br />
13<br />
15 15 15 14<br />
15 15 15 15<br />
15 15 15 15<br />
16 15 15 15<br />
16 16 15 15<br />
33 33<br />
33 33<br />
33<br />
33 33 33 33<br />
33 33<br />
15 15 15 15<br />
13 13 13<br />
14 14 13 13<br />
13 13 K<br />
13 13 13 13 13 13 13 M<br />
13 13 13 13<br />
13 13 13 13<br />
13 13<br />
15 14 14 14<br />
15 15 15 14<br />
15 15 15 15<br />
15 15 15 15<br />
15 14 14 14<br />
13 13 13 13 13 N<br />
13 13 13 13<br />
13 13<br />
14 14 14 14<br />
14 14 14 14<br />
15 14 14 14<br />
15 15 14 14<br />
15 15 15 14<br />
15 15 15 15<br />
15 15<br />
14 14 14 B<br />
14 14 14 14 D<br />
14 14 14 14<br />
14 14 14 14<br />
13 13 13 13 P<br />
13 13 13 13<br />
14 C<br />
14 14 E<br />
14 14 14 G<br />
14 H<br />
13 13 R<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26<br />
Memory Groupings Pins<br />
A<br />
F<br />
14 14 14 14 J<br />
L<br />
T<br />
U<br />
V<br />
W<br />
Y<br />
AA<br />
AB<br />
AC<br />
AD<br />
AE<br />
AF<br />
# HP I/O<br />
# HR I/O<br />
# HP I/O − VCCAUX Group 0<br />
# HP I/O − VCCAUX Group 1<br />
# HP I/O − VCCAUX Group 2<br />
# HP I/O − VCCAUX Group 3<br />
# HP I/O − VCCAUX Group 4<br />
# HP I/O − VCCAUX Group 5<br />
# HP I/O − VCCAUX Group 6<br />
# HP I/O − VCCAUX Group 7<br />
# DQS pin<br />
# DCI pin<br />
# Memory Byte Group 0<br />
# Memory Byte Group 1<br />
# Memory Byte Group 2<br />
# Memory Byte Group 3<br />
# Bank Number<br />
ug475_c3_07_052311<br />
Figure 3-15:<br />
FBG676 Package—XC7K70T Memory Groupings<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 61<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-16<br />
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26<br />
A<br />
16<br />
14<br />
A<br />
B<br />
16<br />
15<br />
B<br />
C<br />
16<br />
14 C<br />
D<br />
16<br />
14<br />
D<br />
E<br />
16<br />
15<br />
E<br />
F<br />
15<br />
14 F<br />
G<br />
16<br />
14<br />
G<br />
H<br />
16<br />
15<br />
H<br />
J<br />
15<br />
J<br />
K<br />
13 K<br />
L<br />
0<br />
14<br />
L<br />
M<br />
15<br />
M<br />
N<br />
13 N<br />
P<br />
0<br />
13<br />
P<br />
R<br />
0<br />
13<br />
R<br />
T<br />
0 0<br />
13 13 T<br />
U 34<br />
12<br />
U<br />
V<br />
33<br />
12<br />
V<br />
W<br />
33<br />
32<br />
W<br />
Y<br />
34<br />
32<br />
12 Y<br />
AA 34<br />
33<br />
12<br />
AA<br />
AB<br />
33<br />
32<br />
AB<br />
AC<br />
34<br />
32<br />
12 AC<br />
AD 34<br />
33<br />
12<br />
AD<br />
AE<br />
33<br />
32<br />
AE<br />
AF<br />
34<br />
32<br />
12 AF<br />
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26<br />
Power Pins<br />
# VCCO_#<br />
VCCINT<br />
VCCAUX<br />
# VCCAUX_IO_G#<br />
VCCBRAM<br />
VCCBATT_0<br />
VCCADC_0<br />
GNDADC_0<br />
MGTVCCAUX<br />
# MGTVCCAUX_G# or MGTHVCCAUX_G#<br />
MGTAVCC<br />
# MGTAVCC_G# or MGTHAVCC_G#<br />
MGTAVTT<br />
# MGTAVTT_G# or MGTHAVTT_G#<br />
GND<br />
ug475_c3_08_052311<br />
Figure 3-16:<br />
FBG676 Package—XC7K70T Power <strong>and</strong> GND Placement<br />
www.BDTIC.com/XILINX<br />
62 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Kintex-7 <strong>FPGAs</strong> Device Diagrams<br />
FBG676 Package—XC7K160T, XC7K325T, <strong>and</strong> XC7K410T<br />
X-Ref Target - Figure 3-17<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26<br />
A<br />
A<br />
B<br />
V<br />
B<br />
B<br />
B<br />
C<br />
V<br />
E<br />
C<br />
B<br />
C<br />
D<br />
V<br />
B<br />
B<br />
D<br />
E<br />
E<br />
U<br />
E<br />
F<br />
F<br />
G<br />
V<br />
E<br />
Y<br />
B<br />
G<br />
H<br />
V<br />
H<br />
J<br />
E<br />
D<br />
s<br />
s<br />
J<br />
K<br />
s<br />
r<br />
s<br />
K<br />
L<br />
V<br />
E<br />
K<br />
r<br />
B<br />
s<br />
L<br />
M<br />
V<br />
V<br />
G<br />
s<br />
B<br />
M<br />
N<br />
V<br />
M<br />
S<br />
S<br />
s<br />
N<br />
P<br />
2<br />
P<br />
S<br />
S<br />
P<br />
R<br />
I<br />
O<br />
L<br />
J<br />
R<br />
T<br />
1<br />
0<br />
T<br />
U<br />
s<br />
s<br />
U<br />
V<br />
V<br />
W<br />
W<br />
Y<br />
s<br />
Y<br />
AA<br />
AA<br />
AB<br />
AB<br />
AC<br />
AC<br />
AD<br />
AD<br />
AE<br />
AE<br />
AF<br />
AF<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26<br />
User I/O Pins<br />
Transceiver Pins<br />
Dedicated Pins<br />
Other Pins<br />
IO_LXXY_#<br />
E<br />
MGTAVCC_G#<br />
C<br />
CCLK_0<br />
S<br />
VP_0<br />
GND<br />
s<br />
IO_XX_#<br />
V<br />
MGTAVTT_G#<br />
CFGBVS_0<br />
S<br />
VN_0<br />
VCCAUX_IO_G#<br />
Multi−Function Pins<br />
V<br />
V<br />
MGTVCCAUX_G#<br />
MGTAVTTRCAL<br />
G MGTRREF<br />
D<br />
J<br />
L<br />
DONE_0<br />
DXP_0<br />
DXN_0<br />
S<br />
S<br />
VREFP_0<br />
VREFN_0<br />
VCCAUX<br />
VCCINT<br />
VCCO_#<br />
B<br />
ADV_B<br />
VRN<br />
MGTREFCLK1/0P<br />
GNDADC_0<br />
VCCBRAM<br />
B<br />
FCS_B<br />
VRP<br />
MGTREFCLK1/0N<br />
Y<br />
INIT_B_0<br />
n<br />
NC<br />
B<br />
FOE_B<br />
VREF<br />
MGTXRXP<br />
0 M0_0<br />
B<br />
MOSI<br />
D00−D31<br />
MGTXRXN<br />
1 M1_0<br />
B<br />
FWE_B<br />
A00−A28<br />
MGTXTXP<br />
2 M2_0<br />
B<br />
DOUT_CSO_B<br />
DQS<br />
MGTXTXN<br />
P<br />
PROGRAM_B_0<br />
B<br />
CSI_B<br />
MRCC<br />
E<br />
MGTHAVCC_G#<br />
K<br />
TCK_0<br />
B<br />
PUDC_B<br />
SRCC<br />
V<br />
MGTHAVTT_G#<br />
I<br />
TDI_0<br />
U<br />
RDWR_B<br />
MGTHRXP<br />
O<br />
TDO_0<br />
r<br />
RS0−RS1<br />
MGTHRXN<br />
M<br />
TMS_0<br />
AD0P/AD0N−AD15P/AD15N<br />
MGTHTXP<br />
VCCADC_0<br />
EMCCLK<br />
MGTHTXN<br />
VCCBATT_0<br />
ug475_c3_21_090511<br />
Figure 3-17:<br />
FBG676 Package—XC7K160T, XC7K325T, <strong>and</strong> XC7K410T <strong>Pinout</strong> Diagram<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 63<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-18<br />
A<br />
1<br />
B 116 116<br />
C<br />
D 116 116<br />
E<br />
F 116 116<br />
G<br />
H 115 115<br />
J<br />
K 115 115<br />
L<br />
M 115 115<br />
N<br />
P 115 115<br />
R<br />
T<br />
U 34 34<br />
V 34 34 34 34<br />
W 34<br />
Y 34 34 34<br />
AA<br />
AB 34 34<br />
34 34 34<br />
34 34 34 34<br />
34 34 34<br />
AC 34 34 34 34<br />
AD 34<br />
AE 34<br />
AF<br />
1<br />
2<br />
116 116<br />
116 116<br />
116 116<br />
116 116<br />
115 115<br />
115 115<br />
115 115<br />
115 115<br />
116 116<br />
116 116<br />
116 116<br />
115 115<br />
115 115<br />
115 115<br />
34<br />
34<br />
16 16 16<br />
16 16 16 16<br />
16 16 16<br />
16 16<br />
16<br />
16 16<br />
16<br />
16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
33<br />
34 33 33 33<br />
34 34<br />
34 34 34 33<br />
34 34 34 34<br />
34 34 34 34<br />
34 34 34 34<br />
2<br />
3<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
34<br />
16 15 15<br />
16 16 15 15<br />
16 16 16 15<br />
16 16 16 16<br />
16 16<br />
33 33 33 33<br />
33 33 33 33<br />
33 33 33 33<br />
34 33 33 33<br />
6<br />
7<br />
33 33 33 33<br />
33 33<br />
33 33 33 33<br />
7<br />
8<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26<br />
16 16 16 16<br />
13 13 13 13<br />
13<br />
15 15 15 14<br />
15 15 15 15<br />
15 15 15 15<br />
16 15 15 15<br />
16 16 15 15<br />
33 33 32 32<br />
33 33 33 33<br />
33 33 32 32<br />
33 33 33 32<br />
33 33 32 32<br />
15 15 15 15<br />
13 13 13<br />
13 13 12 12<br />
32 32 12 12<br />
12 12 12 12<br />
12 12 12 12<br />
32 32 12 12<br />
32 32 32 12<br />
14 14 13 13<br />
12 12 12 U<br />
12 V<br />
12 12 12 12 W<br />
12 12 12 12<br />
12 12 12 12<br />
32 12 12 12<br />
12 12 Y<br />
12 12 12 AB<br />
12 AC<br />
12 12 12 12 AD<br />
12 12 12 12<br />
13 13 K<br />
13 13 13 13 13 13 13 M<br />
13 13 13 13<br />
13 13 13 13<br />
13 13<br />
15 14 14 14<br />
15 15 15 14<br />
15 15 15 15<br />
15 15 15 15<br />
14 14 14 14<br />
14 14 14 14<br />
15 14 14 14<br />
15 15 14 14<br />
15 15 15 14<br />
15 15 15 15<br />
15 15<br />
32 32 32 32<br />
33 33<br />
33 33 33 33<br />
32 32 32 32<br />
32 32 32 32<br />
33 32 32 32<br />
32 32 32 32<br />
32 32 32 32<br />
32 32 32 32<br />
32 32 32 32<br />
32 32 32 32<br />
15 14 14 14<br />
13 13 13 13 13 N<br />
13 13 13 13<br />
14 14 14 B<br />
14 14 14 14 D<br />
14 14 14 14<br />
14 14 14 14<br />
13 13 13 13 P<br />
13 13 13 13<br />
14 C<br />
14 14 E<br />
14 14 14 G<br />
14 H<br />
13 13 R<br />
12 12 AE<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26<br />
A<br />
F<br />
14 14 14 14 J<br />
L<br />
T<br />
AA<br />
AF<br />
ug475_c3_22_011111<br />
Figure 3-18:<br />
FBG676 Package—XC7K160T, XC7K325T, <strong>and</strong> XC7K410T I/O Banks<br />
X-Ref Target - Figure 3-19<br />
A<br />
B<br />
C<br />
D<br />
E<br />
F<br />
G<br />
H<br />
J<br />
K<br />
L<br />
M<br />
N<br />
P<br />
R<br />
T<br />
U 34 34<br />
V 34 34 34 34<br />
W 34<br />
Y 34 34 34<br />
AA<br />
AB 34 34<br />
34 34 34<br />
34 34 34 34<br />
34 34 34<br />
AC 34 34 34 34<br />
AD 34<br />
AE 34<br />
AF<br />
1<br />
1<br />
2<br />
34<br />
34<br />
16 16 16<br />
16 16 16 16<br />
16 16 16<br />
16 16<br />
16<br />
16 16<br />
16<br />
16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
33<br />
34 33 33 33<br />
34 34<br />
34 34 34 33<br />
34 34 34 34<br />
34 34 34 34<br />
34 34 34 34<br />
2<br />
3<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
34<br />
16 15 15<br />
16 16 15 15<br />
16 16 16 15<br />
16 16 16 16<br />
16 16<br />
33 33 33 33<br />
33 33 33 33<br />
33 33 33 33<br />
34 33 33 33<br />
6<br />
7<br />
33 33 33 33<br />
33 33<br />
33 33 33 33<br />
7<br />
8<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26<br />
16 16 16 16<br />
13 13 13 13<br />
13<br />
15 15 15 14<br />
15 15 15 15<br />
15 15 15 15<br />
16 15 15 15<br />
16 16 15 15<br />
33 33 32 32<br />
33 33 33 33<br />
33 33 32 32<br />
33 33 33 32<br />
33 33 32 32<br />
15 15 15 15<br />
13 13 13<br />
13 13 12 12<br />
32 32 12 12<br />
12 12 12 12<br />
12 12 12 12<br />
32 32 12 12<br />
32 32 32 12<br />
14 14 13 13<br />
12 12 12 U<br />
12 V<br />
12 12 12 12 W<br />
12 12 12 12<br />
12 12 12 12<br />
32 12 12 12<br />
12 12 Y<br />
12 12 12 AB<br />
12 AC<br />
12 12 12 12 AD<br />
12 12 12 12<br />
13 13 K<br />
13 13 13 13 13 13 13 M<br />
13 13 13 13<br />
13 13 13 13<br />
13 13<br />
15 14 14 14<br />
15 15 15 14<br />
15 15 15 15<br />
15 15 15 15<br />
14 14 14 14<br />
14 14 14 14<br />
15 14 14 14<br />
15 15 14 14<br />
15 15 15 14<br />
15 15 15 15<br />
15 15<br />
32 32 32 32<br />
33 33<br />
33 33 33 33<br />
32 32 32 32<br />
32 32 32 32<br />
33 32 32 32<br />
32 32 32 32<br />
32 32 32 32<br />
32 32 32 32<br />
32 32 32 32<br />
32 32 32 32<br />
15 14 14 14<br />
13 13 13 13 13 N<br />
13 13 13 13<br />
14 14 14 B<br />
14 14 14 14 D<br />
14 14 14 14<br />
14 14 14 14<br />
13 13 13 13 P<br />
13 13 13 13<br />
14 C<br />
14 14 E<br />
14 14 14 G<br />
14 H<br />
13 13 R<br />
12 12 AE<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26<br />
Memory Groupings Pins<br />
A<br />
F<br />
14 14 14 14 J<br />
L<br />
T<br />
AA<br />
AF<br />
# HP I/O<br />
# HR I/O<br />
# HP I/O − VCCAUX Group 0<br />
# HP I/O − VCCAUX Group 1<br />
# HP I/O − VCCAUX Group 2<br />
# HP I/O − VCCAUX Group 3<br />
# HP I/O − VCCAUX Group 4<br />
# HP I/O − VCCAUX Group 5<br />
# HP I/O − VCCAUX Group 6<br />
# HP I/O − VCCAUX Group 7<br />
# DQS pin<br />
# DCI pin<br />
# Memory Byte Group 0<br />
# Memory Byte Group 1<br />
# Memory Byte Group 2<br />
# Memory Byte Group 3<br />
# Bank Number<br />
ug475_c3_23_052311<br />
Figure 3-19:<br />
FBG676 Package—XC7K160T, XC7K325T, <strong>and</strong> XC7K410T Memory Groupings<br />
www.BDTIC.com/XILINX<br />
64 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Kintex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-20<br />
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26<br />
A<br />
16<br />
14<br />
A<br />
B<br />
16<br />
15<br />
B<br />
C<br />
16<br />
14 C<br />
D<br />
16<br />
14<br />
D<br />
E<br />
16<br />
15<br />
E<br />
F<br />
15<br />
14 F<br />
G<br />
16<br />
14<br />
G<br />
H<br />
16<br />
15<br />
H<br />
J<br />
15<br />
J<br />
K<br />
13 K<br />
L<br />
0<br />
14<br />
L<br />
M<br />
15<br />
M<br />
N<br />
13 N<br />
P<br />
0<br />
13<br />
P<br />
R<br />
0<br />
13<br />
R<br />
T<br />
0 0<br />
13 13 T<br />
U 34<br />
12<br />
U<br />
V<br />
33<br />
12<br />
V<br />
W<br />
33<br />
32<br />
W<br />
Y<br />
34<br />
32<br />
12 Y<br />
AA 34<br />
33<br />
12<br />
AA<br />
AB<br />
33<br />
32<br />
AB<br />
AC<br />
34<br />
32<br />
12 AC<br />
AD 34<br />
33<br />
12<br />
AD<br />
AE<br />
33<br />
32<br />
AE<br />
AF<br />
34<br />
32<br />
12 AF<br />
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26<br />
Power Pins<br />
# VCCO_#<br />
VCCINT<br />
VCCAUX<br />
# VCCAUX_IO_G#<br />
VCCBRAM<br />
VCCBATT_0<br />
VCCADC_0<br />
GNDADC_0<br />
MGTVCCAUX<br />
# MGTVCCAUX_G# or MGTHVCCAUX_G#<br />
MGTAVCC<br />
# MGTAVCC_G# or MGTHAVCC_G#<br />
MGTAVTT<br />
# MGTAVTT_G# or MGTHAVTT_G#<br />
GND<br />
ug475_c3_24_052311<br />
Figure 3-20:<br />
FBG676 Package—XC7K160T, XC7K325T, <strong>and</strong> XC7K410T Power <strong>and</strong> GND Placement<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 65<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
FBG900 Package—XC7K325T <strong>and</strong> XC7K410T<br />
X-Ref Target - Figure 3-21<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
A<br />
Y<br />
A<br />
B<br />
V<br />
E<br />
C<br />
B<br />
C<br />
V<br />
C<br />
D<br />
V<br />
E<br />
D<br />
E<br />
V<br />
K<br />
s<br />
E<br />
F<br />
V<br />
E<br />
M<br />
s<br />
s<br />
F<br />
G<br />
V<br />
O<br />
s<br />
s<br />
s<br />
G<br />
H<br />
V<br />
E<br />
I<br />
H<br />
J<br />
V<br />
J<br />
K<br />
V<br />
E<br />
P<br />
K<br />
L<br />
V<br />
L<br />
M<br />
V<br />
E<br />
D<br />
s<br />
r<br />
r<br />
B<br />
B<br />
B<br />
M<br />
N<br />
V<br />
N<br />
P<br />
V<br />
E<br />
s<br />
B<br />
P<br />
R<br />
V<br />
S<br />
S<br />
s<br />
B<br />
R<br />
T<br />
V<br />
V<br />
S<br />
S<br />
T<br />
U<br />
V<br />
L<br />
J<br />
B U B<br />
U<br />
V<br />
V<br />
V<br />
B<br />
V<br />
W<br />
V<br />
V<br />
G<br />
s<br />
W<br />
Y<br />
s<br />
s<br />
Y<br />
AA<br />
AA<br />
AB<br />
2 1<br />
0<br />
AB<br />
AC<br />
AC<br />
AD<br />
AD<br />
AE<br />
s<br />
s<br />
AE<br />
AF<br />
AF<br />
AG<br />
AG<br />
AH<br />
AH<br />
AJ<br />
AJ<br />
AK<br />
AK<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
User I/O Pins<br />
Transceiver Pins<br />
Dedicated Pins<br />
Other Pins<br />
IO_LXXY_#<br />
E<br />
MGTAVCC_G#<br />
C<br />
CCLK_0<br />
S<br />
VP_0<br />
GND<br />
s<br />
IO_XX_#<br />
V<br />
MGTAVTT_G#<br />
CFGBVS_0<br />
S<br />
VN_0<br />
VCCAUX_IO_G#<br />
Multi−Function Pins<br />
V<br />
V<br />
MGTVCCAUX_G#<br />
MGTAVTTRCAL<br />
G MGTRREF<br />
D<br />
J<br />
L<br />
DONE_0<br />
DXP_0<br />
DXN_0<br />
S<br />
S<br />
VREFP_0<br />
VREFN_0<br />
VCCAUX<br />
VCCINT<br />
VCCO_#<br />
B<br />
ADV_B<br />
VRN<br />
MGTREFCLK1/0P<br />
GNDADC_0<br />
VCCBRAM<br />
B<br />
FCS_B<br />
VRP<br />
MGTREFCLK1/0N<br />
Y<br />
INIT_B_0<br />
n<br />
NC<br />
B<br />
FOE_B<br />
VREF<br />
MGTXRXP<br />
0 M0_0<br />
B<br />
MOSI<br />
D00−D31<br />
MGTXRXN<br />
1 M1_0<br />
B<br />
FWE_B<br />
A00−A28<br />
MGTXTXP<br />
2 M2_0<br />
B<br />
DOUT_CSO_B<br />
DQS<br />
MGTXTXN<br />
P<br />
PROGRAM_B_0<br />
B<br />
CSI_B<br />
MRCC<br />
E<br />
MGTHAVCC_G#<br />
K<br />
TCK_0<br />
B<br />
PUDC_B<br />
SRCC<br />
V<br />
MGTHAVTT_G#<br />
I<br />
TDI_0<br />
U<br />
RDWR_B<br />
MGTHRXP<br />
O<br />
TDO_0<br />
r<br />
RS0−RS1<br />
MGTHRXN<br />
M<br />
TMS_0<br />
AD0P/AD0N−AD15P/AD15N<br />
MGTHTXP<br />
VCCADC_0<br />
EMCCLK<br />
MGTHTXN<br />
VCCBATT_0<br />
ug475_c3_25_090511<br />
Figure 3-21:<br />
FBG900 Package—XC7K325T <strong>and</strong> XC7K410T <strong>Pinout</strong> Diagram<br />
www.BDTIC.com/XILINX<br />
66 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Kintex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-22<br />
A<br />
117 117 117 117<br />
H 117 117<br />
M 116 116<br />
P 116 116<br />
T 115 115<br />
V 115 115<br />
Y 115 115<br />
AC 34 34<br />
AD 34 34 34 34<br />
AE 34<br />
AF 34 34 34<br />
AH 34 34<br />
34 34 34 34<br />
34 34 34<br />
34 34 34 34<br />
AJ 34 34 34 34<br />
AK 34<br />
118 118 118 118<br />
B 118 118 118 118<br />
C<br />
D 118 118<br />
E<br />
F<br />
G<br />
J<br />
K<br />
L<br />
N<br />
R<br />
U<br />
W<br />
AA<br />
AB<br />
AG<br />
1<br />
117 117 117 117<br />
117 117<br />
116 116<br />
116 116<br />
116 116<br />
115 115<br />
115 115<br />
115 115 115 115<br />
115 115<br />
117 117<br />
117 117 117 117<br />
1<br />
2<br />
2<br />
3<br />
118 118<br />
118 118<br />
116 116<br />
116 116<br />
116 116<br />
115 115<br />
33<br />
34 33 33 33<br />
34 34 33 33<br />
34<br />
34 34 34 34<br />
34 34 34 34<br />
34 34 34 34<br />
3<br />
4<br />
4<br />
5<br />
118 118<br />
5<br />
6<br />
118 118<br />
118 118<br />
117 117<br />
116 116<br />
116 116<br />
115 115<br />
115 115<br />
18 18 18<br />
18 18<br />
18 18 18 18<br />
18<br />
18 18 18<br />
18 18 18 18 18 17<br />
18 17 17 17 17 17 17 16<br />
18 18 17 17<br />
18 18 18 18<br />
17 17 17 17<br />
17 17 17 17<br />
18 18 17 17<br />
17 17 17 17<br />
18 18 18 18 18 17 17 17<br />
18<br />
18 18 18 18<br />
18 18 18<br />
33 33<br />
33 33 33 33<br />
33 33 33 33<br />
33 33 33 33<br />
34 34 33 33<br />
34 34 34 33<br />
6<br />
7<br />
7<br />
8<br />
18 18 18 18<br />
18 18 18 18<br />
18 18 17 17<br />
33 32 32 32<br />
33 33 32 32<br />
33 33 33 32<br />
33 33 33 33<br />
33 33 33 33<br />
34 33 33 33<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
33 32 32 32<br />
33 33 32 32<br />
33 33 33 33<br />
33 32 32 32<br />
33 33 32 32<br />
17 17 17 17<br />
17 17 17 17<br />
17 17 17 15<br />
15 15<br />
14 14 14 14 14 14 14 14 14 14 R<br />
14 14<br />
12 12 12 12<br />
12 12 12 12<br />
32 32 32 12 12 12 12 13<br />
32 32 32 32<br />
32 12 12 12<br />
12 12 12 12<br />
12 12 13 13<br />
32 32 12 12 12 12 12 13<br />
32 32 32 12<br />
12 12 12 12<br />
32 12 12 12<br />
32 32 12 12<br />
15 15 15 14<br />
14 14 14 14<br />
14 14 14 14<br />
14<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
15<br />
32 32 32 32<br />
32 32 32 32<br />
17 16 16 16 16 16 16 16 B<br />
17 17 16 16<br />
17 17 17 16<br />
17 17 17 17<br />
32 32<br />
32 32 32 32<br />
32 32 32 32<br />
16 16 16 16<br />
17 16 16 16<br />
15 15 15 15 15 15 15 K<br />
12 12 12 12<br />
12 12 12 12<br />
13 13<br />
13 13 13 13<br />
12 13 13 13<br />
12 12 13 13<br />
12 12 12 13<br />
14 14 14 14<br />
14 14 14 14<br />
14 13 13 13<br />
13 13 13 Y<br />
13 AA<br />
13 13 13 13 AB<br />
13 13 13 13<br />
13 13 AC<br />
13 13 13 AE<br />
13 AF<br />
13 13 13 13 AG<br />
13 13 13 13<br />
14 T<br />
14 14 14 14 14 14 14 14 U<br />
14 14 14 14<br />
16 16 16 16 15 16 H<br />
15 15 15 15<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
16 A<br />
16 16 C<br />
16 16 16 E<br />
16 F<br />
16 16 16 16 G<br />
15<br />
15 15 15 15 M<br />
15 15 N<br />
14 14 14 14 14 14 V<br />
13 13 AH<br />
13 13 13 AK<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
ug475_c3_26_011111<br />
D<br />
J<br />
L<br />
P<br />
W<br />
AD<br />
AJ<br />
Figure 3-22:<br />
FBG900 Package—XC7K325T <strong>and</strong> XC7K410T I/O Banks<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 67<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-23<br />
A<br />
B<br />
C<br />
D<br />
E<br />
F<br />
G<br />
H<br />
J<br />
K<br />
L<br />
M<br />
N<br />
P<br />
R<br />
T<br />
U<br />
V<br />
W<br />
Y<br />
AA<br />
AB<br />
AC 34 34<br />
AD 34 34 34 34<br />
AE 34<br />
AF 34 34 34<br />
AG<br />
1<br />
AH 34 34<br />
34 34 34 34<br />
34 34 34<br />
34 34 34 34<br />
AJ 34 34 34 34<br />
AK 34<br />
1<br />
2<br />
2<br />
3<br />
33<br />
34 33 33 33<br />
34 34 33 33<br />
34<br />
34 34 34 34<br />
34 34 34 34<br />
34 34 34 34<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
18 18 18<br />
18 18<br />
18 18 18 18<br />
18<br />
18 18 18<br />
18 18 18 18 18 17<br />
18 17 17 17 17 17 17 16<br />
18 18 17 17<br />
18 18 18 18<br />
17 17 17 17<br />
17 17 17 17<br />
18 18 17 17<br />
17 17 17 17<br />
18 18 18 18 18 17 17 17<br />
18<br />
18 18 18 18<br />
18 18 18<br />
33 33<br />
33 33 33 33<br />
33 33 33 33<br />
33 33 33 33<br />
34 34 33 33<br />
34 34 34 33<br />
6<br />
7<br />
7<br />
8<br />
18 18 18 18<br />
18 18 18 18<br />
18 18 17 17<br />
33 32 32 32<br />
33 33 32 32<br />
33 33 33 32<br />
33 33 33 33<br />
33 33 33 33<br />
34 33 33 33<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
33 32 32 32<br />
33 33 32 32<br />
33 33 33 33<br />
33 32 32 32<br />
33 33 32 32<br />
17 17 17 17<br />
17 17 17 17<br />
17 17 17 15<br />
15 15<br />
14 14 14 14 14 14 14 14 14 14 R<br />
14 14<br />
12 12 12 12<br />
12 12 12 12<br />
32 32 32 12 12 12 12 13<br />
32 32 32 32<br />
32 12 12 12<br />
12 12 12 12<br />
12 12 13 13<br />
32 32 12 12 12 12 12 13<br />
32 32 32 12<br />
12 12 12 12<br />
32 12 12 12<br />
32 32 12 12<br />
15 15 15 14<br />
14 14 14 14<br />
14 14 14 14<br />
14<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
15<br />
32 32 32 32<br />
32 32 32 32<br />
17 16 16 16 16 16 16 16 B<br />
17 17 16 16<br />
17 17 17 16<br />
17 17 17 17<br />
32 32<br />
32 32 32 32<br />
32 32 32 32<br />
16 16 16 16<br />
17 16 16 16<br />
15 15 15 15 15 15 15 K<br />
12 12 12 12<br />
12 12 12 12<br />
13 13<br />
13 13 13 13<br />
12 13 13 13<br />
12 12 13 13<br />
12 12 12 13<br />
14 14 14 14<br />
14 14 14 14<br />
14 13 13 13<br />
13 13 13 Y<br />
13 AA<br />
13 13 13 13 AB<br />
13 13 13 13<br />
13 13 AC<br />
13 13 13 AE<br />
13 AF<br />
13 13 13 13 AG<br />
13 13 13 13<br />
14 T<br />
14 14 14 14 14 14 14 14 U<br />
14 14 14 14<br />
16 16 16 16 15 16 H<br />
15 15 15 15<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
16 A<br />
16 16 C<br />
16 16 16 E<br />
16 F<br />
16 16 16 16 G<br />
15<br />
15 15 15 15 M<br />
15 15 N<br />
14 14 14 14 14 14 V<br />
13 13 AH<br />
13 13 13 AK<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
Memory Groupings Pins<br />
D<br />
J<br />
L<br />
P<br />
W<br />
AD<br />
AJ<br />
# HP I/O<br />
# HR I/O<br />
# HP I/O − VCCAUX Group 0<br />
# HP I/O − VCCAUX Group 1<br />
# HP I/O − VCCAUX Group 2<br />
# HP I/O − VCCAUX Group 3<br />
# HP I/O − VCCAUX Group 4<br />
# HP I/O − VCCAUX Group 5<br />
# HP I/O − VCCAUX Group 6<br />
# HP I/O − VCCAUX Group 7<br />
# DQS pin<br />
# DCI pin<br />
# Memory Byte Group 0<br />
# Memory Byte Group 1<br />
# Memory Byte Group 2<br />
# Memory Byte Group 3<br />
# Bank Number<br />
ug475_c3_27_052311<br />
Figure 3-23:<br />
FBG900 Package—XC7K325T <strong>and</strong> XC7K410T Memory Groupings<br />
www.BDTIC.com/XILINX<br />
68 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Kintex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-24<br />
1 2 3 4 5<br />
A<br />
B<br />
C<br />
D<br />
E<br />
F<br />
G<br />
H<br />
J<br />
K<br />
L<br />
M<br />
N<br />
P<br />
R<br />
T<br />
U<br />
V<br />
W<br />
Y<br />
AA<br />
AB<br />
AC 34<br />
AD<br />
AE<br />
AF<br />
34<br />
AG 34<br />
AH<br />
AJ<br />
34<br />
AK 34<br />
1 2 3 4 5<br />
6<br />
0<br />
6<br />
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
17<br />
16 A<br />
17<br />
16<br />
B<br />
18<br />
16<br />
C<br />
18<br />
17<br />
16 D<br />
17<br />
16<br />
E<br />
18<br />
16<br />
F<br />
18<br />
17<br />
G<br />
17<br />
16 H<br />
18<br />
15<br />
J<br />
18<br />
15<br />
K<br />
17<br />
15 L<br />
15<br />
M<br />
15<br />
N<br />
15<br />
14 P<br />
14<br />
R<br />
0<br />
14<br />
T<br />
14<br />
U<br />
0<br />
14 V<br />
0 0<br />
14<br />
W<br />
33<br />
12<br />
Y<br />
33<br />
32<br />
13 AA<br />
32<br />
13<br />
AB<br />
33<br />
12<br />
AC<br />
33<br />
12<br />
13 AD<br />
34<br />
32<br />
13<br />
AE<br />
32<br />
12<br />
AF<br />
33<br />
12<br />
AG<br />
34<br />
32<br />
13 AH<br />
32<br />
13<br />
AJ<br />
33<br />
12<br />
AK<br />
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
Power Pins<br />
# VCCO_#<br />
VCCINT<br />
VCCAUX<br />
# VCCAUX_IO_G#<br />
VCCBRAM<br />
VCCBATT_0<br />
VCCADC_0<br />
GNDADC_0<br />
MGTVCCAUX<br />
# MGTVCCAUX_G# or MGTHVCCAUX_G#<br />
MGTAVCC<br />
# MGTAVCC_G# or MGTHAVCC_G#<br />
MGTAVTT<br />
# MGTAVTT_G# or MGTHAVTT_G#<br />
GND<br />
ug475_c3_28_052311<br />
Figure 3-24:<br />
FBG900 Package—XC7K325T <strong>and</strong> XC7K410T Power <strong>and</strong> GND Placement<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 69<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
FFG676 Package—XC7K160T, XC7K325T, <strong>and</strong> XC7K410T<br />
X-Ref Target - Figure 3-25<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26<br />
A<br />
A<br />
B<br />
V<br />
B<br />
B<br />
B<br />
C<br />
V<br />
E<br />
C<br />
B<br />
C<br />
D<br />
V<br />
B<br />
B<br />
D<br />
E<br />
E<br />
U<br />
E<br />
F<br />
F<br />
G<br />
V<br />
E<br />
Y<br />
B<br />
G<br />
H<br />
V<br />
H<br />
J<br />
E<br />
D<br />
s<br />
s<br />
J<br />
K<br />
s<br />
r<br />
s<br />
K<br />
L<br />
V<br />
E<br />
K<br />
r<br />
B<br />
s<br />
L<br />
M<br />
V<br />
V<br />
G<br />
s<br />
B<br />
M<br />
N<br />
V<br />
M<br />
S<br />
S<br />
s<br />
N<br />
P<br />
2<br />
P<br />
S<br />
S<br />
P<br />
R<br />
I<br />
O<br />
L<br />
J<br />
R<br />
T<br />
1<br />
0<br />
T<br />
U<br />
s<br />
s<br />
U<br />
V<br />
V<br />
W<br />
W<br />
Y<br />
s<br />
Y<br />
AA<br />
AA<br />
AB<br />
AB<br />
AC<br />
AC<br />
AD<br />
AD<br />
AE<br />
AE<br />
AF<br />
AF<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26<br />
User I/O Pins<br />
Transceiver Pins<br />
Dedicated Pins<br />
Other Pins<br />
IO_LXXY_#<br />
E<br />
MGTAVCC_G#<br />
C<br />
CCLK_0<br />
S<br />
VP_0<br />
GND<br />
s<br />
IO_XX_#<br />
V<br />
MGTAVTT_G#<br />
CFGBVS_0<br />
S<br />
VN_0<br />
VCCAUX_IO_G#<br />
Multi−Function Pins<br />
V<br />
V<br />
MGTVCCAUX_G#<br />
MGTAVTTRCAL<br />
G MGTRREF<br />
D<br />
J<br />
L<br />
DONE_0<br />
DXP_0<br />
DXN_0<br />
S<br />
S<br />
VREFP_0<br />
VREFN_0<br />
VCCAUX<br />
VCCINT<br />
VCCO_#<br />
B<br />
ADV_B<br />
VRN<br />
MGTREFCLK1/0P<br />
GNDADC_0<br />
VCCBRAM<br />
B<br />
FCS_B<br />
VRP<br />
MGTREFCLK1/0N<br />
Y<br />
INIT_B_0<br />
n<br />
NC<br />
B<br />
FOE_B<br />
VREF<br />
MGTXRXP<br />
0 M0_0<br />
B<br />
MOSI<br />
D00−D31<br />
MGTXRXN<br />
1 M1_0<br />
B<br />
FWE_B<br />
A00−A28<br />
MGTXTXP<br />
2 M2_0<br />
B<br />
DOUT_CSO_B<br />
DQS<br />
MGTXTXN<br />
P<br />
PROGRAM_B_0<br />
B<br />
CSI_B<br />
MRCC<br />
E<br />
MGTHAVCC_G#<br />
K<br />
TCK_0<br />
B<br />
PUDC_B<br />
SRCC<br />
V<br />
MGTHAVTT_G#<br />
I<br />
TDI_0<br />
U<br />
RDWR_B<br />
MGTHRXP<br />
O<br />
TDO_0<br />
r<br />
RS0−RS1<br />
MGTHRXN<br />
M<br />
TMS_0<br />
AD0P/AD0N−AD15P/AD15N<br />
MGTHTXP<br />
VCCADC_0<br />
EMCCLK<br />
MGTHTXN<br />
VCCBATT_0<br />
ug475_c3_29_090511<br />
Figure 3-25:<br />
FFG676 Package—XC7K160T, XC7K325T, <strong>and</strong> XC7K410T <strong>Pinout</strong> Diagram<br />
www.BDTIC.com/XILINX<br />
70 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Kintex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-26<br />
A<br />
1<br />
B 116 116<br />
C<br />
D 116 116<br />
E<br />
F 116 116<br />
G<br />
H 115 115<br />
J<br />
K 115 115<br />
L<br />
M 115 115<br />
N<br />
P 115 115<br />
R<br />
T<br />
U 34 34<br />
V 34 34 34 34<br />
W 34<br />
Y 34 34 34<br />
AA<br />
AB 34 34<br />
34 34 34<br />
34 34 34 34<br />
34 34 34<br />
AC 34 34 34 34<br />
AD 34<br />
AE 34<br />
AF<br />
1<br />
2<br />
116 116<br />
116 116<br />
116 116<br />
116 116<br />
115 115<br />
115 115<br />
115 115<br />
115 115<br />
116 116<br />
116 116<br />
116 116<br />
115 115<br />
115 115<br />
115 115<br />
34<br />
34<br />
16 16 16<br />
16 16 16 16<br />
16 16 16<br />
16 16<br />
16<br />
16 16<br />
16<br />
16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
33<br />
34 33 33 33<br />
34 34<br />
34 34 34 33<br />
34 34 34 34<br />
34 34 34 34<br />
34 34 34 34<br />
2<br />
3<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
34<br />
16 15 15<br />
16 16 15 15<br />
16 16 16 15<br />
16 16 16 16<br />
16 16<br />
33 33 33 33<br />
33 33 33 33<br />
33 33 33 33<br />
34 33 33 33<br />
6<br />
7<br />
33 33 33 33<br />
33 33<br />
33 33 33 33<br />
7<br />
8<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26<br />
16 16 16 16<br />
13 13 13 13<br />
13<br />
15 15 15 14<br />
15 15 15 15<br />
15 15 15 15<br />
16 15 15 15<br />
16 16 15 15<br />
33 33 32 32<br />
33 33 33 33<br />
33 33 32 32<br />
33 33 33 32<br />
33 33 32 32<br />
15 15 15 15<br />
13 13 13<br />
13 13 12 12<br />
32 32 12 12<br />
12 12 12 12<br />
12 12 12 12<br />
32 32 12 12<br />
32 32 32 12<br />
14 14 13 13<br />
12 12 12 U<br />
12 V<br />
12 12 12 12 W<br />
12 12 12 12<br />
12 12 12 12<br />
32 12 12 12<br />
12 12 Y<br />
12 12 12 AB<br />
12 AC<br />
12 12 12 12 AD<br />
12 12 12 12<br />
13 13 K<br />
13 13 13 13 13 13 13 M<br />
13 13 13 13<br />
13 13 13 13<br />
13 13<br />
15 14 14 14<br />
15 15 15 14<br />
15 15 15 15<br />
15 15 15 15<br />
14 14 14 14<br />
14 14 14 14<br />
15 14 14 14<br />
15 15 14 14<br />
15 15 15 14<br />
15 15 15 15<br />
15 15<br />
32 32 32 32<br />
33 33<br />
33 33 33 33<br />
32 32 32 32<br />
32 32 32 32<br />
33 32 32 32<br />
32 32 32 32<br />
32 32 32 32<br />
32 32 32 32<br />
32 32 32 32<br />
32 32 32 32<br />
15 14 14 14<br />
13 13 13 13 13 N<br />
13 13 13 13<br />
14 14 14 B<br />
14 14 14 14 D<br />
14 14 14 14<br />
14 14 14 14<br />
13 13 13 13 P<br />
13 13 13 13<br />
14 C<br />
14 14 E<br />
14 14 14 G<br />
14 H<br />
13 13 R<br />
12 12 AE<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26<br />
A<br />
F<br />
14 14 14 14 J<br />
L<br />
T<br />
AA<br />
AF<br />
ug475_c3_30_011111<br />
Figure 3-26:<br />
FFG676 Package—XC7K160T, XC7K325T, <strong>and</strong> XC7K410T I/O Banks<br />
X-Ref Target - Figure 3-27<br />
A<br />
B<br />
C<br />
D<br />
E<br />
F<br />
G<br />
H<br />
J<br />
K<br />
L<br />
M<br />
N<br />
P<br />
R<br />
T<br />
U 34 34<br />
V 34 34 34 34<br />
W 34<br />
Y 34 34 34<br />
AA<br />
AB 34 34<br />
34 34 34<br />
34 34 34 34<br />
34 34 34<br />
AC 34 34 34 34<br />
AD 34<br />
AE 34<br />
AF<br />
1<br />
1<br />
2<br />
34<br />
34<br />
16 16 16<br />
16 16 16 16<br />
16 16 16<br />
16 16<br />
16<br />
16 16<br />
16<br />
16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
33<br />
34 33 33 33<br />
34 34<br />
34 34 34 33<br />
34 34 34 34<br />
34 34 34 34<br />
34 34 34 34<br />
2<br />
3<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
34<br />
16 15 15<br />
16 16 15 15<br />
16 16 16 15<br />
16 16 16 16<br />
16 16<br />
33 33 33 33<br />
33 33 33 33<br />
33 33 33 33<br />
34 33 33 33<br />
6<br />
7<br />
33 33 33 33<br />
33 33<br />
33 33 33 33<br />
7<br />
8<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26<br />
16 16 16 16<br />
13 13 13 13<br />
13<br />
15 15 15 14<br />
15 15 15 15<br />
15 15 15 15<br />
16 15 15 15<br />
16 16 15 15<br />
33 33 32 32<br />
33 33 33 33<br />
33 33 32 32<br />
33 33 33 32<br />
33 33 32 32<br />
15 15 15 15<br />
13 13 13<br />
13 13 12 12<br />
32 32 12 12<br />
12 12 12 12<br />
12 12 12 12<br />
32 32 12 12<br />
32 32 32 12<br />
14 14 13 13<br />
12 12 12 U<br />
12 V<br />
12 12 12 12 W<br />
12 12 12 12<br />
12 12 12 12<br />
32 12 12 12<br />
12 12 Y<br />
12 12 12 AB<br />
12 AC<br />
12 12 12 12 AD<br />
12 12 12 12<br />
13 13 K<br />
13 13 13 13 13 13 13 M<br />
13 13 13 13<br />
13 13 13 13<br />
13 13<br />
15 14 14 14<br />
15 15 15 14<br />
15 15 15 15<br />
15 15 15 15<br />
14 14 14 14<br />
14 14 14 14<br />
15 14 14 14<br />
15 15 14 14<br />
15 15 15 14<br />
15 15 15 15<br />
15 15<br />
32 32 32 32<br />
33 33<br />
33 33 33 33<br />
32 32 32 32<br />
32 32 32 32<br />
33 32 32 32<br />
32 32 32 32<br />
32 32 32 32<br />
32 32 32 32<br />
32 32 32 32<br />
32 32 32 32<br />
15 14 14 14<br />
13 13 13 13 13 N<br />
13 13 13 13<br />
14 14 14 B<br />
14 14 14 14 D<br />
14 14 14 14<br />
14 14 14 14<br />
13 13 13 13 P<br />
13 13 13 13<br />
14 C<br />
14 14 E<br />
14 14 14 G<br />
14 H<br />
13 13 R<br />
12 12 AE<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26<br />
Memory Groupings Pins<br />
A<br />
F<br />
14 14 14 14 J<br />
L<br />
T<br />
AA<br />
AF<br />
# HP I/O<br />
# HR I/O<br />
# HP I/O − VCCAUX Group 0<br />
# HP I/O − VCCAUX Group 1<br />
# HP I/O − VCCAUX Group 2<br />
# HP I/O − VCCAUX Group 3<br />
# HP I/O − VCCAUX Group 4<br />
# HP I/O − VCCAUX Group 5<br />
# HP I/O − VCCAUX Group 6<br />
# HP I/O − VCCAUX Group 7<br />
# DQS pin<br />
# DCI pin<br />
# Memory Byte Group 0<br />
# Memory Byte Group 1<br />
# Memory Byte Group 2<br />
# Memory Byte Group 3<br />
# Bank Number<br />
ug475_c3_31_052311<br />
Figure 3-27:<br />
FFG676 Package—XC7K160T, XC7K325T, <strong>and</strong> XC7K410T Memory Groupings<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 71<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-28<br />
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26<br />
A<br />
16<br />
14<br />
A<br />
B<br />
16<br />
15<br />
B<br />
C<br />
16<br />
14 C<br />
D<br />
16<br />
14<br />
D<br />
E<br />
16<br />
15<br />
E<br />
F<br />
15<br />
14 F<br />
G<br />
16<br />
14<br />
G<br />
H<br />
16<br />
15<br />
H<br />
J<br />
15<br />
J<br />
K<br />
13 K<br />
L<br />
0<br />
14<br />
L<br />
M<br />
15<br />
M<br />
N<br />
13 N<br />
P<br />
0<br />
13<br />
P<br />
R<br />
0<br />
13<br />
R<br />
T<br />
0 0<br />
13 13 T<br />
U 34<br />
12<br />
U<br />
V<br />
33<br />
12<br />
V<br />
W<br />
33<br />
32<br />
W<br />
Y<br />
34<br />
32<br />
12 Y<br />
AA 34<br />
33<br />
12<br />
AA<br />
AB<br />
33<br />
32<br />
AB<br />
AC<br />
34<br />
32<br />
12 AC<br />
AD 34<br />
33<br />
12<br />
AD<br />
AE<br />
33<br />
32<br />
AE<br />
AF<br />
34<br />
32<br />
12 AF<br />
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26<br />
Power Pins<br />
# VCCO_#<br />
VCCINT<br />
VCCAUX<br />
# VCCAUX_IO_G#<br />
VCCBRAM<br />
VCCBATT_0<br />
VCCADC_0<br />
GNDADC_0<br />
MGTVCCAUX<br />
# MGTVCCAUX_G# or MGTHVCCAUX_G#<br />
MGTAVCC<br />
# MGTAVCC_G# or MGTHAVCC_G#<br />
MGTAVTT<br />
# MGTAVTT_G# or MGTHAVTT_G#<br />
GND<br />
ug475_c3_32_052311<br />
Figure 3-28:<br />
FFG676 Package—XC7K160T, XC7K325T, <strong>and</strong> XC7K410T Power <strong>and</strong> GND Placement<br />
www.BDTIC.com/XILINX<br />
72 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Kintex-7 <strong>FPGAs</strong> Device Diagrams<br />
FFG900 Package—XC7K325T <strong>and</strong> XC7K410T<br />
X-Ref Target - Figure 3-29<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
A<br />
Y<br />
A<br />
B<br />
V<br />
E<br />
C<br />
B<br />
C<br />
V<br />
C<br />
D<br />
V<br />
E<br />
D<br />
E<br />
V<br />
K<br />
s<br />
E<br />
F<br />
V<br />
E<br />
M<br />
s<br />
s<br />
F<br />
G<br />
V<br />
O<br />
s<br />
s<br />
s<br />
G<br />
H<br />
V<br />
E<br />
I<br />
H<br />
J<br />
V<br />
J<br />
K<br />
V<br />
E<br />
P<br />
K<br />
L<br />
V<br />
L<br />
M<br />
V<br />
E<br />
D<br />
s<br />
r<br />
r<br />
B<br />
B<br />
B<br />
M<br />
N<br />
V<br />
N<br />
P<br />
V<br />
E<br />
s<br />
B<br />
P<br />
R<br />
V<br />
S<br />
S<br />
s<br />
B<br />
R<br />
T<br />
V<br />
V<br />
S<br />
S<br />
T<br />
U<br />
V<br />
L<br />
J<br />
B U B<br />
U<br />
V<br />
V<br />
V<br />
B<br />
V<br />
W<br />
V<br />
V<br />
G<br />
s<br />
W<br />
Y<br />
s<br />
s<br />
Y<br />
AA<br />
AA<br />
AB<br />
2 1<br />
0<br />
AB<br />
AC<br />
AC<br />
AD<br />
AD<br />
AE<br />
s<br />
s<br />
AE<br />
AF<br />
AF<br />
AG<br />
AG<br />
AH<br />
AH<br />
AJ<br />
AJ<br />
AK<br />
AK<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
User I/O Pins<br />
Transceiver Pins<br />
Dedicated Pins<br />
Other Pins<br />
IO_LXXY_#<br />
E<br />
MGTAVCC_G#<br />
C<br />
CCLK_0<br />
S<br />
VP_0<br />
GND<br />
s<br />
IO_XX_#<br />
V<br />
MGTAVTT_G#<br />
CFGBVS_0<br />
S<br />
VN_0<br />
VCCAUX_IO_G#<br />
Multi−Function Pins<br />
V<br />
V<br />
MGTVCCAUX_G#<br />
MGTAVTTRCAL<br />
G MGTRREF<br />
D<br />
J<br />
L<br />
DONE_0<br />
DXP_0<br />
DXN_0<br />
S<br />
S<br />
VREFP_0<br />
VREFN_0<br />
VCCAUX<br />
VCCINT<br />
VCCO_#<br />
B<br />
ADV_B<br />
VRN<br />
MGTREFCLK1/0P<br />
GNDADC_0<br />
VCCBRAM<br />
B<br />
FCS_B<br />
VRP<br />
MGTREFCLK1/0N<br />
Y<br />
INIT_B_0<br />
n<br />
NC<br />
B<br />
FOE_B<br />
VREF<br />
MGTXRXP<br />
0 M0_0<br />
B<br />
MOSI<br />
D00−D31<br />
MGTXRXN<br />
1 M1_0<br />
B<br />
FWE_B<br />
A00−A28<br />
MGTXTXP<br />
2 M2_0<br />
B<br />
DOUT_CSO_B<br />
DQS<br />
MGTXTXN<br />
P<br />
PROGRAM_B_0<br />
B<br />
CSI_B<br />
MRCC<br />
E<br />
MGTHAVCC_G#<br />
K<br />
TCK_0<br />
B<br />
PUDC_B<br />
SRCC<br />
V<br />
MGTHAVTT_G#<br />
I<br />
TDI_0<br />
U<br />
RDWR_B<br />
MGTHRXP<br />
O<br />
TDO_0<br />
r<br />
RS0−RS1<br />
MGTHRXN<br />
M<br />
TMS_0<br />
AD0P/AD0N−AD15P/AD15N<br />
MGTHTXP<br />
VCCADC_0<br />
EMCCLK<br />
MGTHTXN<br />
VCCBATT_0<br />
ug475_c3_33_090511<br />
Figure 3-29:<br />
FFG900 Package—XC7K325T <strong>and</strong> XC7K410T <strong>Pinout</strong> Diagram<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 73<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-30<br />
A<br />
117 117 117 117<br />
H 117 117<br />
M 116 116<br />
P 116 116<br />
T 115 115<br />
V 115 115<br />
Y 115 115<br />
AC 34 34<br />
AD 34 34 34 34<br />
AE 34<br />
AF 34 34 34<br />
AH 34 34<br />
34 34 34 34<br />
34 34 34<br />
34 34 34 34<br />
AJ 34 34 34 34<br />
AK 34<br />
118 118 118 118<br />
B 118 118 118 118<br />
C<br />
D 118 118<br />
E<br />
F<br />
G<br />
J<br />
K<br />
L<br />
N<br />
R<br />
U<br />
W<br />
AA<br />
AB<br />
AG<br />
1<br />
117 117 117 117<br />
117 117<br />
116 116<br />
116 116<br />
116 116<br />
115 115<br />
115 115<br />
115 115 115 115<br />
115 115<br />
117 117<br />
117 117 117 117<br />
1<br />
2<br />
2<br />
3<br />
118 118<br />
118 118<br />
116 116<br />
116 116<br />
116 116<br />
115 115<br />
33<br />
34 33 33 33<br />
34 34 33 33<br />
34<br />
34 34 34 34<br />
34 34 34 34<br />
34 34 34 34<br />
3<br />
4<br />
4<br />
5<br />
118 118<br />
5<br />
6<br />
118 118<br />
118 118<br />
117 117<br />
116 116<br />
116 116<br />
115 115<br />
115 115<br />
18 18 18<br />
18 18<br />
18 18 18 18<br />
18<br />
18 18 18<br />
18 18 18 18 18 17<br />
18 17 17 17 17 17 17 16<br />
18 18 17 17<br />
18 18 18 18<br />
17 17 17 17<br />
17 17 17 17<br />
18 18 17 17<br />
17 17 17 17<br />
18 18 18 18 18 17 17 17<br />
18<br />
18 18 18 18<br />
18 18 18<br />
33 33<br />
33 33 33 33<br />
33 33 33 33<br />
33 33 33 33<br />
34 34 33 33<br />
34 34 34 33<br />
6<br />
7<br />
7<br />
8<br />
18 18 18 18<br />
18 18 18 18<br />
18 18 17 17<br />
33 32 32 32<br />
33 33 32 32<br />
33 33 33 32<br />
33 33 33 33<br />
33 33 33 33<br />
34 33 33 33<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
33 32 32 32<br />
33 33 32 32<br />
33 33 33 33<br />
33 32 32 32<br />
33 33 32 32<br />
17 17 17 17<br />
17 17 17 17<br />
17 17 17 15<br />
15 15<br />
14 14 14 14 14 14 14 14 14 14 R<br />
14 14<br />
12 12 12 12<br />
12 12 12 12<br />
32 32 32 12 12 12 12 13<br />
32 32 32 32<br />
32 12 12 12<br />
12 12 12 12<br />
12 12 13 13<br />
32 32 12 12 12 12 12 13<br />
32 32 32 12<br />
12 12 12 12<br />
32 12 12 12<br />
32 32 12 12<br />
15 15 15 14<br />
14 14 14 14<br />
14 14 14 14<br />
14<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
15<br />
32 32 32 32<br />
32 32 32 32<br />
17 16 16 16 16 16 16 16 B<br />
17 17 16 16<br />
17 17 17 16<br />
17 17 17 17<br />
32 32<br />
32 32 32 32<br />
32 32 32 32<br />
16 16 16 16<br />
17 16 16 16<br />
15 15 15 15 15 15 15 K<br />
12 12 12 12<br />
12 12 12 12<br />
13 13<br />
13 13 13 13<br />
12 13 13 13<br />
12 12 13 13<br />
12 12 12 13<br />
14 14 14 14<br />
14 14 14 14<br />
14 13 13 13<br />
13 13 13 Y<br />
13 AA<br />
13 13 13 13 AB<br />
13 13 13 13<br />
13 13 AC<br />
13 13 13 AE<br />
13 AF<br />
13 13 13 13 AG<br />
13 13 13 13<br />
14 T<br />
14 14 14 14 14 14 14 14 U<br />
14 14 14 14<br />
16 16 16 16 15 16 H<br />
15 15 15 15<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
16 A<br />
16 16 C<br />
16 16 16 E<br />
16 F<br />
16 16 16 16 G<br />
15<br />
15 15 15 15 M<br />
15 15 N<br />
14 14 14 14 14 14 V<br />
13 13 AH<br />
13 13 13 AK<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
ug475_c3_34_011111<br />
D<br />
J<br />
L<br />
P<br />
W<br />
AD<br />
AJ<br />
Figure 3-30:<br />
FFG900 Package—XC7K325T <strong>and</strong> XC7K410T I/O Banks<br />
www.BDTIC.com/XILINX<br />
74 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Kintex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-31<br />
A<br />
B<br />
C<br />
D<br />
E<br />
F<br />
G<br />
H<br />
J<br />
K<br />
L<br />
M<br />
N<br />
P<br />
R<br />
T<br />
U<br />
V<br />
W<br />
Y<br />
AA<br />
AB<br />
AC 34 34<br />
AD 34 34 34 34<br />
AE 34<br />
AF 34 34 34<br />
AG<br />
1<br />
AH 34 34<br />
34 34 34 34<br />
34 34 34<br />
34 34 34 34<br />
AJ 34 34 34 34<br />
AK 34<br />
1<br />
2<br />
2<br />
3<br />
33<br />
34 33 33 33<br />
34 34 33 33<br />
34<br />
34 34 34 34<br />
34 34 34 34<br />
34 34 34 34<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
18 18 18<br />
18 18<br />
18 18 18 18<br />
18<br />
18 18 18<br />
18 18 18 18 18 17<br />
18 17 17 17 17 17 17 16<br />
18 18 17 17<br />
18 18 18 18<br />
17 17 17 17<br />
17 17 17 17<br />
18 18 17 17<br />
17 17 17 17<br />
18 18 18 18 18 17 17 17<br />
18<br />
18 18 18 18<br />
18 18 18<br />
33 33<br />
33 33 33 33<br />
33 33 33 33<br />
33 33 33 33<br />
34 34 33 33<br />
34 34 34 33<br />
6<br />
7<br />
7<br />
8<br />
18 18 18 18<br />
18 18 18 18<br />
18 18 17 17<br />
33 32 32 32<br />
33 33 32 32<br />
33 33 33 32<br />
33 33 33 33<br />
33 33 33 33<br />
34 33 33 33<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
33 32 32 32<br />
33 33 32 32<br />
33 33 33 33<br />
33 32 32 32<br />
33 33 32 32<br />
17 17 17 17<br />
17 17 17 17<br />
17 17 17 15<br />
15 15<br />
14 14 14 14 14 14 14 14 14 14 R<br />
14 14<br />
12 12 12 12<br />
12 12 12 12<br />
32 32 32 12 12 12 12 13<br />
32 32 32 32<br />
32 12 12 12<br />
12 12 12 12<br />
12 12 13 13<br />
32 32 12 12 12 12 12 13<br />
32 32 32 12<br />
12 12 12 12<br />
32 12 12 12<br />
32 32 12 12<br />
15 15 15 14<br />
14 14 14 14<br />
14 14 14 14<br />
14<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
15<br />
32 32 32 32<br />
32 32 32 32<br />
17 16 16 16 16 16 16 16 B<br />
17 17 16 16<br />
17 17 17 16<br />
17 17 17 17<br />
32 32<br />
32 32 32 32<br />
32 32 32 32<br />
16 16 16 16<br />
17 16 16 16<br />
15 15 15 15 15 15 15 K<br />
12 12 12 12<br />
12 12 12 12<br />
13 13<br />
13 13 13 13<br />
12 13 13 13<br />
12 12 13 13<br />
12 12 12 13<br />
14 14 14 14<br />
14 14 14 14<br />
14 13 13 13<br />
13 13 13 Y<br />
13 AA<br />
13 13 13 13 AB<br />
13 13 13 13<br />
13 13 AC<br />
13 13 13 AE<br />
13 AF<br />
13 13 13 13 AG<br />
13 13 13 13<br />
14 T<br />
14 14 14 14 14 14 14 14 U<br />
14 14 14 14<br />
16 16 16 16 15 16 H<br />
15 15 15 15<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
16 A<br />
16 16 C<br />
16 16 16 E<br />
16 F<br />
16 16 16 16 G<br />
15<br />
15 15 15 15 M<br />
15 15 N<br />
14 14 14 14 14 14 V<br />
13 13 AH<br />
13 13 13 AK<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
D<br />
J<br />
L<br />
P<br />
W<br />
AD<br />
AJ<br />
Memory Groupings Pins<br />
# HP I/O<br />
# HR I/O<br />
# HP I/O − VCCAUX Group 0<br />
# HP I/O − VCCAUX Group 1<br />
# HP I/O − VCCAUX Group 2<br />
# HP I/O − VCCAUX Group 3<br />
# HP I/O − VCCAUX Group 4<br />
# HP I/O − VCCAUX Group 5<br />
# HP I/O − VCCAUX Group 6<br />
# HP I/O − VCCAUX Group 7<br />
# DQS pin<br />
# DCI pin<br />
# Memory Byte Group 0<br />
# Memory Byte Group 1<br />
# Memory Byte Group 2<br />
# Memory Byte Group 3<br />
# Bank Number<br />
ug475_c3_35_052311<br />
Figure 3-31:<br />
FFG900 Package—XC7K325T <strong>and</strong> XC7K410T Memory Groupings<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 75<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-32<br />
1 2 3 4 5<br />
A<br />
B<br />
C<br />
D<br />
E<br />
F<br />
G<br />
H<br />
J<br />
K<br />
L<br />
M<br />
N<br />
P<br />
R<br />
T<br />
U<br />
V<br />
W<br />
Y<br />
AA<br />
AB<br />
AC 34<br />
AD<br />
AE<br />
AF<br />
34<br />
AG 34<br />
AH<br />
AJ<br />
34<br />
AK 34<br />
1 2 3 4 5<br />
6<br />
0<br />
6<br />
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
17<br />
16 A<br />
17<br />
16<br />
B<br />
18<br />
16<br />
C<br />
18<br />
17<br />
16 D<br />
17<br />
16<br />
E<br />
18<br />
16<br />
F<br />
18<br />
17<br />
G<br />
17<br />
16 H<br />
18<br />
15<br />
J<br />
18<br />
15<br />
K<br />
17<br />
15 L<br />
15<br />
M<br />
15<br />
N<br />
15<br />
14 P<br />
14<br />
R<br />
0<br />
14<br />
T<br />
14<br />
U<br />
0<br />
14 V<br />
0 0<br />
14<br />
W<br />
33<br />
12<br />
Y<br />
33<br />
32<br />
13 AA<br />
32<br />
13<br />
AB<br />
33<br />
12<br />
AC<br />
33<br />
12<br />
13 AD<br />
34<br />
32<br />
13<br />
AE<br />
32<br />
12<br />
AF<br />
33<br />
12<br />
AG<br />
34<br />
32<br />
13 AH<br />
32<br />
13<br />
AJ<br />
33<br />
12<br />
AK<br />
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
Power Pins<br />
# VCCO_#<br />
VCCINT<br />
VCCAUX<br />
# VCCAUX_IO_G#<br />
VCCBRAM<br />
VCCBATT_0<br />
VCCADC_0<br />
GNDADC_0<br />
MGTVCCAUX<br />
# MGTVCCAUX_G# or MGTHVCCAUX_G#<br />
MGTAVCC<br />
# MGTAVCC_G# or MGTHAVCC_G#<br />
MGTAVTT<br />
# MGTAVTT_G# or MGTHAVTT_G#<br />
GND<br />
ug475_c3_36_052311<br />
Figure 3-32:<br />
FFG900 Package—XC7K325T <strong>and</strong> XC7K410T Power <strong>and</strong> GND Placement<br />
www.BDTIC.com/XILINX<br />
76 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Kintex-7 <strong>FPGAs</strong> Device Diagrams<br />
FFG901 Package—XC7K355T<br />
X-Ref Target - Figure 3-33<br />
1<br />
A<br />
B<br />
C<br />
D<br />
E<br />
F<br />
G<br />
H<br />
J<br />
K<br />
L<br />
M<br />
N<br />
P<br />
R<br />
T<br />
U<br />
V<br />
W<br />
Y<br />
AA<br />
AB<br />
AC<br />
AD<br />
AE<br />
AF<br />
AG<br />
AH<br />
AJ<br />
AK<br />
1<br />
2 3 4 5 6 7 8 9<br />
V<br />
V<br />
V V V<br />
E<br />
E<br />
V<br />
V<br />
E<br />
E<br />
V<br />
V<br />
E<br />
E G<br />
V<br />
V<br />
E<br />
E<br />
V<br />
V<br />
E<br />
E<br />
V<br />
V<br />
V<br />
V<br />
V<br />
E n n<br />
E n n<br />
V<br />
n<br />
V<br />
E n n V<br />
E n<br />
V n n V<br />
V<br />
V n<br />
2 3 4 5 6 7 8 9<br />
V<br />
V<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
n n n n<br />
A<br />
E<br />
n n n<br />
B<br />
n n n n<br />
C<br />
E<br />
n n n<br />
D<br />
n n n<br />
s<br />
E<br />
n n n<br />
F<br />
n n n<br />
G<br />
Y I K C n n n n<br />
s<br />
H<br />
M O n n n<br />
s<br />
J<br />
B<br />
K<br />
s<br />
s<br />
L<br />
B<br />
B<br />
M<br />
N<br />
r r s<br />
P<br />
S S<br />
U B<br />
B R<br />
S S<br />
B s<br />
T<br />
L J<br />
U<br />
B<br />
B V<br />
s<br />
s<br />
W<br />
n n<br />
s s<br />
Y<br />
n n<br />
AA<br />
P 2 n n n n n<br />
AB<br />
D 1 0 n n n n n<br />
AC<br />
n n n n n<br />
AD<br />
n n n n n n n s<br />
AE<br />
n<br />
n n n n<br />
AF<br />
n n n n n n n<br />
AG<br />
n E<br />
n n n n n n<br />
AH<br />
n n n n n n n<br />
AJ<br />
n E<br />
n n n n n n<br />
AK<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
User I/O Pins<br />
Transceiver Pins<br />
Dedicated Pins<br />
Other Pins<br />
IO_LXXY_#<br />
E<br />
MGTAVCC_G#<br />
C<br />
CCLK_0<br />
S<br />
VP_0<br />
GND<br />
s<br />
IO_XX_#<br />
V<br />
MGTAVTT_G#<br />
CFGBVS_0<br />
S<br />
VN_0<br />
VCCAUX_IO_G#<br />
Multi−Function Pins<br />
V<br />
V<br />
MGTVCCAUX_G#<br />
MGTAVTTRCAL<br />
G MGTRREF<br />
D<br />
J<br />
L<br />
DONE_0<br />
DXP_0<br />
DXN_0<br />
S<br />
S<br />
VREFP_0<br />
VREFN_0<br />
VCCAUX<br />
VCCINT<br />
VCCO_#<br />
B<br />
ADV_B<br />
VRN<br />
MGTREFCLK1/0P<br />
GNDADC_0<br />
VCCBRAM<br />
B<br />
FCS_B<br />
VRP<br />
MGTREFCLK1/0N<br />
Y<br />
INIT_B_0<br />
n<br />
NC<br />
B<br />
FOE_B<br />
VREF<br />
MGTXRXP<br />
0 M0_0<br />
B<br />
MOSI<br />
D00−D31<br />
MGTXRXN<br />
1 M1_0<br />
B<br />
FWE_B<br />
A00−A28<br />
MGTXTXP<br />
2 M2_0<br />
B<br />
DOUT_CSO_B<br />
DQS<br />
MGTXTXN<br />
P<br />
PROGRAM_B_0<br />
B<br />
CSI_B<br />
MRCC<br />
E<br />
MGTHAVCC_G#<br />
K<br />
TCK_0<br />
B<br />
PUDC_B<br />
SRCC<br />
V<br />
MGTHAVTT_G#<br />
I<br />
TDI_0<br />
U<br />
RDWR_B<br />
MGTHRXP<br />
O<br />
TDO_0<br />
r<br />
RS0−RS1<br />
MGTHRXN<br />
M<br />
TMS_0<br />
AD0P/AD0N−AD15P/AD15N<br />
MGTHTXP<br />
VCCADC_0<br />
EMCCLK<br />
MGTHTXN<br />
VCCBATT_0<br />
ug475_c3_37_090511<br />
Figure 3-33:<br />
FFG901 Package—XC7K355T <strong>Pinout</strong> Diagram<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 77<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-34<br />
A<br />
B 116 116<br />
C<br />
D 116 116<br />
E<br />
F 115 115<br />
G<br />
H 115 115<br />
J<br />
K 115 115<br />
L<br />
M<br />
N<br />
P 114 114<br />
R<br />
T 114 114<br />
U<br />
V<br />
W<br />
Y 113 113<br />
AA<br />
AB 113 113<br />
AC<br />
AD 113 113<br />
AE<br />
AF 113 113<br />
AG<br />
AH 112 112<br />
AJ<br />
1<br />
AK 112 112<br />
116 116<br />
116 116<br />
116 116<br />
116 116<br />
115 115<br />
115 115<br />
114 114<br />
113 113<br />
113 113<br />
112 112<br />
112 112<br />
112 112<br />
112 112<br />
114 114<br />
114 114 114 114<br />
114 114<br />
116 116<br />
116 116<br />
116 116<br />
116 116<br />
115 115<br />
115 115 115 115<br />
114 114<br />
114 114 114 114<br />
1<br />
2<br />
2<br />
3<br />
3<br />
4<br />
4<br />
5<br />
113 113<br />
113 113<br />
112 112<br />
112 112<br />
112 112<br />
112 112<br />
5<br />
6<br />
6<br />
7<br />
117 117<br />
117 117<br />
115 115<br />
115 115<br />
115 115<br />
113 113<br />
113 113<br />
117 117<br />
117 117 117<br />
117 117<br />
7<br />
8<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
117 117<br />
117 117<br />
117 117<br />
117 117<br />
117<br />
15 15 15 15<br />
15<br />
14 14 14 14<br />
14 14<br />
14 14 14 14<br />
14<br />
17 17 17 17 17<br />
17 17 17<br />
17 17 17 17<br />
17<br />
17 17 17<br />
15 15 15 15<br />
15 15 15 15<br />
14 14 14 14<br />
14 14 14 14<br />
14 14 14 14 14 14 13<br />
12 12<br />
12 12 12 12<br />
12<br />
12 12 12<br />
12 13 13 13<br />
12 12 13 13<br />
12 12 12 12<br />
12 12<br />
12 12 12 12<br />
12<br />
17 17 17 16<br />
17 17 17 17<br />
17 17<br />
17 17 17 17<br />
17 17<br />
17 17 17 17<br />
17 17<br />
12 12 12 12<br />
12 12 12 12<br />
12 12<br />
12 12 12 12<br />
12<br />
17 17 16 16<br />
17 17 17 17<br />
17 16 16 16<br />
17 15 15 15<br />
15 15 15 15<br />
15 15 15 15 15 15 15<br />
16 16 16 16<br />
17 17 16 16<br />
17 17 17 16<br />
14 14 14 14<br />
14 14 14 14<br />
16 16 16 16<br />
15 15 15 15<br />
15 15 15 15<br />
14 14 14 14<br />
14 14 14 14<br />
13 13 13 13<br />
12 13 13 13<br />
12 12 13 13<br />
12 12 12 13<br />
12 12 12 12<br />
13 13 13 13<br />
13 13 13 13<br />
16 16 16 16 B<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 E<br />
16 16 16 16 G<br />
16 16 16 16<br />
15 15 15 K<br />
14 15 14 R<br />
13 13 13 Y<br />
13 13 13 13 AB<br />
12 13 13 13<br />
15<br />
15 15 15 15 M<br />
15 15 15 15<br />
16 A<br />
16 16 C<br />
16 F<br />
16 16 H<br />
15 15 N<br />
14 T<br />
14 14 14 14 U<br />
14 14 V<br />
13 AA<br />
13 13 AC<br />
13 13 13 AE<br />
13 AF<br />
13 13 13 13 AG<br />
13 13 AH<br />
13 13 13 AK<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
D<br />
J<br />
L<br />
P<br />
W<br />
AD<br />
AJ<br />
ug475_c3_38_052311<br />
Figure 3-34:<br />
FFG901 Package—XC7K355T I/O Banks<br />
www.BDTIC.com/XILINX<br />
78 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Kintex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-35<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
A<br />
17 17 17 17 17<br />
16 16 16 16<br />
16<br />
A<br />
B<br />
17 17 17<br />
17 17 16 16<br />
16 16 16 16<br />
B<br />
C<br />
17 17 17 17<br />
16 16 16 16<br />
16 16<br />
C<br />
D<br />
17 17<br />
17 17 17 16<br />
16 16 16 16<br />
D<br />
E<br />
17 17 17 17<br />
17 16 16 16<br />
16 16 16<br />
E<br />
F<br />
17<br />
17 17 17 17<br />
16 16 16 16<br />
16<br />
F<br />
G<br />
17 17 17<br />
17 17 16 16<br />
16 16 16 16<br />
G<br />
H<br />
17 17 17 17<br />
16 16 16 16<br />
16 16<br />
H<br />
J<br />
17 17<br />
17 17 17 16<br />
16 16 16 16<br />
J<br />
K<br />
17 17 17 17<br />
17 15 15 15<br />
15 15 15<br />
K<br />
L<br />
17 17<br />
15 15 15 15<br />
15 15 15 15<br />
15<br />
L<br />
M<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15 M<br />
N<br />
15<br />
15 15 15 15<br />
15 15 15 15<br />
15 15<br />
N<br />
P<br />
15 15 15 15 15 15 15<br />
15 15 15 15<br />
P<br />
R<br />
14 14 14 14<br />
14 14 14 14<br />
14 15 14<br />
R<br />
T<br />
14 14<br />
14 14 14 14<br />
14 14 14 14<br />
14<br />
T<br />
U<br />
14 14 14 14<br />
14 14 14 14<br />
14 14 14 14<br />
U<br />
V<br />
14<br />
14 14 14 14<br />
14 14 14 14<br />
14 14<br />
V<br />
W<br />
14 14 14 14 14 14 13<br />
13 13 13 13<br />
W<br />
Y<br />
12 12<br />
12 13 13 13<br />
13 13 13<br />
Y<br />
AA<br />
12 12 12 12<br />
13 13 13 13<br />
13 AA<br />
AB<br />
12<br />
12 12 13 13<br />
13 13 13 13 AB<br />
AC<br />
12 12 12<br />
13 13 13 13<br />
13 13 AC<br />
AD<br />
12 12 12 12<br />
12 13 13 13<br />
AD<br />
AE<br />
12 12<br />
12 12 12 12<br />
13 13 13 AE<br />
AF<br />
12 12 12 12<br />
12 12 13 13<br />
13 AF<br />
AG<br />
12<br />
12 12 12 12<br />
13 13 13 13 AG<br />
AH<br />
12 12<br />
12 12 12 13<br />
13 13 AH<br />
AJ<br />
12 12 12 12<br />
12 13 13 13<br />
AJ<br />
AK<br />
12<br />
12 12 12 12<br />
13 13 13 AK<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
Memory Groupings Pins<br />
# HP I/O<br />
# HR I/O<br />
# HP I/O − VCCAUX Group 0<br />
# HP I/O − VCCAUX Group 1<br />
# HP I/O − VCCAUX Group 2<br />
# HP I/O − VCCAUX Group 3<br />
# HP I/O − VCCAUX Group 4<br />
# HP I/O − VCCAUX Group 5<br />
# HP I/O − VCCAUX Group 6<br />
# HP I/O − VCCAUX Group 7<br />
# DQS pin<br />
# DCI pin<br />
# Memory Byte Group 0<br />
# Memory Byte Group 1<br />
# Memory Byte Group 2<br />
# Memory Byte Group 3<br />
# Bank Number<br />
ug475_c3_39_052311<br />
Figure 3-35:<br />
FFG901 Package—XC7K355T Memory Groupings<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 79<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-36<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
A<br />
17<br />
16<br />
A<br />
B<br />
18<br />
16<br />
B<br />
C<br />
17<br />
C<br />
D<br />
17<br />
16<br />
D<br />
E<br />
18<br />
16<br />
E<br />
F<br />
18<br />
16<br />
F<br />
G<br />
17<br />
G<br />
H<br />
17<br />
16<br />
H<br />
J<br />
0<br />
18<br />
16<br />
J<br />
K<br />
0<br />
17<br />
K<br />
L<br />
15 15<br />
L<br />
M<br />
15<br />
M<br />
N<br />
15<br />
N<br />
P<br />
15 15<br />
P<br />
R<br />
14 14<br />
R<br />
T<br />
14<br />
T<br />
U<br />
14<br />
U<br />
V<br />
14 14<br />
V<br />
W<br />
13<br />
W<br />
Y<br />
12<br />
Y<br />
AA<br />
11<br />
13<br />
AA<br />
AB<br />
11<br />
13<br />
AB<br />
AC<br />
12<br />
AC<br />
AD<br />
12<br />
13 AD<br />
AE<br />
11<br />
13<br />
AE<br />
AF<br />
11<br />
12<br />
AF<br />
AG<br />
12<br />
AG<br />
AH<br />
11<br />
13<br />
AH<br />
AJ<br />
11<br />
12<br />
AJ<br />
AK<br />
12<br />
AK<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
Power Pins<br />
# VCCO_#<br />
VCCINT<br />
VCCAUX<br />
# VCCAUX_IO_G#<br />
VCCBRAM<br />
VCCBATT_0<br />
VCCADC_0<br />
GNDADC_0<br />
MGTVCCAUX<br />
# MGTVCCAUX_G# or MGTHVCCAUX_G#<br />
MGTAVCC<br />
# MGTAVCC_G# or MGTHAVCC_G#<br />
MGTAVTT<br />
# MGTAVTT_G# or MGTHAVTT_G#<br />
GND<br />
ug475_c3_40_052311<br />
Figure 3-36:<br />
FFG901 Package—XC7K355T Power <strong>and</strong> GND Placement<br />
www.BDTIC.com/XILINX<br />
80 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Kintex-7 <strong>FPGAs</strong> Device Diagrams<br />
FFG901 Package—XC7K420T<br />
X-Ref Target - Figure 3-37<br />
1<br />
A<br />
B<br />
C<br />
D<br />
E<br />
F<br />
G<br />
H<br />
J<br />
K<br />
L<br />
M<br />
N<br />
P<br />
R<br />
T<br />
U<br />
V<br />
W<br />
Y<br />
AA<br />
AB<br />
AC<br />
AD<br />
AE<br />
AF<br />
AG<br />
AH<br />
AJ<br />
AK<br />
1<br />
2 3 4 5 6 7 8 9<br />
V<br />
V<br />
V V V<br />
E<br />
E<br />
V<br />
V<br />
E<br />
E<br />
V<br />
V<br />
E<br />
E G<br />
V<br />
V<br />
E<br />
E<br />
V<br />
V<br />
E<br />
E<br />
V<br />
V<br />
E<br />
E<br />
V<br />
V<br />
E<br />
V<br />
E<br />
V<br />
V<br />
V<br />
V<br />
2 3 4 5 6 7 8 9<br />
V<br />
V<br />
V<br />
V<br />
V<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
Y<br />
D<br />
E<br />
E<br />
I<br />
M<br />
P<br />
E<br />
E<br />
K<br />
S<br />
S<br />
L<br />
2<br />
C<br />
O<br />
S<br />
S<br />
J<br />
n n n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n n n<br />
1 0<br />
s<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
s<br />
B<br />
B<br />
r r s<br />
s<br />
U<br />
B<br />
s<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
s<br />
B<br />
s<br />
s<br />
s<br />
s<br />
s<br />
s<br />
B<br />
s<br />
s<br />
B<br />
B<br />
B<br />
A<br />
B<br />
C<br />
D<br />
E<br />
F<br />
G<br />
H<br />
J<br />
K<br />
L<br />
M<br />
N<br />
P<br />
R<br />
T<br />
U<br />
V<br />
W<br />
Y<br />
AA<br />
AB<br />
AC<br />
AD<br />
AE<br />
AF<br />
AG<br />
AH<br />
AJ<br />
AK<br />
User I/O Pins<br />
Transceiver Pins<br />
Dedicated Pins<br />
Other Pins<br />
IO_LXXY_#<br />
E<br />
MGTAVCC_G#<br />
C<br />
CCLK_0<br />
S<br />
VP_0<br />
GND<br />
s<br />
IO_XX_#<br />
V<br />
MGTAVTT_G#<br />
CFGBVS_0<br />
S<br />
VN_0<br />
VCCAUX_IO_G#<br />
Multi−Function Pins<br />
V<br />
V<br />
MGTVCCAUX_G#<br />
MGTAVTTRCAL<br />
G MGTRREF<br />
D<br />
J<br />
L<br />
DONE_0<br />
DXP_0<br />
DXN_0<br />
S<br />
S<br />
VREFP_0<br />
VREFN_0<br />
VCCAUX<br />
VCCINT<br />
VCCO_#<br />
B<br />
ADV_B<br />
VRN<br />
MGTREFCLK1/0P<br />
GNDADC_0<br />
VCCBRAM<br />
B<br />
FCS_B<br />
VRP<br />
MGTREFCLK1/0N<br />
Y<br />
INIT_B_0<br />
n<br />
NC<br />
B<br />
FOE_B<br />
VREF<br />
MGTXRXP<br />
0 M0_0<br />
B<br />
MOSI<br />
D00−D31<br />
MGTXRXN<br />
1 M1_0<br />
B<br />
FWE_B<br />
A00−A28<br />
MGTXTXP<br />
2 M2_0<br />
B<br />
DOUT_CSO_B<br />
DQS<br />
MGTXTXN<br />
P<br />
PROGRAM_B_0<br />
B<br />
CSI_B<br />
MRCC<br />
E<br />
MGTHAVCC_G#<br />
K<br />
TCK_0<br />
B<br />
PUDC_B<br />
SRCC<br />
V<br />
MGTHAVTT_G#<br />
I<br />
TDI_0<br />
U<br />
RDWR_B<br />
MGTHRXP<br />
O<br />
TDO_0<br />
r<br />
RS0−RS1<br />
MGTHRXN<br />
M<br />
TMS_0<br />
AD0P/AD0N−AD15P/AD15N<br />
MGTHTXP<br />
VCCADC_0<br />
EMCCLK<br />
MGTHTXN<br />
VCCBATT_0<br />
ug475_c3_41_090511<br />
Figure 3-37:<br />
FFG901 Package—XC7K420T <strong>Pinout</strong> Diagram<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 81<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-38<br />
A<br />
B 116 116<br />
C<br />
D 116 116<br />
E<br />
F 115 115<br />
G<br />
H 115 115<br />
J<br />
K 115 115<br />
L<br />
M<br />
N<br />
P 114 114<br />
R<br />
T 114 114<br />
U<br />
V<br />
W<br />
Y 113 113<br />
AA<br />
AB 113 113<br />
AC<br />
AD 113 113<br />
AE<br />
AF 113 113<br />
AG<br />
AH 112 112<br />
AJ<br />
1<br />
AK 112 112<br />
115 115<br />
115 115<br />
114 114<br />
113 113<br />
113 113<br />
112 112<br />
112 112<br />
112 112<br />
112 112<br />
114 114<br />
114 114 114 114<br />
114 114<br />
115 115<br />
115 115 115 115<br />
114 114<br />
114 114 114 114<br />
1<br />
2<br />
2<br />
3<br />
116 116<br />
116 116<br />
116 116<br />
116 116<br />
3<br />
4<br />
4<br />
5<br />
116 116<br />
116 116<br />
116 116<br />
116 116<br />
113 113<br />
113 113<br />
112 112<br />
112 112<br />
112 112<br />
112 112<br />
5<br />
6<br />
6<br />
7<br />
117 117<br />
117 117<br />
115 115<br />
115 115<br />
115 115<br />
113 113<br />
113 113<br />
111 111<br />
111 111<br />
111 111<br />
111 111<br />
117 117<br />
117 117 117<br />
117 117<br />
7<br />
8<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
117 117<br />
117 117<br />
111 111<br />
111 111<br />
111 111<br />
117 117<br />
117 117<br />
117<br />
111 111<br />
111 111<br />
111 111<br />
11 11<br />
11 11 11 11<br />
11<br />
11 11 11 11<br />
11 11<br />
11 11 11 11<br />
11<br />
11 11 11<br />
15 15 15 15<br />
15<br />
14 14 14 14<br />
14 14<br />
14 14 14 14<br />
14<br />
17 17 17 17 17<br />
17 17 17<br />
17 17 17 17<br />
17<br />
17 17 17<br />
14 14 14 14 14 14 13<br />
11 11 12 12<br />
11 11<br />
11 11 11 12<br />
11 11 11 11<br />
11 12 12 12<br />
11 11 11 11 11 12 12<br />
11 11 11 12<br />
11 11 11 11<br />
15 15 15 15<br />
15 15 15 15<br />
14 14 14 14<br />
14 14 14 14<br />
12 12 12 12<br />
11 11 12 12<br />
11 11 11 12<br />
17 17 16 16<br />
17 17 17 16<br />
17 17 17 17<br />
17 17<br />
17 17 17 17<br />
17 17<br />
17 17 17 17<br />
17 17<br />
17 17 17 17<br />
12 13 13 13<br />
12 12 13 13<br />
12 12 12 12<br />
12 12 12 12<br />
17 16 16 16<br />
17 15 15 15<br />
15 15 15 15<br />
15 15 15 15 15 15 15<br />
14 14 14 14<br />
14 14 14 14<br />
12 12 12 12<br />
12 12 12 12<br />
12 12 12 12<br />
16 16 16 16<br />
16 16 16 16<br />
17 17 16 16<br />
17 17 17 16<br />
15 15 15 15<br />
15 15 15 15<br />
14 14 14 14<br />
14 14 14 14<br />
13 13 13 13<br />
12 13 13 13<br />
12 12 13 13<br />
12 12 12 13<br />
12 12 12 12<br />
13 13 13 13<br />
13 13 13 13<br />
16 16 16 16 B<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 E<br />
16 16 16 16 G<br />
16 16 16 16<br />
15 15 15 K<br />
14 15 14 R<br />
13 13 13 Y<br />
13 13 13 13 AB<br />
12 13 13 13<br />
15<br />
15 15 15 15 M<br />
15 15 15 15<br />
16 A<br />
16 16 C<br />
16 F<br />
16 16 H<br />
15 15 N<br />
14 T<br />
14 14 14 14 U<br />
14 14 V<br />
13 AA<br />
13 13 AC<br />
13 13 13 AE<br />
13 AF<br />
13 13 13 13 AG<br />
13 13 AH<br />
13 13 13 AK<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
D<br />
J<br />
L<br />
P<br />
W<br />
AD<br />
AJ<br />
ug475_c3_42_052311<br />
Figure 3-38:<br />
FFG901 Package—XC7K420T I/O Banks<br />
www.BDTIC.com/XILINX<br />
82 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Kintex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-39<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
A<br />
17 17 17 17 17<br />
16 16 16 16<br />
16<br />
A<br />
B<br />
17 17 17<br />
17 17 16 16<br />
16 16 16 16<br />
B<br />
C<br />
17 17 17 17<br />
16 16 16 16<br />
16 16<br />
C<br />
D<br />
17 17<br />
17 17 17 16<br />
16 16 16 16<br />
D<br />
E<br />
17 17 17 17<br />
17 16 16 16<br />
16 16 16<br />
E<br />
F<br />
17<br />
17 17 17 17<br />
16 16 16 16<br />
16<br />
F<br />
G<br />
17 17 17<br />
17 17 16 16<br />
16 16 16 16<br />
G<br />
H<br />
17 17 17 17<br />
16 16 16 16<br />
16 16<br />
H<br />
J<br />
17 17<br />
17 17 17 16<br />
16 16 16 16<br />
J<br />
K<br />
17 17 17 17<br />
17 15 15 15<br />
15 15 15<br />
K<br />
L<br />
17 17<br />
15 15 15 15<br />
15 15 15 15<br />
15<br />
L<br />
M<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15 M<br />
N<br />
15<br />
15 15 15 15<br />
15 15 15 15<br />
15 15<br />
N<br />
P<br />
15 15 15 15 15 15 15<br />
15 15 15 15<br />
P<br />
R<br />
14 14 14 14<br />
14 14 14 14<br />
14 15 14<br />
R<br />
T<br />
14 14<br />
14 14 14 14<br />
14 14 14 14<br />
14<br />
T<br />
U<br />
14 14 14 14<br />
14 14 14 14<br />
14 14 14 14<br />
U<br />
V<br />
14<br />
14 14 14 14<br />
14 14 14 14<br />
14 14<br />
V<br />
W<br />
14 14 14 14 14 14 13<br />
13 13 13 13<br />
W<br />
Y<br />
11 11 12 12<br />
12 13 13 13<br />
13 13 13<br />
Y<br />
AA<br />
11 11<br />
12 12 12 12<br />
13 13 13 13<br />
13 AA<br />
AB<br />
11 11<br />
11 11 11 12<br />
12 12 13 13<br />
13 13 13 13 AB<br />
AC<br />
11 11 11 11<br />
11 12 12 12<br />
13 13 13 13<br />
13 13 AC<br />
AD<br />
11<br />
11 11 11 11<br />
12 12 12 12<br />
12 13 13 13<br />
AD<br />
AE<br />
11 11 11 11 11 12 12<br />
12 12 12 12<br />
13 13 13 AE<br />
AF<br />
11 11 11 11<br />
12 12 12 12<br />
12 12 13 13<br />
13 AF<br />
AG<br />
11 11<br />
11 11 11 12<br />
12 12 12 12<br />
13 13 13 13 AG<br />
AH<br />
11 11 11 11<br />
11 11 12 12<br />
12 12 12 13<br />
13 13 AH<br />
AJ<br />
11<br />
11 11 11 11<br />
12 12 12 12<br />
12 13 13 13<br />
AJ<br />
AK<br />
11 11 11<br />
11 11 11 12<br />
12 12 12 12<br />
13 13 13 AK<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
Memory Groupings Pins<br />
# HP I/O<br />
# HR I/O<br />
# HP I/O − VCCAUX Group 0<br />
# HP I/O − VCCAUX Group 1<br />
# HP I/O − VCCAUX Group 2<br />
# HP I/O − VCCAUX Group 3<br />
# HP I/O − VCCAUX Group 4<br />
# HP I/O − VCCAUX Group 5<br />
# HP I/O − VCCAUX Group 6<br />
# HP I/O − VCCAUX Group 7<br />
# DQS pin<br />
# DCI pin<br />
# Memory Byte Group 0<br />
# Memory Byte Group 1<br />
# Memory Byte Group 2<br />
# Memory Byte Group 3<br />
# Bank Number<br />
ug475_c3_43_052311<br />
Figure 3-39:<br />
FFG901 Package—XC7K420T Memory Groupings<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 83<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-40<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
A<br />
17<br />
16<br />
A<br />
B<br />
18<br />
16<br />
B<br />
C<br />
17<br />
C<br />
D<br />
17<br />
16<br />
D<br />
E<br />
18<br />
16<br />
E<br />
F<br />
18<br />
16<br />
F<br />
G<br />
17<br />
G<br />
H<br />
17<br />
16<br />
H<br />
J<br />
0<br />
18<br />
16<br />
J<br />
K<br />
0<br />
17<br />
K<br />
L<br />
15 15<br />
L<br />
M<br />
15<br />
M<br />
N<br />
15<br />
N<br />
P<br />
15 15<br />
P<br />
R<br />
14 14<br />
R<br />
T<br />
14<br />
T<br />
U<br />
14<br />
U<br />
V<br />
14 14<br />
V<br />
W<br />
13<br />
W<br />
Y<br />
12<br />
Y<br />
AA<br />
11<br />
13<br />
AA<br />
AB<br />
11<br />
13<br />
AB<br />
AC<br />
12<br />
AC<br />
AD<br />
12<br />
13 AD<br />
AE<br />
11<br />
13<br />
AE<br />
AF<br />
11<br />
12<br />
AF<br />
AG<br />
12<br />
AG<br />
AH<br />
11<br />
13<br />
AH<br />
AJ<br />
11<br />
12<br />
AJ<br />
AK<br />
12<br />
AK<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
Power Pins<br />
# VCCO_#<br />
VCCINT<br />
VCCAUX<br />
# VCCAUX_IO_G#<br />
VCCBRAM<br />
VCCBATT_0<br />
VCCADC_0<br />
GNDADC_0<br />
MGTVCCAUX<br />
# MGTVCCAUX_G# or MGTHVCCAUX_G#<br />
MGTAVCC<br />
# MGTAVCC_G# or MGTHAVCC_G#<br />
MGTAVTT<br />
# MGTAVTT_G# or MGTHAVTT_G#<br />
GND<br />
ug475_c3_44_052311<br />
Figure 3-40:<br />
FFG901 Package—XC7K420T Power <strong>and</strong> GND Placement<br />
www.BDTIC.com/XILINX<br />
84 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Kintex-7 <strong>FPGAs</strong> Device Diagrams<br />
FFG901 Package—XC7K480T<br />
X-Ref Target - Figure 3-41<br />
1<br />
A<br />
B<br />
C<br />
D<br />
E<br />
F<br />
G<br />
H<br />
J<br />
K<br />
L<br />
M<br />
N<br />
P<br />
R<br />
T<br />
U<br />
V<br />
W<br />
Y<br />
AA<br />
AB<br />
AC<br />
AD<br />
AE<br />
AF<br />
AG<br />
AH<br />
AJ<br />
AK<br />
1<br />
2 3 4 5 6 7 8 9<br />
V<br />
V<br />
V V V<br />
E<br />
E<br />
V<br />
V<br />
E<br />
E<br />
V<br />
V<br />
E<br />
E G<br />
V<br />
V<br />
E<br />
E<br />
V<br />
V<br />
E<br />
E<br />
V<br />
V<br />
E<br />
E<br />
V<br />
V<br />
E<br />
V<br />
E<br />
V<br />
V<br />
V<br />
V<br />
2 3 4 5 6 7 8 9<br />
V<br />
V<br />
V<br />
V<br />
V<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
Y<br />
D<br />
E<br />
E<br />
I<br />
M<br />
P<br />
E<br />
E<br />
K<br />
S<br />
S<br />
L<br />
2<br />
C<br />
O<br />
S<br />
S<br />
J<br />
1 0<br />
s<br />
s<br />
B<br />
B<br />
r r s<br />
s<br />
U<br />
B<br />
s<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
s<br />
B<br />
s<br />
s<br />
s<br />
s<br />
s<br />
s<br />
B<br />
s<br />
s<br />
B<br />
B<br />
B<br />
A<br />
B<br />
C<br />
D<br />
E<br />
F<br />
G<br />
H<br />
J<br />
K<br />
L<br />
M<br />
N<br />
P<br />
R<br />
T<br />
U<br />
V<br />
W<br />
Y<br />
AA<br />
AB<br />
AC<br />
AD<br />
AE<br />
AF<br />
AG<br />
AH<br />
AJ<br />
AK<br />
User I/O Pins<br />
Transceiver Pins<br />
Dedicated Pins<br />
Other Pins<br />
IO_LXXY_#<br />
E<br />
MGTAVCC_G#<br />
C<br />
CCLK_0<br />
S<br />
VP_0<br />
GND<br />
s<br />
IO_XX_#<br />
V<br />
MGTAVTT_G#<br />
CFGBVS_0<br />
S<br />
VN_0<br />
VCCAUX_IO_G#<br />
Multi−Function Pins<br />
V<br />
V<br />
MGTVCCAUX_G#<br />
MGTAVTTRCAL<br />
G MGTRREF<br />
D<br />
J<br />
L<br />
DONE_0<br />
DXP_0<br />
DXN_0<br />
S<br />
S<br />
VREFP_0<br />
VREFN_0<br />
VCCAUX<br />
VCCINT<br />
VCCO_#<br />
B<br />
ADV_B<br />
VRN<br />
MGTREFCLK1/0P<br />
GNDADC_0<br />
VCCBRAM<br />
B<br />
FCS_B<br />
VRP<br />
MGTREFCLK1/0N<br />
Y<br />
INIT_B_0<br />
n<br />
NC<br />
B<br />
FOE_B<br />
VREF<br />
MGTXRXP<br />
0 M0_0<br />
B<br />
MOSI<br />
D00−D31<br />
MGTXRXN<br />
1 M1_0<br />
B<br />
FWE_B<br />
A00−A28<br />
MGTXTXP<br />
2 M2_0<br />
B<br />
DOUT_CSO_B<br />
DQS<br />
MGTXTXN<br />
P<br />
PROGRAM_B_0<br />
B<br />
CSI_B<br />
MRCC<br />
E<br />
MGTHAVCC_G#<br />
K<br />
TCK_0<br />
B<br />
PUDC_B<br />
SRCC<br />
V<br />
MGTHAVTT_G#<br />
I<br />
TDI_0<br />
U<br />
RDWR_B<br />
MGTHRXP<br />
O<br />
TDO_0<br />
r<br />
RS0−RS1<br />
MGTHRXN<br />
M<br />
TMS_0<br />
AD0P/AD0N−AD15P/AD15N<br />
MGTHTXP<br />
VCCADC_0<br />
EMCCLK<br />
MGTHTXN<br />
VCCBATT_0<br />
ug475_c3_45_090511<br />
Figure 3-41:<br />
FFG901 Package—XC7K480T <strong>Pinout</strong> Diagram<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 85<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-42<br />
A<br />
B 116 116<br />
C<br />
D 116 116<br />
E<br />
F 115 115<br />
G<br />
H 115 115<br />
J<br />
K 115 115<br />
L<br />
M<br />
N<br />
P 114 114<br />
R<br />
T 114 114<br />
U<br />
V<br />
W<br />
Y 113 113<br />
AA<br />
AB 113 113<br />
AC<br />
AD 113 113<br />
AE<br />
AF 113 113<br />
AG<br />
AH 112 112<br />
AJ<br />
1<br />
AK 112 112<br />
115 115<br />
115 115<br />
114 114<br />
113 113<br />
113 113<br />
112 112<br />
112 112<br />
112 112<br />
112 112<br />
114 114<br />
114 114 114 114<br />
114 114<br />
115 115<br />
115 115 115 115<br />
114 114<br />
114 114 114 114<br />
1<br />
2<br />
2<br />
3<br />
116 116<br />
116 116<br />
116 116<br />
116 116<br />
3<br />
4<br />
4<br />
5<br />
116 116<br />
116 116<br />
116 116<br />
116 116<br />
113 113<br />
113 113<br />
112 112<br />
112 112<br />
112 112<br />
112 112<br />
5<br />
6<br />
6<br />
7<br />
117 117<br />
117 117<br />
115 115<br />
115 115<br />
115 115<br />
113 113<br />
113 113<br />
111 111<br />
111 111<br />
111 111<br />
111 111<br />
117 117<br />
117 117 117<br />
117 117<br />
7<br />
8<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
117 117<br />
117 117<br />
111 111<br />
111 111<br />
111 111<br />
117 117<br />
117 117<br />
117<br />
111 111<br />
111 111<br />
111 111<br />
18 18 18 18 17 17 17 17 17<br />
18 18<br />
18 18 18 18<br />
18<br />
18 18 18<br />
18 18 18 17 17 17<br />
18<br />
11 11<br />
11 11 11 11<br />
11<br />
11 11 11 11<br />
11 11<br />
11 11 11 11<br />
11<br />
18 18 18 17<br />
11 11 11<br />
18 17 17 17<br />
18 18 17 17<br />
18 18 18 18<br />
18 18 17 17<br />
15 15 15 15<br />
15<br />
14 14 14 14<br />
14 14<br />
14 14 14 14<br />
14<br />
17 17 17 17<br />
14 14 14 14 14 14 13<br />
11 11 12 12<br />
11 11<br />
11 11 11 12<br />
11 11 11 11<br />
11 12 12 12<br />
11 11 11 11 11 12 12<br />
11 11 11 12<br />
11 11 11 11<br />
15 15 15 15<br />
15 15 15 15<br />
14 14 14 14<br />
14 14 14 14<br />
12 12 12 12<br />
11 11 12 12<br />
11 11 11 12<br />
17 17 16 16<br />
17 17 17 16<br />
17 17 17 17<br />
17 17 17 17<br />
17 17<br />
17 17 17 17<br />
17 17 17 17<br />
12 13 13 13<br />
12 12 13 13<br />
12 12 12 12<br />
12 12 12 12<br />
17 16 16 16<br />
17 15 15 15<br />
15 15 15 15<br />
15 15 15 15 15 15 15<br />
14 14 14 14<br />
14 14 14 14<br />
12 12 12 12<br />
12 12 12 12<br />
12 12 12 12<br />
16 16 16 16<br />
16 16 16 16<br />
17 17 16 16<br />
17 17 17 16<br />
15 15 15 15<br />
15 15 15 15<br />
14 14 14 14<br />
14 14 14 14<br />
13 13 13 13<br />
12 13 13 13<br />
12 12 13 13<br />
12 12 12 13<br />
12 12 12 12<br />
13 13 13 13<br />
13 13 13 13<br />
16 16 16 16 B<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 E<br />
16 16 16 16 G<br />
16 16 16 16<br />
15 15 15 K<br />
14 15 14 R<br />
13 13 13 Y<br />
13 13 13 13 AB<br />
12 13 13 13<br />
15<br />
15 15 15 15 M<br />
15 15 15 15<br />
16 A<br />
16 16 C<br />
16 F<br />
16 16 H<br />
15 15 N<br />
14 T<br />
14 14 14 14 U<br />
14 14 V<br />
13 AA<br />
13 13 AC<br />
13 13 13 AE<br />
13 AF<br />
13 13 13 13 AG<br />
13 13 AH<br />
13 13 13 AK<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
D<br />
J<br />
L<br />
P<br />
W<br />
AD<br />
AJ<br />
ug475_c3_46_052311<br />
Figure 3-42:<br />
FFG901 Package—XC7K480T I/O Banks<br />
www.BDTIC.com/XILINX<br />
86 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Kintex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-43<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
A<br />
18 18 18 18 17 17 17 17 17<br />
16 16 16 16<br />
16<br />
A<br />
B<br />
18 18<br />
18 17 17 17<br />
17 17 16 16<br />
16 16 16 16<br />
B<br />
C<br />
18 18 18 18<br />
17 17 17 17<br />
16 16 16 16<br />
16 16<br />
C<br />
D<br />
18<br />
18 18 17 17<br />
17 17 17 16<br />
16 16 16 16<br />
D<br />
E<br />
18 18 18<br />
17 17 17 17<br />
17 16 16 16<br />
16 16 16<br />
E<br />
F<br />
18 18 18 17<br />
17 17 17 17<br />
16 16 16 16<br />
16<br />
F<br />
G<br />
18 18 18 17 17 17<br />
17 17 16 16<br />
16 16 16 16<br />
G<br />
H<br />
18 18 18 18<br />
17 17 17 17<br />
16 16 16 16<br />
16 16<br />
H<br />
J<br />
18<br />
18 18 17 17<br />
17 17 17 16<br />
16 16 16 16<br />
J<br />
K<br />
17 17 17 17<br />
17 15 15 15<br />
15 15 15<br />
K<br />
L<br />
17 17<br />
15 15 15 15<br />
15 15 15 15<br />
15<br />
L<br />
M<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15 M<br />
N<br />
15<br />
15 15 15 15<br />
15 15 15 15<br />
15 15<br />
N<br />
P<br />
15 15 15 15 15 15 15<br />
15 15 15 15<br />
P<br />
R<br />
14 14 14 14<br />
14 14 14 14<br />
14 15 14<br />
R<br />
T<br />
14 14<br />
14 14 14 14<br />
14 14 14 14<br />
14<br />
T<br />
U<br />
14 14 14 14<br />
14 14 14 14<br />
14 14 14 14<br />
U<br />
V<br />
14<br />
14 14 14 14<br />
14 14 14 14<br />
14 14<br />
V<br />
W<br />
14 14 14 14 14 14 13<br />
13 13 13 13<br />
W<br />
Y<br />
11 11 12 12<br />
12 13 13 13<br />
13 13 13<br />
Y<br />
AA<br />
11 11<br />
12 12 12 12<br />
13 13 13 13<br />
13 AA<br />
AB<br />
11 11<br />
11 11 11 12<br />
12 12 13 13<br />
13 13 13 13 AB<br />
AC<br />
11 11 11 11<br />
11 12 12 12<br />
13 13 13 13<br />
13 13 AC<br />
AD<br />
11<br />
11 11 11 11<br />
12 12 12 12<br />
12 13 13 13<br />
AD<br />
AE<br />
11 11 11 11 11 12 12<br />
12 12 12 12<br />
13 13 13 AE<br />
AF<br />
11 11 11 11<br />
12 12 12 12<br />
12 12 13 13<br />
13 AF<br />
AG<br />
11 11<br />
11 11 11 12<br />
12 12 12 12<br />
13 13 13 13 AG<br />
AH<br />
11 11 11 11<br />
11 11 12 12<br />
12 12 12 13<br />
13 13 AH<br />
AJ<br />
11<br />
11 11 11 11<br />
12 12 12 12<br />
12 13 13 13<br />
AJ<br />
AK<br />
11 11 11<br />
11 11 11 12<br />
12 12 12 12<br />
13 13 13 AK<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
Memory Groupings Pins<br />
# HP I/O<br />
# HR I/O<br />
# HP I/O − VCCAUX Group 0<br />
# HP I/O − VCCAUX Group 1<br />
# HP I/O − VCCAUX Group 2<br />
# HP I/O − VCCAUX Group 3<br />
# HP I/O − VCCAUX Group 4<br />
# HP I/O − VCCAUX Group 5<br />
# HP I/O − VCCAUX Group 6<br />
# HP I/O − VCCAUX Group 7<br />
# DQS pin<br />
# DCI pin<br />
# Memory Byte Group 0<br />
# Memory Byte Group 1<br />
# Memory Byte Group 2<br />
# Memory Byte Group 3<br />
# Bank Number<br />
ug475_c3_47_052311<br />
Figure 3-43:<br />
FFG901 Package—XC7K480T Memory Groupings<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 87<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-44<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
A<br />
17<br />
16<br />
A<br />
B<br />
18<br />
16<br />
B<br />
C<br />
17<br />
C<br />
D<br />
17<br />
16<br />
D<br />
E<br />
18<br />
16<br />
E<br />
F<br />
18<br />
16<br />
F<br />
G<br />
17<br />
G<br />
H<br />
17<br />
16<br />
H<br />
J<br />
0<br />
18<br />
16<br />
J<br />
K<br />
0<br />
17<br />
K<br />
L<br />
15 15<br />
L<br />
M<br />
15<br />
M<br />
N<br />
15<br />
N<br />
P<br />
15 15<br />
P<br />
R<br />
14 14<br />
R<br />
T<br />
14<br />
T<br />
U<br />
14<br />
U<br />
V<br />
14 14<br />
V<br />
W<br />
13<br />
W<br />
Y<br />
12<br />
Y<br />
AA<br />
11<br />
13<br />
AA<br />
AB<br />
11<br />
13<br />
AB<br />
AC<br />
12<br />
AC<br />
AD<br />
12<br />
13 AD<br />
AE<br />
11<br />
13<br />
AE<br />
AF<br />
11<br />
12<br />
AF<br />
AG<br />
12<br />
AG<br />
AH<br />
11<br />
13<br />
AH<br />
AJ<br />
11<br />
12<br />
AJ<br />
AK<br />
12<br />
AK<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30<br />
Power Pins<br />
# VCCO_#<br />
VCCINT<br />
VCCAUX<br />
# VCCAUX_IO_G#<br />
VCCBRAM<br />
VCCBATT_0<br />
VCCADC_0<br />
GNDADC_0<br />
MGTVCCAUX<br />
# MGTVCCAUX_G# or MGTHVCCAUX_G#<br />
MGTAVCC<br />
# MGTAVCC_G# or MGTHAVCC_G#<br />
MGTAVTT<br />
# MGTAVTT_G# or MGTHAVTT_G#<br />
GND<br />
ug475_c3_48_052311<br />
Figure 3-44:<br />
FFG901 Package—XC7K480T Power <strong>and</strong> GND Placement<br />
www.BDTIC.com/XILINX<br />
88 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 89<br />
<strong>UG475</strong> (v1.4) October 17, 2011<br />
Kintex-7 <strong>FPGAs</strong> Device Diagrams<br />
FFG1156 Package—XC7K420T<br />
X-Ref Target - Figure 3-45<br />
Figure 3-45:<br />
FFG1156 Package—XC7K420T <strong>Pinout</strong> Diagram<br />
ug475_c3_49_090511<br />
User I/O Pins<br />
IO_LXXY_#<br />
s<br />
IO_XX_#<br />
Multi−Function Pins<br />
B<br />
ADV_B<br />
B<br />
FCS_B<br />
B<br />
FOE_B<br />
B<br />
MOSI<br />
B<br />
FWE_B<br />
B<br />
DOUT_CSO_B<br />
B<br />
CSI_B<br />
B<br />
PUDC_B<br />
U<br />
RDWR_B<br />
r<br />
RS0−RS1<br />
AD0P/AD0N−AD15P/AD15N<br />
EMCCLK<br />
VRN<br />
VRP<br />
VREF<br />
D00−D31<br />
A00−A28<br />
DQS<br />
MRCC<br />
SRCC<br />
Transceiver Pins<br />
E<br />
MGTAVCC_G#<br />
V<br />
MGTAVTT_G#<br />
V<br />
MGTVCCAUX_G#<br />
V<br />
MGTAVTTRCAL<br />
G<br />
MGTRREF<br />
MGTREFCLK1/0P<br />
MGTREFCLK1/0N<br />
MGTXRXP<br />
MGTXRXN<br />
MGTXTXP<br />
MGTXTXN<br />
E<br />
MGTHAVCC_G#<br />
V<br />
MGTHAVTT_G#<br />
MGTHRXP<br />
MGTHRXN<br />
MGTHTXP<br />
MGTHTXN<br />
Dedicated Pins<br />
C<br />
CCLK_0<br />
CFGBVS_0<br />
D<br />
DONE_0<br />
J<br />
DXP_0<br />
L<br />
DXN_0<br />
GNDADC_0<br />
Y<br />
INIT_B_0<br />
0 M0_0<br />
1 M1_0<br />
2 M2_0<br />
P<br />
PROGRAM_B_0<br />
K<br />
TCK_0<br />
I<br />
TDI_0<br />
O<br />
TDO_0<br />
M<br />
TMS_0<br />
VCCADC_0<br />
VCCBATT_0<br />
S<br />
VP_0<br />
S<br />
VN_0<br />
S<br />
VREFP_0<br />
S<br />
VREFN_0<br />
Other Pins<br />
GND<br />
VCCAUX_IO_G#<br />
VCCAUX<br />
VCCINT<br />
VCCO_#<br />
VCCBRAM<br />
n<br />
NC<br />
L<br />
J<br />
S<br />
S<br />
S<br />
S<br />
C<br />
K<br />
M<br />
O<br />
I<br />
Y<br />
P<br />
D<br />
2 0<br />
1<br />
s<br />
s<br />
s<br />
s<br />
s<br />
s<br />
s<br />
B<br />
B<br />
B<br />
U<br />
B<br />
B<br />
s<br />
s<br />
B<br />
B<br />
B<br />
r<br />
r<br />
s<br />
s<br />
s<br />
s<br />
s<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n n n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
V<br />
G<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
V<br />
V<br />
V<br />
V<br />
V V V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V V V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
1<br />
1<br />
2<br />
2<br />
3<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
6<br />
7<br />
7<br />
8<br />
8<br />
9<br />
9<br />
10<br />
10<br />
11<br />
11<br />
12<br />
12<br />
13<br />
13<br />
14<br />
14<br />
15<br />
15<br />
16<br />
16<br />
17<br />
17<br />
18<br />
18<br />
19<br />
19<br />
20<br />
20<br />
21<br />
21<br />
22<br />
22<br />
23<br />
23<br />
24<br />
24<br />
25<br />
25<br />
26<br />
26<br />
27<br />
27<br />
28<br />
28<br />
29<br />
29<br />
30<br />
30<br />
31<br />
31<br />
32<br />
32<br />
33<br />
33<br />
34<br />
34<br />
A<br />
A<br />
B<br />
B<br />
C<br />
C<br />
D<br />
D<br />
E<br />
E<br />
F<br />
F<br />
G<br />
G<br />
H<br />
H<br />
J<br />
J<br />
K<br />
K<br />
L<br />
L<br />
M<br />
M<br />
N<br />
N<br />
P<br />
P<br />
R<br />
R<br />
T<br />
T<br />
U<br />
U<br />
V<br />
V<br />
W<br />
W<br />
Y<br />
Y<br />
AA<br />
AA<br />
AB<br />
AB<br />
AC<br />
AC<br />
AD<br />
AD<br />
AE<br />
AE<br />
AF<br />
AF<br />
AG<br />
AG<br />
AH<br />
AH<br />
AJ<br />
AJ<br />
AK<br />
AK<br />
AL<br />
AL<br />
AM<br />
AM<br />
AN<br />
AN<br />
AP<br />
AP<br />
www.BDTIC.com/XILINX
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-46<br />
A<br />
B 117 117<br />
C<br />
D 117 117<br />
E<br />
F 116 116<br />
G<br />
H 116 116<br />
J<br />
K<br />
L<br />
114 114 114 114<br />
Y 114 114<br />
AD 113 113<br />
AF 113 113<br />
AH 113 113<br />
AK 113 113<br />
AM 112 112<br />
AP 112 112<br />
115 115<br />
114 114 114 114<br />
114 114<br />
113 113<br />
113 113<br />
113 113<br />
112 112<br />
112 112<br />
112 112<br />
115 115<br />
P 115 115 115 115<br />
T 115 115<br />
115 115<br />
115 115<br />
116 116<br />
116 116 116 116<br />
116 116 116 116<br />
M 116 116<br />
N<br />
R<br />
U<br />
V<br />
W<br />
AA<br />
115 115<br />
114 114<br />
AB 114 114 114 114<br />
AC<br />
AE<br />
AG<br />
AJ<br />
AL<br />
AN<br />
1<br />
1<br />
2<br />
2<br />
3<br />
117 117<br />
117 117<br />
117 117<br />
117 117<br />
116 116<br />
3<br />
4<br />
4<br />
5<br />
117 117<br />
117 117<br />
117 117<br />
113 113<br />
113 113<br />
112 112<br />
112 112<br />
112 112<br />
112 112<br />
5<br />
6<br />
6<br />
7<br />
117 117<br />
116 116<br />
115 115<br />
115 115<br />
114 114<br />
113 113<br />
112 112<br />
111 111<br />
111 111<br />
111 111<br />
7<br />
8<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
115 115<br />
111 111<br />
111 111<br />
111 111<br />
111 111<br />
111 111<br />
111 111<br />
111 111<br />
11 11 11 11<br />
11 11 11 11<br />
11<br />
11 11 11 11<br />
11 11<br />
11 11 11<br />
11 11 11 11<br />
11 11 11 11<br />
11 11<br />
11 11 11 11<br />
11 11 11 11<br />
11 11 11 12<br />
11 11 11 12<br />
11 11 11 11<br />
17 17 17<br />
17 17<br />
17<br />
15 15 15<br />
15 14<br />
14 14 14 14<br />
14<br />
14 14 14 14 14 14 14 14 14 AA<br />
12 12 14 14<br />
12<br />
12 12 12<br />
11 11 12 12<br />
12 12 12 12<br />
11 12 12 12<br />
11 12 12 12<br />
17 17 17 15<br />
15 15<br />
15 15 15 15<br />
15<br />
17 17 17 17<br />
17 17 17 17<br />
17 17 17<br />
12 12 12 12<br />
12 12 12 12<br />
12 12 12 12<br />
12 12 12 12<br />
12 12 12 12<br />
14 14 14 14<br />
14 14 14 14<br />
14 14 14 14<br />
14 14<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15 15 15 15 15 R<br />
15 15 15 15<br />
17 16 16 16<br />
17 17 16 16<br />
17 17 17 16<br />
17 17 17 17<br />
16 16 16 16<br />
15 15 15 15<br />
14 14 14 14<br />
14 14 14 13 13 13 13 AC<br />
12 13 13 13<br />
12 12 13 13<br />
12 12 12 13<br />
12 13 13 13<br />
12 13 13 13<br />
12 12 13 13<br />
16 16 16 16<br />
16 16 16 16<br />
17 16 16 16<br />
17 17 17 17 17 16 16<br />
17 17 17 17<br />
17 17 17 17 17<br />
17 17 17<br />
15 15 15 15<br />
15 15 15 N<br />
15 15 15 15<br />
14 14 14 V<br />
14 14 14 14 Y<br />
14 14 14 14<br />
13 AD<br />
13 13 13 13 AE<br />
13 13 13 13<br />
13 13 AF<br />
13 13 13 AH<br />
13 AJ<br />
13 13 13 13 AK<br />
13 13 13 13<br />
13<br />
16<br />
16 16 16 C<br />
16 16 16 16 E<br />
16 16 16 16<br />
17 17 16 16<br />
13 13 13 13 13<br />
16 D<br />
16 16 F<br />
16 16 16 H<br />
16<br />
16 16 16 16 K<br />
15 P<br />
15 15 T<br />
14 W<br />
13 13 AL<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
A<br />
B<br />
G<br />
J<br />
16 16 L<br />
M<br />
U<br />
AB<br />
AG<br />
AM<br />
13 AN<br />
AP<br />
ug475_c3_50_052311<br />
Figure 3-46:<br />
FFG1156 Package—XC7K420T I/O Banks<br />
www.BDTIC.com/XILINX<br />
90 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Kintex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-47<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
A<br />
17 17 17<br />
17 16 16 16<br />
16<br />
A<br />
B<br />
17 17 17 17<br />
16 16 16 16<br />
B<br />
C<br />
17 17<br />
17 17 16 16<br />
16 16 16<br />
C<br />
D<br />
17 17 17 17<br />
16 16 16 16<br />
16<br />
D<br />
E<br />
17<br />
17 17 17 16<br />
16 16 16 16<br />
E<br />
F<br />
17 17 17<br />
17 16 16 16<br />
16 16<br />
F<br />
G<br />
17 17 17 17<br />
16 16 16 16<br />
G<br />
H<br />
17 17 17 17 17 16 16<br />
16 16 16<br />
H<br />
J<br />
17 17 17 17<br />
16 16 16 16<br />
16<br />
J<br />
K<br />
17 17 17 17 17<br />
16 16 16 16<br />
K<br />
L<br />
17 17 17<br />
17 17 16 16<br />
16 16<br />
L<br />
M<br />
17 17 17 15<br />
15 15 15 15<br />
M<br />
N<br />
15 15<br />
15 15 15 15<br />
15 15 15<br />
N<br />
P<br />
15 15 15 15<br />
15 15 15 15<br />
15<br />
P<br />
R<br />
15<br />
15 15 15 15 15 15 15 15<br />
R<br />
T<br />
15 15 15<br />
15 15 15 15<br />
15 15<br />
T<br />
U<br />
15 15 15 15<br />
15 15 15 15<br />
U<br />
V<br />
15 14<br />
14 14 14 14<br />
14 14 14<br />
V<br />
W<br />
14 14 14 14<br />
14 14 14 14<br />
14 W<br />
Y<br />
14<br />
14 14 14 14<br />
14 14 14 14<br />
Y<br />
AA<br />
14 14 14 14 14 14 14 14 14 AA<br />
AB<br />
14 14 14 14<br />
14 14 14 14<br />
AB<br />
AC<br />
14 14<br />
14 14 14 13 13 13 13 AC<br />
AD<br />
12 12 14 14<br />
12 13 13 13<br />
13 AD<br />
AE<br />
12<br />
12 12 12 12<br />
13 13 13 13 AE<br />
AF<br />
12 12 12<br />
12 12 13 13<br />
13 13 AF<br />
AG<br />
11 11 11 11<br />
11 11 11 11<br />
12 12 12 12<br />
13 13 13 13<br />
AG<br />
AH<br />
11 11 11 11<br />
11 11 12 12<br />
12 12 12 13<br />
13 13 13 AH<br />
AJ<br />
11 11<br />
11 11 11 11<br />
12 12 12 12<br />
12 13 13 13<br />
13 AJ<br />
AK<br />
11 11 11 11<br />
11 11 11 12<br />
12 12 12 12<br />
13 13 13 13 AK<br />
AL<br />
11<br />
11 11 11 11<br />
11 12 12 12<br />
12 13 13 13<br />
13 13 AL<br />
AM<br />
11 11 11<br />
11 11 11 12<br />
12 12 12 12<br />
13 13 13 13<br />
AM<br />
AN<br />
11 11 11 11<br />
11 12 12 12<br />
12 12 13 13<br />
13<br />
13 AN<br />
AP<br />
11 11<br />
11 11 11 11<br />
12 12 12 12<br />
13 13 13 13 13<br />
AP<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
Memory Groupings Pins<br />
# HP I/O<br />
# HR I/O<br />
# HP I/O − VCCAUX Group 0<br />
# HP I/O − VCCAUX Group 1<br />
# HP I/O − VCCAUX Group 2<br />
# HP I/O − VCCAUX Group 3<br />
# HP I/O − VCCAUX Group 4<br />
# HP I/O − VCCAUX Group 5<br />
# HP I/O − VCCAUX Group 6<br />
# HP I/O − VCCAUX Group 7<br />
# DQS pin<br />
# DCI pin<br />
# Memory Byte Group 0<br />
# Memory Byte Group 1<br />
# Memory Byte Group 2<br />
# Memory Byte Group 3<br />
# Bank Number<br />
ug475_c3_51_052311<br />
Figure 3-47:<br />
FFG1156 Package—XC7K420T Memory Groupings<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 91<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-48<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
A<br />
18<br />
16<br />
A<br />
B<br />
18<br />
16<br />
B<br />
C<br />
18<br />
17<br />
C<br />
D<br />
18<br />
16<br />
D<br />
E<br />
18<br />
16<br />
E<br />
F<br />
18<br />
17<br />
F<br />
G<br />
0<br />
17<br />
16<br />
G<br />
H<br />
0<br />
18<br />
16<br />
H<br />
J<br />
17<br />
J<br />
K<br />
17<br />
K<br />
L<br />
16<br />
L<br />
M<br />
17<br />
M<br />
N<br />
15<br />
N<br />
P<br />
15<br />
P<br />
R<br />
15<br />
R<br />
T<br />
15<br />
T<br />
U<br />
15 15<br />
U<br />
V<br />
14<br />
V<br />
W<br />
14<br />
W<br />
Y<br />
14<br />
Y<br />
AA<br />
14<br />
AA<br />
AB<br />
14<br />
AB<br />
AC<br />
14<br />
AC<br />
AD<br />
13<br />
AD<br />
AE<br />
13<br />
AE<br />
AF<br />
12<br />
AF<br />
AG<br />
12<br />
13 AG<br />
AH<br />
11<br />
13<br />
AH<br />
AJ<br />
11<br />
12<br />
AJ<br />
AK<br />
11<br />
12<br />
AK<br />
AL<br />
11<br />
13<br />
AL<br />
AM<br />
11<br />
13<br />
AM<br />
AN<br />
11<br />
12<br />
13<br />
AN<br />
AP<br />
12<br />
AP<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
Power Pins<br />
# VCCO_#<br />
VCCINT<br />
VCCAUX<br />
# VCCAUX_IO_G#<br />
VCCBRAM<br />
VCCBATT_0<br />
VCCADC_0<br />
GNDADC_0<br />
MGTVCCAUX<br />
# MGTVCCAUX_G# or MGTHVCCAUX_G#<br />
MGTAVCC<br />
# MGTAVCC_G# or MGTHAVCC_G#<br />
MGTAVTT<br />
# MGTAVTT_G# or MGTHAVTT_G#<br />
GND<br />
ug475_c3_52_052311<br />
Figure 3-48:<br />
FFG1156 Package—XC7K420T Power <strong>and</strong> GND Placement<br />
www.BDTIC.com/XILINX<br />
92 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Kintex-7 <strong>FPGAs</strong> Device Diagrams<br />
FFG1156 Package—XC7K480T<br />
X-Ref Target - Figure 3-49<br />
1<br />
A<br />
B<br />
C<br />
D<br />
E<br />
F<br />
G<br />
H<br />
J<br />
K<br />
L<br />
M<br />
N<br />
P<br />
R<br />
T<br />
U<br />
V<br />
W<br />
Y<br />
AA<br />
AB<br />
AC<br />
AD<br />
AE<br />
AF<br />
AG<br />
AH<br />
AJ<br />
AK<br />
AL<br />
AM<br />
AN<br />
AP<br />
1<br />
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
V V V<br />
V<br />
V<br />
V<br />
V<br />
E<br />
E<br />
V<br />
E<br />
V<br />
E<br />
V<br />
E<br />
V<br />
E<br />
V<br />
E<br />
V<br />
E<br />
V<br />
E<br />
V<br />
E<br />
V<br />
E<br />
V<br />
E<br />
V<br />
E<br />
V<br />
V<br />
V<br />
V<br />
V V V<br />
V<br />
V<br />
V<br />
G<br />
E<br />
V<br />
A<br />
E<br />
B<br />
C<br />
E<br />
C<br />
D<br />
E<br />
E O K<br />
F<br />
I s<br />
G<br />
M<br />
s s<br />
H<br />
s<br />
J<br />
K<br />
s<br />
L<br />
s<br />
B<br />
M<br />
N<br />
P<br />
r r R<br />
s<br />
B B T<br />
S S<br />
U<br />
S S<br />
s<br />
B<br />
B V<br />
L J<br />
W<br />
B<br />
Y<br />
s<br />
B AA<br />
U B<br />
AB<br />
s<br />
s s<br />
s<br />
s<br />
AC<br />
AD<br />
AE<br />
AF<br />
Y<br />
D<br />
2<br />
s<br />
1<br />
0<br />
s<br />
AG<br />
AH<br />
AJ<br />
E<br />
AK<br />
AL<br />
E<br />
P<br />
AM<br />
AN<br />
E<br />
AP<br />
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
User I/O Pins<br />
Transceiver Pins<br />
Dedicated Pins<br />
Other Pins<br />
IO_LXXY_#<br />
E<br />
MGTAVCC_G#<br />
C<br />
CCLK_0<br />
S<br />
VP_0<br />
GND<br />
s<br />
IO_XX_#<br />
V<br />
MGTAVTT_G#<br />
CFGBVS_0<br />
S<br />
VN_0<br />
VCCAUX_IO_G#<br />
Multi−Function Pins<br />
V<br />
V<br />
MGTVCCAUX_G#<br />
MGTAVTTRCAL<br />
G MGTRREF<br />
D<br />
J<br />
L<br />
DONE_0<br />
DXP_0<br />
DXN_0<br />
S<br />
S<br />
VREFP_0<br />
VREFN_0<br />
VCCAUX<br />
VCCINT<br />
VCCO_#<br />
B<br />
ADV_B<br />
VRN<br />
MGTREFCLK1/0P<br />
GNDADC_0<br />
VCCBRAM<br />
B<br />
FCS_B<br />
VRP<br />
MGTREFCLK1/0N<br />
Y<br />
INIT_B_0<br />
n<br />
NC<br />
B<br />
FOE_B<br />
VREF<br />
MGTXRXP<br />
0 M0_0<br />
B<br />
MOSI<br />
D00−D31<br />
MGTXRXN<br />
1 M1_0<br />
B<br />
FWE_B<br />
A00−A28<br />
MGTXTXP<br />
2 M2_0<br />
B<br />
DOUT_CSO_B<br />
DQS<br />
MGTXTXN<br />
P<br />
PROGRAM_B_0<br />
B<br />
CSI_B<br />
MRCC<br />
E<br />
MGTHAVCC_G#<br />
K<br />
TCK_0<br />
B<br />
PUDC_B<br />
SRCC<br />
V<br />
MGTHAVTT_G#<br />
I<br />
TDI_0<br />
U<br />
RDWR_B<br />
MGTHRXP<br />
O<br />
TDO_0<br />
r<br />
RS0−RS1<br />
MGTHRXN<br />
M<br />
TMS_0<br />
AD0P/AD0N−AD15P/AD15N<br />
MGTHTXP<br />
VCCADC_0<br />
EMCCLK<br />
MGTHTXN<br />
VCCBATT_0<br />
ug475_c3_53_090511<br />
Figure 3-49:<br />
FFG1156 Package—XC7K480T <strong>Pinout</strong> Diagram<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 93<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-50<br />
A<br />
B 117 117<br />
C<br />
D 117 117<br />
E<br />
F 116 116<br />
G<br />
H 116 116<br />
J<br />
K<br />
L<br />
114 114 114 114<br />
Y 114 114<br />
AD 113 113<br />
AF 113 113<br />
AH 113 113<br />
AK 113 113<br />
AM 112 112<br />
AP 112 112<br />
115 115<br />
114 114 114 114<br />
114 114<br />
113 113<br />
113 113<br />
113 113<br />
112 112<br />
112 112<br />
112 112<br />
115 115<br />
P 115 115 115 115<br />
T 115 115<br />
115 115<br />
115 115<br />
116 116<br />
116 116 116 116<br />
116 116 116 116<br />
M 116 116<br />
N<br />
R<br />
U<br />
V<br />
W<br />
AA<br />
114 114<br />
AB 114 114 114 114<br />
AC<br />
AE<br />
AG<br />
AJ<br />
AL<br />
AN<br />
1<br />
1<br />
2<br />
2<br />
3<br />
117 117<br />
117 117<br />
117 117<br />
117 117<br />
116 116<br />
3<br />
4<br />
4<br />
5<br />
117 117<br />
117 117<br />
117 117<br />
115 115<br />
113 113<br />
113 113<br />
112 112<br />
112 112<br />
112 112<br />
112 112<br />
5<br />
6<br />
6<br />
7<br />
118 118<br />
118 118<br />
118 118<br />
117 117<br />
116 116<br />
115 115<br />
115 115<br />
114 114<br />
113 113<br />
112 112<br />
111 111<br />
111 111<br />
111 111<br />
7<br />
8<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
118 118<br />
118 118<br />
118 118<br />
118 118<br />
115 115<br />
111 111<br />
111 111<br />
111 111<br />
111 111<br />
118 118<br />
118 118<br />
118 118<br />
111 111<br />
111 111<br />
111 111<br />
18<br />
18 18 18<br />
18 18 18 18<br />
18<br />
18 18 18<br />
11 11 11 11<br />
11 11 11 11<br />
11<br />
18 18 18 18<br />
18 18<br />
18 18 18 18<br />
11 11 11 11<br />
11 11<br />
11 11 11<br />
11 11 11 11<br />
11 11 11 11<br />
11 11<br />
18 18 18 18<br />
18 18 18 18<br />
18 18 18 18<br />
18 18 18 18<br />
11 11 11 11<br />
11 11 11 11<br />
11 11 11 12<br />
11 11 11 12<br />
11 11 11 11<br />
18 17 17 17<br />
18 18 17 17<br />
18 18 18 17<br />
18 18 18 18<br />
15 15 15<br />
15 14<br />
14 14 14 14<br />
14<br />
14 14 14 14 14 14 14 14 14 AA<br />
12 12 14 14<br />
12<br />
12 12 12<br />
11 11 12 12<br />
12 12 12 12<br />
11 12 12 12<br />
11 12 12 12<br />
17 17 17 15<br />
15 15<br />
15 15 15 15<br />
15<br />
17 17 17 17<br />
17 17 17 17<br />
18 17 17 17<br />
12 12 12 12<br />
12 12 12 12<br />
12 12 12 12<br />
12 12 12 12<br />
12 12 12 12<br />
14 14 14 14<br />
14 14 14 14<br />
14 14 14 14<br />
14 14<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15 15 15 15 15 R<br />
15 15 15 15<br />
17 16 16 16<br />
17 17 16 16<br />
17 17 17 16<br />
17 17 17 17<br />
16 16 16 16<br />
15 15 15 15<br />
14 14 14 14<br />
14 14 14 13 13 13 13 AC<br />
12 13 13 13<br />
12 12 13 13<br />
12 12 12 13<br />
12 13 13 13<br />
12 13 13 13<br />
12 12 13 13<br />
16 16 16 16<br />
16 16 16 16<br />
17 16 16 16<br />
18 17 17 17 17 17 16 16<br />
17 17 17 17<br />
17 17 17 17 17<br />
17 17 17<br />
15 15 15 15<br />
15 15 15 N<br />
15 15 15 15<br />
14 14 14 V<br />
14 14 14 14 Y<br />
14 14 14 14<br />
13 AD<br />
13 13 13 13 AE<br />
13 13 13 13<br />
13 13 AF<br />
13 13 13 AH<br />
13 AJ<br />
13 13 13 13 AK<br />
13 13 13 13<br />
13<br />
16<br />
16 16 16 C<br />
16 16 16 16 E<br />
16 16 16 16<br />
17 17 16 16<br />
13 13 13 13 13<br />
16 D<br />
16 16 F<br />
16 16 16 H<br />
16<br />
16 16 16 16 K<br />
15 P<br />
15 15 T<br />
14 W<br />
13 13 AL<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
A<br />
B<br />
G<br />
J<br />
16 16 L<br />
M<br />
U<br />
AB<br />
AG<br />
AM<br />
13 AN<br />
AP<br />
ug475_c3_54_052311<br />
Figure 3-50:<br />
FFG1156 Package—XC7K480T I/O Banks<br />
www.BDTIC.com/XILINX<br />
94 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Kintex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-51<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
A<br />
18<br />
18 18 18 18<br />
18 17 17 17<br />
17 16 16 16<br />
16<br />
A<br />
B<br />
18 18 18<br />
18 18 18 18<br />
17 17 17 17<br />
16 16 16 16<br />
B<br />
C<br />
18 18 18 18<br />
18 18 17 17<br />
17 17 16 16<br />
16 16 16<br />
C<br />
D<br />
18 18<br />
18 18 18 18<br />
17 17 17 17<br />
16 16 16 16<br />
16<br />
D<br />
E<br />
18 18 18 18<br />
18 18 18 17<br />
17 17 17 16<br />
16 16 16 16<br />
E<br />
F<br />
18<br />
18 18 18 18<br />
18 17 17 17<br />
17 16 16 16<br />
16 16<br />
F<br />
G<br />
18 18 18<br />
18 18 18 18<br />
17 17 17 17<br />
16 16 16 16<br />
G<br />
H<br />
18 18 18 18<br />
18 17 17 17 17 17 16 16<br />
16 16 16<br />
H<br />
J<br />
17 17 17 17<br />
16 16 16 16<br />
16<br />
J<br />
K<br />
17 17 17 17 17<br />
16 16 16 16<br />
K<br />
L<br />
17 17 17<br />
17 17 16 16<br />
16 16<br />
L<br />
M<br />
17 17 17 15<br />
15 15 15 15<br />
M<br />
N<br />
15 15<br />
15 15 15 15<br />
15 15 15<br />
N<br />
P<br />
15 15 15 15<br />
15 15 15 15<br />
15<br />
P<br />
R<br />
15<br />
15 15 15 15 15 15 15 15<br />
R<br />
T<br />
15 15 15<br />
15 15 15 15<br />
15 15<br />
T<br />
U<br />
15 15 15 15<br />
15 15 15 15<br />
U<br />
V<br />
15 14<br />
14 14 14 14<br />
14 14 14<br />
V<br />
W<br />
14 14 14 14<br />
14 14 14 14<br />
14 W<br />
Y<br />
14<br />
14 14 14 14<br />
14 14 14 14<br />
Y<br />
AA<br />
14 14 14 14 14 14 14 14 14 AA<br />
AB<br />
14 14 14 14<br />
14 14 14 14<br />
AB<br />
AC<br />
14 14<br />
14 14 14 13 13 13 13 AC<br />
AD<br />
12 12 14 14<br />
12 13 13 13<br />
13 AD<br />
AE<br />
12<br />
12 12 12 12<br />
13 13 13 13 AE<br />
AF<br />
12 12 12<br />
12 12 13 13<br />
13 13 AF<br />
AG<br />
11 11 11 11<br />
11 11 11 11<br />
12 12 12 12<br />
13 13 13 13<br />
AG<br />
AH<br />
11 11 11 11<br />
11 11 12 12<br />
12 12 12 13<br />
13 13 13 AH<br />
AJ<br />
11 11<br />
11 11 11 11<br />
12 12 12 12<br />
12 13 13 13<br />
13 AJ<br />
AK<br />
11 11 11 11<br />
11 11 11 12<br />
12 12 12 12<br />
13 13 13 13 AK<br />
AL<br />
11<br />
11 11 11 11<br />
11 12 12 12<br />
12 13 13 13<br />
13 13 AL<br />
AM<br />
11 11 11<br />
11 11 11 12<br />
12 12 12 12<br />
13 13 13 13<br />
AM<br />
AN<br />
11 11 11 11<br />
11 12 12 12<br />
12 12 13 13<br />
13<br />
13 AN<br />
AP<br />
11 11<br />
11 11 11 11<br />
12 12 12 12<br />
13 13 13 13 13<br />
AP<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
Memory Groupings Pins<br />
# HP I/O<br />
# HR I/O<br />
# HP I/O − VCCAUX Group 0<br />
# HP I/O − VCCAUX Group 1<br />
# HP I/O − VCCAUX Group 2<br />
# HP I/O − VCCAUX Group 3<br />
# HP I/O − VCCAUX Group 4<br />
# HP I/O − VCCAUX Group 5<br />
# HP I/O − VCCAUX Group 6<br />
# HP I/O − VCCAUX Group 7<br />
# DQS pin<br />
# DCI pin<br />
# Memory Byte Group 0<br />
# Memory Byte Group 1<br />
# Memory Byte Group 2<br />
# Memory Byte Group 3<br />
# Bank Number<br />
ug475_c3_55_052311<br />
Figure 3-51:<br />
FFG1156 Package—XC7K480T Memory Groupings<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 95<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-52<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
A<br />
18<br />
16<br />
A<br />
B<br />
18<br />
16<br />
B<br />
C<br />
18<br />
17<br />
C<br />
D<br />
18<br />
16<br />
D<br />
E<br />
18<br />
16<br />
E<br />
F<br />
18<br />
17<br />
F<br />
G<br />
0<br />
17<br />
16<br />
G<br />
H<br />
0<br />
18<br />
16<br />
H<br />
J<br />
17<br />
J<br />
K<br />
17<br />
K<br />
L<br />
16<br />
L<br />
M<br />
17<br />
M<br />
N<br />
15<br />
N<br />
P<br />
15<br />
P<br />
R<br />
15<br />
R<br />
T<br />
15<br />
T<br />
U<br />
15 15<br />
U<br />
V<br />
14<br />
V<br />
W<br />
14<br />
W<br />
Y<br />
14<br />
Y<br />
AA<br />
14<br />
AA<br />
AB<br />
14<br />
AB<br />
AC<br />
14<br />
AC<br />
AD<br />
13<br />
AD<br />
AE<br />
13<br />
AE<br />
AF<br />
12<br />
AF<br />
AG<br />
12<br />
13 AG<br />
AH<br />
11<br />
13<br />
AH<br />
AJ<br />
11<br />
12<br />
AJ<br />
AK<br />
11<br />
12<br />
AK<br />
AL<br />
11<br />
13<br />
AL<br />
AM<br />
11<br />
13<br />
AM<br />
AN<br />
11<br />
12<br />
13<br />
AN<br />
AP<br />
12<br />
AP<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
Power Pins<br />
# VCCO_#<br />
VCCINT<br />
VCCAUX<br />
# VCCAUX_IO_G#<br />
VCCBRAM<br />
VCCBATT_0<br />
VCCADC_0<br />
GNDADC_0<br />
MGTVCCAUX<br />
# MGTVCCAUX_G# or MGTHVCCAUX_G#<br />
MGTAVCC<br />
# MGTAVCC_G# or MGTHAVCC_G#<br />
MGTAVTT<br />
# MGTAVTT_G# or MGTHAVTT_G#<br />
GND<br />
ug475_c3_56_052311<br />
Figure 3-52:<br />
FFG1156 Package—XC7K480T Power <strong>and</strong> GND Placement<br />
www.BDTIC.com/XILINX<br />
96 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Virtex-7 <strong>FPGAs</strong> Device Diagrams<br />
Virtex-7 <strong>FPGAs</strong> Device Diagrams<br />
Table 3-3:<br />
Device<br />
Virtex-7 <strong>FPGAs</strong> Device Diagrams Cross Reference<br />
FF(G) FF(G) FF(G) FF(G) FF(G) FF(G) FF(G) FL(G) FL(G) FL(G) FL(G) FH(G)<br />
1157 1158 1761 1926 1927 1928 1930 1761 1925 1928 1930 1761<br />
XC7V585T page 98 page 102<br />
XC7V1500T<br />
FL1761/<br />
FLG1761<br />
XC7V2000T page 106 page 110<br />
XC7VX330T<br />
FF1157/<br />
FFG1157<br />
FF1761/<br />
FFG1761<br />
XC7VX415T<br />
FF1157/<br />
FFG1157<br />
FF1158/<br />
FFG1158<br />
FF1927/<br />
FFG1927<br />
XC7VX485T page 114 page 118 page 122 page 126 page 130<br />
XC7VX550T<br />
FF1158/<br />
FFG1158<br />
FF1927/<br />
FFG1927<br />
XC7VX690T<br />
XC7VX980T<br />
FF1157/<br />
FFG1157<br />
FF1158/<br />
FFG1158<br />
FF1761/<br />
FFG1761<br />
FF1926/<br />
FFG1926<br />
FF1926/<br />
FFG1926<br />
FF1927/<br />
FFG1927<br />
FF1928/<br />
FFG1928<br />
FF1930/<br />
FFG1930<br />
FF1930/<br />
FFG1930<br />
XC7VX1140T<br />
FL1928/<br />
FLG1928<br />
FL1930/<br />
FLG1930<br />
Note: The available files are listed in Table 3-3 are linked. Figures for some Virtex-7 <strong>FPGAs</strong> are in<br />
development.<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 97<br />
<strong>UG475</strong> (v1.4) October 17, 2011
98 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011<br />
Chapter 3: Device Diagrams<br />
FFG1157 Package—XC7V585T<br />
X-Ref Target - Figure 3-53<br />
Figure 3-53:<br />
FF(G)1157 Package—XC7V585T <strong>Pinout</strong> Diagram<br />
User I/O Pins<br />
IO_LXXY_#<br />
s<br />
IO_XX_#<br />
Multi−Function Pins<br />
B<br />
ADV_B<br />
B<br />
FCS_B<br />
B<br />
FOE_B<br />
B<br />
MOSI<br />
B<br />
FWE_B<br />
B<br />
DOUT_CSO_B<br />
B<br />
CSI_B<br />
B<br />
PUDC_B<br />
U<br />
RDWR_B<br />
r<br />
RS0−RS1<br />
AD0P/AD0N−AD15P/AD15N<br />
EMCCLK<br />
VRN<br />
VRP<br />
VREF<br />
D00−D31<br />
A00−A28<br />
DQS<br />
MRCC<br />
SRCC<br />
Transceiver Pins<br />
E<br />
MGTAVCC_G#<br />
V<br />
MGTAVTT_G#<br />
V<br />
MGTVCCAUX_G#<br />
V<br />
MGTAVTTRCAL<br />
G<br />
MGTRREF<br />
MGTREFCLK1/0P<br />
MGTREFCLK1/0N<br />
MGTXRXP<br />
MGTXRXN<br />
MGTXTXP<br />
MGTXTXN<br />
E<br />
MGTHAVCC_G#<br />
V<br />
MGTHAVTT_G#<br />
MGTHRXP<br />
MGTHRXN<br />
MGTHTXP<br />
MGTHTXN<br />
Dedicated Pins<br />
C<br />
CCLK_0<br />
CFGBVS_0<br />
D<br />
DONE_0<br />
J<br />
DXP_0<br />
L<br />
DXN_0<br />
GNDADC_0<br />
Y<br />
INIT_B_0<br />
0 M0_0<br />
1 M1_0<br />
2 M2_0<br />
P<br />
PROGRAM_B_0<br />
K<br />
TCK_0<br />
I<br />
TDI_0<br />
O<br />
TDO_0<br />
M<br />
TMS_0<br />
VCCADC_0<br />
VCCBATT_0<br />
S<br />
VP_0<br />
S<br />
VN_0<br />
S<br />
VREFP_0<br />
S<br />
VREFN_0<br />
Other Pins<br />
GND<br />
VCCAUX_IO_G#<br />
VCCAUX<br />
VCCINT<br />
VCCO_#<br />
VCCBRAM<br />
n<br />
NC<br />
ug475_c3_170_090511<br />
L<br />
J<br />
S<br />
S<br />
S<br />
S<br />
C<br />
K<br />
M<br />
O<br />
I<br />
Y<br />
P<br />
D<br />
2<br />
0<br />
1<br />
B<br />
B<br />
B<br />
U<br />
B<br />
B<br />
B<br />
B<br />
B<br />
r<br />
r<br />
V<br />
G<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
n<br />
n<br />
1<br />
1<br />
2<br />
2<br />
3<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
6<br />
7<br />
7<br />
8<br />
8<br />
9<br />
9<br />
10<br />
10<br />
11<br />
11<br />
12<br />
12<br />
13<br />
13<br />
14<br />
14<br />
15<br />
15<br />
16<br />
16<br />
17<br />
17<br />
18<br />
18<br />
19<br />
19<br />
20<br />
20<br />
21<br />
21<br />
22<br />
22<br />
23<br />
23<br />
24<br />
24<br />
25<br />
25<br />
26<br />
26<br />
27<br />
27<br />
28<br />
28<br />
29<br />
29<br />
30<br />
30<br />
31<br />
31<br />
32<br />
32<br />
33<br />
33<br />
34<br />
34<br />
A<br />
A<br />
B<br />
B<br />
C<br />
C<br />
D<br />
D<br />
E<br />
E<br />
F<br />
F<br />
G<br />
G<br />
H<br />
H<br />
J<br />
J<br />
K<br />
K<br />
L<br />
L<br />
M<br />
M<br />
N<br />
N<br />
P<br />
P<br />
R<br />
R<br />
T<br />
T<br />
U<br />
U<br />
V<br />
V<br />
W<br />
W<br />
Y<br />
Y<br />
AA<br />
AA<br />
AB<br />
AB<br />
AC<br />
AC<br />
AD<br />
AD<br />
AE<br />
AE<br />
AF<br />
AF<br />
AG<br />
AG<br />
AH<br />
AH<br />
AJ<br />
AJ<br />
AK<br />
AK<br />
AL<br />
AL<br />
AM<br />
AM<br />
AN<br />
AN<br />
AP<br />
AP<br />
www.BDTIC.com/XILINX
Virtex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-54<br />
A<br />
B 118 118<br />
C<br />
D 118 118<br />
E<br />
F 117 117<br />
G<br />
H 117 117<br />
J<br />
K 117 117<br />
L<br />
M 117 117<br />
N<br />
P 116 116<br />
R<br />
AB 115 115<br />
AD 115 115<br />
AK 114 114<br />
AM 114 114<br />
115 115<br />
115 115<br />
114 114<br />
114 114<br />
114 114<br />
115 115<br />
115 115<br />
AF 115 115 115 115<br />
AH 115 115<br />
116 116<br />
T 116 116 116 116<br />
U<br />
V 116 116<br />
W<br />
Y 116 116<br />
AA<br />
AC<br />
AE<br />
AG<br />
AJ<br />
AL<br />
AN<br />
1<br />
114 114<br />
114 114<br />
114 114<br />
AP 114 114 114 114 115<br />
1<br />
2<br />
2<br />
3<br />
118 118<br />
118 118<br />
118 118<br />
118 118<br />
117 117<br />
117 117<br />
117 117<br />
116 116<br />
116 116<br />
116 116<br />
115 115<br />
3<br />
4<br />
4<br />
5<br />
118 118<br />
118 118<br />
118 118<br />
118 118<br />
117 117<br />
117 117<br />
117 117<br />
116 116<br />
5<br />
6<br />
6<br />
7<br />
115<br />
7<br />
8<br />
39 39 39 39<br />
39 39 39<br />
34 34<br />
34 34<br />
34<br />
34 34 34 34<br />
34 34 34 34<br />
34<br />
34 34 34<br />
34 34 35 35<br />
34 34 34 35<br />
34 34 34 34<br />
34 34<br />
34 34 34 34<br />
34 34 35 35<br />
34 34 34 35<br />
34 34 34 34<br />
34 34<br />
34<br />
34 34 34<br />
39 39 38 38 38 37 37 37<br />
39 39 39 38 38 38 37 37<br />
34 34 35 35<br />
38 38 38 37<br />
37 37 19 19<br />
37 37 37 19<br />
37 37 37 19<br />
37 19 19 19<br />
37 37 18 18<br />
18 18 18 18<br />
16 16 16<br />
35 35 36 36 36 15 15 15<br />
35 35 35 35<br />
35 35 35 35<br />
34 35 35 35<br />
35 35 35 36<br />
35 35 35 35<br />
35 35 35 35<br />
35 35 35 36<br />
35 35 35 35<br />
35 35 35 35<br />
38 37 37 37<br />
39 39 39 39 38 38 38 38 38 37 37<br />
39 39 39 39<br />
39 39 39 39 38 38<br />
39 39 39 39<br />
39<br />
39 39 39<br />
39 38 38 38 38 38<br />
39 39 39 38<br />
39 39 39 39<br />
39 39<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
39 39 39<br />
39 39 39 39<br />
38 38 38 38<br />
38 38 38 38<br />
38 38 38 38<br />
39 38 38 38<br />
38 38 38 37<br />
38 38 38 38<br />
38 38 38 38<br />
37 37 37 37<br />
37 37 37 37<br />
37 37 37 37<br />
37<br />
36 36 36 36<br />
35 36 36 36<br />
35 35 35 36<br />
35 36 36 36<br />
35 35 36 36<br />
37 37 37 37<br />
38 37 37 37<br />
37 37 37 37<br />
17 17 17 17 17 17 17<br />
17 17<br />
17<br />
36 36 15 15<br />
36 36 36 36<br />
36 36 36 36<br />
19 19 19 18<br />
17 17 17 17<br />
17 17 17<br />
16 16 16 16<br />
16<br />
16 16 16 16<br />
15 15 15 15<br />
36 14 14 15<br />
36 36 14 14<br />
14 15 15 15<br />
36 14 14 14<br />
36 36 14 14<br />
36 36 36 14<br />
19 19 19 19<br />
37 19 19 19<br />
37 37 19 19<br />
36 36 36 36<br />
36 36 36 36<br />
36 36 36 36<br />
19 19 19 19<br />
19 19 19 18<br />
17 17 17 17<br />
17 17 17 17<br />
14 14 14 14<br />
14 14 14 14<br />
36 14 14 14<br />
19 19 19 19<br />
18 18 18 18<br />
18 18 18 18 18 18 18 18 K<br />
18 18 18 18<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
19 19 19 19<br />
19 18 18 18 18 18 F<br />
18 18 18 18<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
14 14 15 15<br />
14 14 14 14<br />
14 14 14 14<br />
19 19 19 19 19 B<br />
19 19 19 19<br />
18 18 18 18<br />
17 17 17 17<br />
17 17 17 17<br />
17 17 17 17<br />
16 17 17 17<br />
16 16 16 16<br />
16 16 16 16<br />
19 18 18 18 E<br />
18 18 18 18<br />
19<br />
19 19 19 C<br />
18 18 18 H<br />
18 18<br />
17 17 17 N<br />
17 17 17 17 R<br />
16 16 16 V<br />
16 16 16 16<br />
14 14 14 14 AK<br />
14 14 14 14<br />
14 14 AL<br />
14 14 14 AN<br />
14 14 14 14 14<br />
15 AD<br />
15 15 15 15 AE<br />
15 15 15 15<br />
19 D<br />
18<br />
17 P<br />
17 17 T<br />
16 W<br />
16 16 16 16 Y<br />
16 16 AA<br />
16 16 16 AC<br />
15 15 AF<br />
15 15 15 AH<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
A<br />
G<br />
J<br />
L<br />
M<br />
U<br />
AB<br />
AG<br />
15 AJ<br />
AM<br />
AP<br />
ug475_c3_7V585TFFG1157_061011<br />
Figure 3-54:<br />
FF(G)1157 Package—XC7V585T I/O Banks<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 99<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-55<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
A<br />
39 39 39 39<br />
38 38 38 38<br />
38 37 37 37<br />
37 37 19 19<br />
19 19 19 19<br />
19<br />
A<br />
B<br />
39 39 39<br />
39 38 38 38 38 38<br />
37 37 37 37<br />
19 19 19 19<br />
19 19 19 19 19<br />
B<br />
C<br />
39 39 39 39 38 38 38 38 38 37 37<br />
37 37 37 19<br />
19 19 19 19<br />
19 19 19<br />
C<br />
D<br />
39 39 39 39<br />
38 38 38 38<br />
37 37 37 37<br />
37 19 19 19<br />
19 19 19 19<br />
19<br />
D<br />
E<br />
39 39 39 39 38 38<br />
38 38 38 37<br />
37 37 37 19<br />
19 19 19 19<br />
19 18 18 18<br />
E<br />
F<br />
39 39 39 39<br />
38 38 38 38<br />
38 37 37 37<br />
37 19 19 19<br />
19 18 18 18 18 18<br />
F<br />
G<br />
39<br />
39 39 39 38<br />
38 38 38 38<br />
37 37 37 37<br />
19 19 19 18<br />
18 18 18 18<br />
G<br />
H<br />
39 39 39<br />
39 39 38 38 38 37 37 37<br />
37 37 19 19<br />
18 18 18 18<br />
18 18 18<br />
H<br />
J<br />
39 39 39 39<br />
38 38 38 38<br />
37 37 37 37<br />
19 19 19 18<br />
18 18 18 18<br />
18<br />
J<br />
K<br />
39 39<br />
39 39 39 38 38 38 37 37<br />
37 37 18 18<br />
18 18 18 18 18 18 18 18<br />
K<br />
L<br />
39 39 39<br />
39 38 38 38<br />
37 37 37 37<br />
18 18 18 18<br />
18 18 18 18<br />
18 18<br />
L<br />
M<br />
39 39 39 39<br />
38 38 38 37<br />
37<br />
18 18 18 18<br />
17 17 17 17<br />
M<br />
N<br />
17 17 17 17 17 17 17<br />
17 17 17<br />
N<br />
P<br />
17 17 17 17<br />
17 17 17 17<br />
17<br />
P<br />
R<br />
17 17<br />
17 17 17 17<br />
17 17 17 17<br />
R<br />
T<br />
17 17 17<br />
17 17 17 17<br />
17 17<br />
T<br />
U<br />
17<br />
17 17 17 17<br />
16 17 17 17<br />
U<br />
V<br />
16 16 16<br />
16 16 16 16<br />
16 16 16<br />
V<br />
W<br />
16 16 16 16<br />
16 16 16 16<br />
16 W<br />
Y<br />
16<br />
16 16 16 16<br />
16 16 16 16<br />
Y<br />
AA<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 AA<br />
AB<br />
16 16 16 16<br />
16 16 16 16<br />
AB<br />
AC<br />
34 34<br />
34<br />
35 35 36 36 36 15 15 15<br />
15 15 15 15<br />
16 16 16 AC<br />
AD<br />
34 34 34 34<br />
35 35 35 35<br />
36 36 36 36<br />
15 15 15 15<br />
15 15 15 15<br />
15 AD<br />
AE<br />
34 34<br />
34 34 35 35<br />
35 35 35 36<br />
36 36 15 15<br />
15 15 15 15<br />
15 15 15 15 AE<br />
AF<br />
34 34 34 34<br />
35 35 35 35<br />
35 36 36 36<br />
36 14 14 15<br />
15 15 15 15<br />
15 15 AF<br />
AG<br />
34<br />
34 34 34 35<br />
35 35 35 35<br />
36 36 36 36<br />
14 15 15 15<br />
15 15 15 15<br />
AG<br />
AH<br />
34 34 34<br />
34 34 35 35<br />
35 35 35 36<br />
36 36 14 14<br />
15 15 15 15<br />
15 15 15 AH<br />
AJ<br />
34 34 34 34<br />
35 35 35 35<br />
36 36 36 36<br />
36 14 14 14<br />
14 14 15 15<br />
15 AJ<br />
AK<br />
34 34<br />
34 34 34 35<br />
35 35 35 36<br />
36 36 36 36<br />
14 14 14 14<br />
14 14 14 14 AK<br />
AL<br />
34 34 34 34<br />
34 35 35 35<br />
35 36 36 36<br />
36 36 14 14<br />
14 14 14 14<br />
14 14 AL<br />
AM<br />
34 34 34 34<br />
35 35 35 35<br />
36 36 36 36<br />
14 14 14 14<br />
14 14 14 14<br />
AM<br />
AN<br />
34 34<br />
34 34 35 35<br />
35 35 36 36<br />
36 36 36 14<br />
14 14 14 14<br />
14 14 14 AN<br />
AP<br />
34<br />
34 34 34<br />
35 35 35 35<br />
36 36 36 36<br />
36 14 14 14<br />
14 14 14 14 14<br />
AP<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
Memory Groupings Pins<br />
# HP I/O<br />
# HR I/O<br />
# HP I/O − VCCAUX Group 0<br />
# HP I/O − VCCAUX Group 1<br />
# HP I/O − VCCAUX Group 2<br />
# HP I/O − VCCAUX Group 3<br />
# HP I/O − VCCAUX Group 4<br />
# HP I/O − VCCAUX Group 5<br />
# HP I/O − VCCAUX Group 6<br />
# HP I/O − VCCAUX Group 7<br />
# DQS pin<br />
# DCI pin<br />
# Memory Byte Group 0<br />
# Memory Byte Group 1<br />
# Memory Byte Group 2<br />
# Memory Byte Group 3<br />
# Bank Number<br />
ug475_c3_7V585TFFG1157_061011<br />
Figure 3-55:<br />
FF(G)1157 Package—XC7V585T Memory Groupings<br />
www.BDTIC.com/XILINX<br />
100 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Virtex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-56<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
A<br />
38<br />
37<br />
19<br />
A<br />
B<br />
39<br />
37<br />
19<br />
B<br />
C<br />
11<br />
11<br />
38<br />
19<br />
C<br />
D<br />
11<br />
38<br />
37<br />
19<br />
D<br />
E<br />
11<br />
39<br />
37<br />
19<br />
E<br />
F<br />
38<br />
19<br />
F<br />
G<br />
11<br />
11<br />
38<br />
19<br />
18<br />
G<br />
H<br />
11<br />
39<br />
37<br />
18<br />
H<br />
J<br />
11<br />
39<br />
37<br />
18<br />
J<br />
K<br />
38<br />
18<br />
K<br />
L<br />
11<br />
11<br />
39<br />
18 18<br />
L<br />
M<br />
11<br />
39<br />
37<br />
18<br />
M<br />
N<br />
11<br />
3<br />
1<br />
17<br />
N<br />
P<br />
17 17<br />
P<br />
R<br />
10<br />
10<br />
3<br />
1<br />
17<br />
R<br />
T<br />
10<br />
17<br />
T<br />
U<br />
10<br />
3<br />
1<br />
16<br />
17<br />
U<br />
V<br />
16<br />
V<br />
W<br />
10<br />
10<br />
0<br />
2<br />
0<br />
16<br />
W<br />
Y<br />
10<br />
16<br />
Y<br />
AA<br />
10<br />
2<br />
0<br />
16<br />
AA<br />
AB<br />
0<br />
16<br />
AB<br />
AC<br />
10<br />
10<br />
2<br />
35<br />
0<br />
15<br />
AC<br />
AD<br />
10<br />
34<br />
15 15<br />
AD<br />
AE<br />
10<br />
34<br />
36<br />
15<br />
AE<br />
AF<br />
35<br />
15<br />
AF<br />
AG<br />
10<br />
10<br />
35<br />
14<br />
15 AG<br />
AH<br />
10<br />
34<br />
36<br />
15<br />
AH<br />
AJ<br />
10<br />
34<br />
35<br />
14<br />
AJ<br />
AK<br />
35<br />
36<br />
AK<br />
AL<br />
10<br />
10<br />
34<br />
36<br />
14<br />
AL<br />
AM<br />
10<br />
34<br />
36<br />
14<br />
AM<br />
AN<br />
10<br />
35<br />
14<br />
AN<br />
AP<br />
34<br />
36<br />
14 AP<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
Power Pins<br />
# VCCO_#<br />
VCCINT<br />
VCCAUX<br />
# VCCAUX_IO_G#<br />
VCCBRAM<br />
VCCBATT_0<br />
VCCADC_0<br />
GNDADC_0<br />
MGTVCCAUX<br />
# MGTVCCAUX_G# or MGTHVCCAUX_G#<br />
MGTAVCC<br />
# MGTAVCC_G# or MGTHAVCC_G#<br />
MGTAVTT<br />
# MGTAVTT_G# or MGTHAVTT_G#<br />
GND<br />
ug475_c3_7V585TFFG1157_080911<br />
Figure 3-56:<br />
FF(G)1157 Package—XC7V585T Power <strong>and</strong> GND Placement<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 101<br />
<strong>UG475</strong> (v1.4) October 17, 2011
102 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011<br />
Chapter 3: Device Diagrams<br />
FFG1761 Package—XC7V585T<br />
X-Ref Target - Figure 3-57<br />
Figure 3-57:<br />
FF(G)1761 Package—XC7V585T <strong>Pinout</strong> Diagram<br />
ug475_c3_174_090511<br />
User I/O Pins<br />
IO_LXXY_#<br />
s<br />
IO_XX_#<br />
Multi−Function Pins<br />
B<br />
ADV_B<br />
B<br />
FCS_B<br />
B<br />
FOE_B<br />
B<br />
MOSI<br />
B<br />
FWE_B<br />
B<br />
DOUT_CSO_B<br />
B<br />
CSI_B<br />
B<br />
PUDC_B<br />
U<br />
RDWR_B<br />
r<br />
RS0−RS1<br />
AD0P/AD0N−AD15P/AD15N<br />
EMCCLK<br />
VRN<br />
VRP<br />
VREF<br />
D00−D31<br />
A00−A28<br />
DQS<br />
MRCC<br />
SRCC<br />
Transceiver Pins<br />
E<br />
MGTAVCC_G#<br />
V<br />
MGTAVTT_G#<br />
V<br />
MGTVCCAUX_G#<br />
V<br />
MGTAVTTRCAL<br />
G<br />
MGTRREF<br />
MGTREFCLK1/0P<br />
MGTREFCLK1/0N<br />
MGTXRXP<br />
MGTXRXN<br />
MGTXTXP<br />
MGTXTXN<br />
E<br />
MGTHAVCC_G#<br />
V<br />
MGTHAVTT_G#<br />
MGTHRXP<br />
MGTHRXN<br />
MGTHTXP<br />
MGTHTXN<br />
Dedicated Pins<br />
C<br />
CCLK_0<br />
CFGBVS_0<br />
D<br />
DONE_0<br />
J<br />
DXP_0<br />
L<br />
DXN_0<br />
GNDADC_0<br />
Y<br />
INIT_B_0<br />
0 M0_0<br />
1 M1_0<br />
2 M2_0<br />
P<br />
PROGRAM_B_0<br />
K<br />
TCK_0<br />
I<br />
TDI_0<br />
O<br />
TDO_0<br />
M<br />
TMS_0<br />
VCCADC_0<br />
VCCBATT_0<br />
S<br />
VP_0<br />
S<br />
VN_0<br />
S<br />
VREFP_0<br />
S<br />
VREFN_0<br />
Other Pins<br />
GND<br />
VCCAUX_IO_G#<br />
VCCAUX<br />
VCCINT<br />
VCCO_#<br />
VCCBRAM<br />
n<br />
NC<br />
L<br />
J<br />
S<br />
S<br />
S<br />
S<br />
C<br />
K<br />
M<br />
O<br />
I<br />
Y<br />
P<br />
D<br />
2<br />
0<br />
1<br />
s<br />
s<br />
s<br />
s<br />
B<br />
B<br />
B<br />
U<br />
B<br />
B<br />
B<br />
B<br />
B<br />
r<br />
r<br />
V<br />
G<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
1<br />
1<br />
2<br />
2<br />
3<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
6<br />
7<br />
7<br />
8<br />
8<br />
9<br />
9<br />
10<br />
10<br />
11<br />
11<br />
12<br />
12<br />
13<br />
13<br />
14<br />
14<br />
15<br />
15<br />
16<br />
16<br />
17<br />
17<br />
18<br />
18<br />
19<br />
19<br />
20<br />
20<br />
21<br />
21<br />
22<br />
22<br />
23<br />
23<br />
24<br />
24<br />
25<br />
25<br />
26<br />
26<br />
27<br />
27<br />
28<br />
28<br />
29<br />
29<br />
30<br />
30<br />
31<br />
31<br />
32<br />
32<br />
33<br />
33<br />
34<br />
34<br />
35<br />
35<br />
36<br />
36<br />
37<br />
37<br />
38<br />
38<br />
39<br />
39<br />
40<br />
40<br />
41<br />
41<br />
42<br />
42<br />
A<br />
A<br />
B<br />
B<br />
C<br />
C<br />
D<br />
D<br />
E<br />
E<br />
F<br />
F<br />
G<br />
G<br />
H<br />
H<br />
J<br />
J<br />
K<br />
K<br />
L<br />
L<br />
M<br />
M<br />
N<br />
N<br />
P<br />
P<br />
R<br />
R<br />
T<br />
T<br />
U<br />
U<br />
V<br />
V<br />
W<br />
W<br />
Y<br />
Y<br />
AA<br />
AA<br />
AB<br />
AB<br />
AC<br />
AC<br />
AD<br />
AD<br />
AE<br />
AE<br />
AF<br />
AF<br />
AG<br />
AG<br />
AH<br />
AH<br />
AJ<br />
AJ<br />
AK<br />
AK<br />
AL<br />
AL<br />
AM<br />
AM<br />
AN<br />
AN<br />
AP<br />
AP<br />
AR<br />
AR<br />
AT<br />
AT<br />
AU<br />
AU<br />
AV<br />
AV<br />
AW<br />
AW<br />
AY<br />
AY<br />
BA<br />
BA<br />
BB<br />
BB<br />
www.BDTIC.com/XILINX
Virtex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-58<br />
A<br />
B<br />
C 119 119<br />
D<br />
E 119 119<br />
F<br />
G 118 118<br />
H<br />
J 118 118<br />
K<br />
R 116 116<br />
U 116 116<br />
W 115 115<br />
AG 114 114<br />
AJ 114 114<br />
AL 113 113<br />
AN 113 113<br />
AR 112 112<br />
115 115<br />
AA 115 115 115 115<br />
AC 115 115<br />
AE 115 115<br />
117 117<br />
116 116<br />
116 116<br />
116 116<br />
115 115<br />
114 114<br />
114 114<br />
114 114<br />
114 114<br />
113 113<br />
113 113<br />
117 117<br />
L 117 117 117 117<br />
M<br />
N 117 117<br />
P<br />
T<br />
V<br />
Y<br />
AB<br />
AD<br />
AF<br />
AH<br />
AK<br />
AM<br />
AP<br />
AT<br />
112 112<br />
AW 111 111 111 111<br />
111 111 111 111<br />
BA 111 111 111 111<br />
112 112<br />
112 112 112 112<br />
AU 112 112 112 112<br />
AV<br />
AY<br />
BB<br />
1<br />
1<br />
2<br />
2<br />
3<br />
119 119<br />
119 119<br />
118 118<br />
118 118<br />
117 117<br />
113 113<br />
113 113<br />
113 113<br />
112 112 112 112<br />
111 111 111 111<br />
3<br />
4<br />
4<br />
5<br />
119 119<br />
119 119<br />
118 118<br />
118 118<br />
117 117<br />
116 116<br />
116 116<br />
116 116<br />
115 115<br />
114 114<br />
114 114<br />
113 113<br />
5<br />
6<br />
6<br />
7<br />
119 119<br />
119 119<br />
118 118<br />
118 118<br />
117 117<br />
117 117<br />
117 117<br />
116 116<br />
116 116<br />
115 115<br />
115 115<br />
114 114<br />
114 114<br />
113 113<br />
113 113<br />
7<br />
8<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42<br />
119 119<br />
119 119<br />
118 118<br />
118 118<br />
112 112<br />
111 111<br />
111 111<br />
115<br />
31 31<br />
31<br />
31<br />
31 31 31<br />
31 31 31 31<br />
31<br />
115<br />
31 31 31<br />
31 31 32 32<br />
31 31 31 32<br />
31 31 31 32<br />
31 31 31 31<br />
31<br />
31 31 31<br />
31 31 32 32<br />
31 31 31 32<br />
31 31<br />
31 31 31 31<br />
31<br />
31 31 31<br />
39 38 38 38 38 38 38 37 37 37 37 37<br />
39<br />
39 39 39 39<br />
39 39<br />
39 39 39 39<br />
39 39 39<br />
39 39 39<br />
39 39 39<br />
39 38 38 38<br />
39 39 38 38<br />
39 38<br />
39 39 39 39<br />
39 39 39 39<br />
39 39<br />
39 39 39 39<br />
32 32 32 32<br />
31 32 32 32<br />
31 31 32 32<br />
38 38 38 38<br />
38 38 38 38<br />
39 38 38 38<br />
38 38 38 36 36 36 36 36<br />
39 39 38 38 38 36 36 36<br />
39 39 39 38<br />
39 39 39 39<br />
32 32 32 33<br />
32 33 33 33<br />
32 32 33 33<br />
32 32 32 32<br />
32 32 32 32<br />
32 32 33 33<br />
32 32 32 33<br />
32 32 32 32<br />
32 32 32 32<br />
38 38 37 37<br />
38 38 38 38<br />
39 38 38 38<br />
36 36 36 36<br />
33 33 33 33<br />
12 12<br />
33 33 12 12<br />
33 33 33 33<br />
31 32 32 32 32 33 33 33<br />
36 36 36 36 36 36 36 36<br />
33 12 12 12<br />
33 33 12 12<br />
33 33 33 12<br />
33 33 33 33<br />
32 33 33 33<br />
32 32 33 33<br />
36 36 36 36<br />
12 12 12 12<br />
33 12 12 12<br />
33 33 12 12<br />
33 33 33 33<br />
33 33 33 33<br />
36 36 36 36<br />
38 38 36 36 36 36 36 36<br />
38 38 38 36<br />
38 38<br />
38 37 37 37 37 37 37 37<br />
38 36 36 36<br />
37 37 37 37<br />
38 38 37 37 37 37 37 37<br />
37 37 37 37<br />
36 36 36 36<br />
12 12 12 12<br />
12 12 13 13<br />
12 12 12 12<br />
12 12 12 12<br />
33 33 12 12<br />
36 36 34 34<br />
36 36 34 34<br />
36 36 34 34<br />
36 36<br />
37 37 37 37<br />
34 34 34<br />
14 14 14 14<br />
14<br />
12 14 14 14<br />
12 12 12 13<br />
12 12 13 13<br />
12 12 12 13<br />
12 12 12 12<br />
34 34 34 18<br />
16 16 16 16<br />
16<br />
16 16 16<br />
14 14 16 16<br />
14<br />
34 34 34 34<br />
34 34 34 34<br />
34 34 34 34<br />
34<br />
37 37 37 37<br />
37 37 37 37<br />
34 34<br />
34 34 18 18<br />
34 34 34<br />
14 14 14 16<br />
14 14 14 14<br />
14 14 14 14<br />
13 13 13 13<br />
12 13 13 13<br />
12 13 13 13<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
16 16<br />
34 34 34 34<br />
34 34 34 34<br />
13 13 13 13<br />
13 13 13 13<br />
13 13 13 13<br />
18 18 18 19<br />
18 18 18 18<br />
34 18 18 18<br />
34 34 18 18<br />
34 34<br />
37 35 35 35<br />
37 37 35 35<br />
37 37 37 37 37 37 37<br />
35 35 35 35<br />
35 34 34 35<br />
16 16 16 16<br />
14 14 14 16<br />
14 14 14 14<br />
14 14 14 14<br />
14 14 14 14<br />
13 13 13 13<br />
13 13 13 13<br />
13 13 13 13<br />
35 35 35 35<br />
35 35 35 35<br />
35 35 35 35<br />
34 34 19 19<br />
18 18 18 18<br />
16 16 16 16<br />
16 16 16 16<br />
18 18 18 18<br />
18 18 18 18<br />
35 35 35 35<br />
35 35 35 35<br />
35 35 35 35 35<br />
16 16 16 17<br />
16 16 16 16<br />
14 14 14 17<br />
14 14 14 14<br />
14 14 15 15<br />
14 14 14 15<br />
13 13 13 15<br />
13 15 15 15<br />
13 13 15 15<br />
13 13 13 15<br />
35 35 35 19<br />
18 18 18 19<br />
18 18 18 18<br />
18 18 18 18<br />
16 17 17 17<br />
16 16 17 17<br />
16 17 17 17<br />
16 17 17 17<br />
14 17 17 17<br />
15 15 15 15<br />
15 15 15 15<br />
13 15 15 15<br />
35 19 19<br />
35 35 19 19<br />
18 18 18 18 T<br />
18 18 18 18<br />
15 15 AM<br />
15 15 15 AP<br />
15 AR<br />
15 15 15 15 AT<br />
15 15 15 15<br />
15 15 15 15<br />
19 19 19 D<br />
17 18 18 W<br />
17 17 17 17 AA<br />
17 17 17 17<br />
17 17 AB<br />
15 15 AU<br />
15 15 15 AW<br />
15 AY<br />
15 15 15 15 BA<br />
15<br />
17 Y<br />
17 17 17 AD<br />
17 AE<br />
17 17 17 17 AF<br />
17 17 17 17<br />
19 19 B<br />
19 E<br />
35 19 19 19 F<br />
35 35 35 19 19 19 G<br />
34 35 35 35<br />
35 19 19 19<br />
19 19 19 19<br />
19 19 19 19<br />
19 19 19 19<br />
19 K<br />
19 19 M<br />
19 19 19 P<br />
19 R<br />
18 18 U<br />
17 17 AG<br />
17 17 17 AJ<br />
17 AK<br />
17 17 17 17 AL<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42<br />
A<br />
C<br />
H<br />
19 19 19 J<br />
19 19 19 19 L<br />
ug475_c3_175_080911<br />
N<br />
V<br />
AC<br />
AH<br />
AN<br />
AV<br />
BB<br />
Figure 3-58:<br />
FF(G)1761 Package—XC7V585T I/O Banks<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 103<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-59<br />
31 31<br />
31<br />
31<br />
31 31 31<br />
31 31 31 31<br />
31<br />
31 31 31<br />
31 31 32 32<br />
31 31 31 32<br />
31 31 31 32<br />
31 31 31 31<br />
31<br />
31 31 31<br />
31 31 32 32<br />
31 31 31 32<br />
31 31<br />
31 31 31 31<br />
31<br />
31 31 31<br />
39 38 38 38 38 38 38 37 37 37 37 37<br />
39 39 39 39<br />
39 39<br />
39<br />
39 39 39 39<br />
39 39 39<br />
39 39 39<br />
39 38 38 38<br />
39 39 38 38<br />
39 38<br />
39 39 39 39<br />
39 39<br />
39 39 39 39<br />
39 39<br />
39 39 39<br />
32 32 32 32<br />
31 32 32 32<br />
31 31 32 32<br />
38 38 38 38<br />
38 38 38 38<br />
39 38 38 38<br />
38 38 38 36 36 36 36 36<br />
39 39 38 38 38 36 36 36<br />
39 39 39 38<br />
39 39 39 39<br />
32 32 32 33<br />
32 33 33 33<br />
32 32 33 33<br />
32 32 32 32<br />
32 32 32 32<br />
32 32 33 33<br />
32 32 32 33<br />
32 32 32 32<br />
32 32 32 32<br />
38 38 37 37<br />
38 38 38 38<br />
39 38 38 38<br />
36 36 36 36<br />
33 33 33 33<br />
12 12<br />
33 33 12 12<br />
33 33 33 33<br />
31 32 32 32 32 33 33 33<br />
36 36 36 36 36 36 36 36<br />
33 12 12 12<br />
33 33 12 12<br />
33 33 33 12<br />
33 33 33 33<br />
32 33 33 33<br />
32 32 33 33<br />
36 36 36 36<br />
12 12 12 12<br />
33 12 12 12<br />
33 33 12 12<br />
33 33 33 33<br />
33 33 33 33<br />
36 36 36 36<br />
38 38 36 36 36 36 36 36<br />
38 38 38 36<br />
38 38<br />
38 37 37 37 37 37 37 37<br />
38 36 36 36<br />
37 37 37 37<br />
38 38 37 37 37 37 37 37<br />
37 37 37 37<br />
36 36 36 36<br />
12 12 12 12<br />
12 12 13 13<br />
12 12 12 12<br />
12 12 12 12<br />
33 33 12 12<br />
36 36 34 34<br />
36 36 34 34<br />
36 36 34 34<br />
36 36<br />
37 37 37 37<br />
34 34 34<br />
14 14 14 14<br />
14<br />
12 14 14 14<br />
12 12 12 13<br />
12 12 13 13<br />
12 12 12 13<br />
12 12 12 12<br />
34 34 34 18<br />
16 16 16 16<br />
16<br />
16 16 16<br />
14 14 16 16<br />
14<br />
34 34 34 34<br />
34 34 34 34<br />
34 34 34 34<br />
34<br />
37 37 37 37<br />
37 37 37 37<br />
34 34<br />
34 34 18 18<br />
34 34 34<br />
14 14 14 16<br />
14 14 14 14<br />
14 14 14 14<br />
13 13 13 13<br />
12 13 13 13<br />
12 13 13 13<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
16 16<br />
34 34 34 34<br />
34 34 34 34<br />
13 13 13 13<br />
13 13 13 13<br />
13 13 13 13<br />
18 18 18 19<br />
18 18 18 18<br />
34 18 18 18<br />
34 34 18 18<br />
34 34<br />
37 35 35 35<br />
37 37 35 35<br />
37 37 37 37 37 37 37<br />
35 35 35 35<br />
35 34 34 35<br />
16 16 16 16<br />
14 14 14 16<br />
14 14 14 14<br />
14 14 14 14<br />
14 14 14 14<br />
13 13 13 13<br />
13 13 13 13<br />
13 13 13 13<br />
35 35 35 35<br />
35 35 35 35<br />
35 35 35 35<br />
34 34 19 19<br />
18 18 18 18<br />
16 16 16 16<br />
16 16 16 16<br />
18 18 18 18<br />
18 18 18 18<br />
35 35 35 35<br />
35 35 35 35<br />
35 35 35 35 35<br />
16 16 16 17<br />
16 16 16 16<br />
14 14 14 17<br />
14 14 14 14<br />
14 14 15 15<br />
14 14 14 15<br />
13 13 13 15<br />
13 15 15 15<br />
13 13 15 15<br />
13 13 13 15<br />
35 35 35 19<br />
18 18 18 19<br />
18 18 18 18<br />
18 18 18 18<br />
16 17 17 17<br />
16 16 17 17<br />
16 17 17 17<br />
16 17 17 17<br />
14 17 17 17<br />
15 15 15 15<br />
15 15 15 15<br />
13 15 15 15<br />
35 19 19<br />
18 18 18 18<br />
18 18 18 18<br />
15 15<br />
15 15 15<br />
15<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
19 19<br />
35 35 19 19<br />
19 19 19<br />
35 19 19 19<br />
35 19 19 19<br />
18 18<br />
17 18 18<br />
17 17 17 17<br />
17 17<br />
17 17 17 17<br />
15 15<br />
15 15 15<br />
15<br />
15 15 15 15<br />
15<br />
17<br />
17 17 17<br />
17<br />
17 17 17 17<br />
17 17<br />
17 17 17 17<br />
19<br />
35 35 35 19 19 19<br />
34 35 35 35<br />
19 19 19 19<br />
19 19 19 19<br />
19 19 19<br />
19<br />
19 19 19 19<br />
19 19<br />
19 19 19 19<br />
19 19 19<br />
19<br />
17 17 17<br />
17<br />
17 17 17 17<br />
Memory Groupings Pins<br />
# HP I/O<br />
# HR I/O<br />
# HP I/O − VCCAUX Group 0<br />
# HP I/O − VCCAUX Group 1<br />
# HP I/O − VCCAUX Group 2<br />
# HP I/O − VCCAUX Group 3<br />
# HP I/O − VCCAUX Group 4<br />
# HP I/O − VCCAUX Group 5<br />
# HP I/O − VCCAUX Group 6<br />
# HP I/O − VCCAUX Group 7<br />
# DQS pin<br />
# DCI pin<br />
# Memory Byte Group 0<br />
# Memory Byte Group 1<br />
# Memory Byte Group 2<br />
# Memory Byte Group 3<br />
# Bank Number<br />
ug475_c3_176_080911<br />
Figure 3-59:<br />
FF(G)1761 Package—XC7V585T Memory Groupings<br />
www.BDTIC.com/XILINX<br />
104 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 105<br />
<strong>UG475</strong> (v1.4) October 17, 2011<br />
Virtex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-60<br />
Figure 3-60:<br />
FF(G)1761 Package—XC7V585T Power <strong>and</strong> GND Placement<br />
11<br />
11<br />
11<br />
11<br />
11<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
11<br />
10<br />
10<br />
1<br />
1<br />
1<br />
2<br />
2<br />
2<br />
3<br />
3<br />
3<br />
4<br />
4<br />
4<br />
5<br />
5<br />
5<br />
14<br />
14<br />
14<br />
14<br />
14<br />
14<br />
14<br />
15<br />
15<br />
15<br />
15<br />
15<br />
15<br />
16<br />
16<br />
16<br />
16<br />
16<br />
16<br />
17<br />
17<br />
17<br />
17<br />
17<br />
17<br />
18<br />
18<br />
18<br />
18 18<br />
18<br />
19<br />
19<br />
19<br />
19<br />
19<br />
19<br />
19<br />
31<br />
31<br />
31<br />
31<br />
31<br />
31<br />
31<br />
32<br />
32<br />
32<br />
32<br />
32<br />
32<br />
33<br />
33<br />
33<br />
33<br />
33<br />
33<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
35<br />
35<br />
35<br />
35<br />
35<br />
35<br />
35<br />
36<br />
36<br />
36<br />
36<br />
36<br />
36<br />
36<br />
37<br />
37<br />
37<br />
37<br />
37<br />
37<br />
38<br />
38<br />
38<br />
38<br />
38<br />
38<br />
39<br />
39<br />
39<br />
39<br />
39<br />
39<br />
0<br />
0<br />
12<br />
12<br />
12<br />
12<br />
12<br />
12<br />
13<br />
13<br />
13<br />
13<br />
13<br />
13<br />
13<br />
1<br />
1<br />
2<br />
2<br />
3<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
6<br />
7<br />
7<br />
8<br />
8<br />
9<br />
9<br />
10<br />
10<br />
11<br />
11<br />
12<br />
12<br />
13<br />
13<br />
14<br />
14<br />
15<br />
15<br />
16<br />
16<br />
17<br />
17<br />
18<br />
18<br />
19<br />
19<br />
20<br />
20<br />
21<br />
21<br />
22<br />
22<br />
23<br />
23<br />
24<br />
24<br />
25<br />
25<br />
26<br />
26<br />
27<br />
27<br />
28<br />
28<br />
29<br />
29<br />
30<br />
30<br />
31<br />
31<br />
32<br />
32<br />
33<br />
33<br />
34<br />
34<br />
35<br />
35<br />
36<br />
36<br />
37<br />
37<br />
38<br />
38<br />
39<br />
39<br />
40<br />
40<br />
41<br />
41<br />
42<br />
42<br />
A<br />
A<br />
B<br />
B<br />
C<br />
C<br />
D<br />
D<br />
E<br />
E<br />
F<br />
F<br />
G<br />
G<br />
H<br />
H<br />
J<br />
J<br />
K<br />
K<br />
L<br />
L<br />
M<br />
M<br />
N<br />
N<br />
P<br />
P<br />
R<br />
R<br />
T<br />
T<br />
U<br />
U<br />
V<br />
V<br />
W<br />
W<br />
Y<br />
Y<br />
AA<br />
AA<br />
AB<br />
AB<br />
AC<br />
AC<br />
AD<br />
AD<br />
AE<br />
AE<br />
AF<br />
AF<br />
AG<br />
AG<br />
AH<br />
AH<br />
AJ<br />
AJ<br />
AK<br />
AK<br />
AL<br />
AL<br />
AM<br />
AM<br />
AN<br />
AN<br />
AP<br />
AP<br />
AR<br />
AR<br />
AT<br />
AT<br />
AU<br />
AU<br />
AV<br />
AV<br />
AW<br />
AW<br />
AY<br />
AY<br />
BA<br />
BA<br />
BB<br />
BB<br />
Power Pins<br />
# VCCO_#<br />
VCCINT<br />
VCCAUX<br />
# VCCAUX_IO_G#<br />
VCCBRAM<br />
VCCBATT_0<br />
VCCADC_0<br />
GNDADC_0<br />
MGTVCCAUX<br />
# MGTVCCAUX_G# or MGTHVCCAUX_G#<br />
MGTAVCC<br />
# MGTAVCC_G# or MGTHAVCC_G#<br />
MGTAVTT<br />
# MGTAVTT_G# or MGTHAVTT_G#<br />
GND<br />
ug475_c3_177_080911<br />
www.BDTIC.com/XILINX
106 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011<br />
Chapter 3: Device Diagrams<br />
FLG1925 Package—XC7V2000T<br />
X-Ref Target - Figure 3-61<br />
Figure 3-61:<br />
FLG1925 Package—XC7V2000T <strong>Pinout</strong> Diagram<br />
ug475_c3_200_090511<br />
User I/O Pins<br />
IO_LXXY_#<br />
s<br />
IO_XX_#<br />
Multi−Function Pins<br />
B<br />
ADV_B<br />
B<br />
FCS_B<br />
B<br />
FOE_B<br />
B<br />
MOSI<br />
B<br />
FWE_B<br />
B<br />
DOUT_CSO_B<br />
B<br />
CSI_B<br />
B<br />
PUDC_B<br />
U<br />
RDWR_B<br />
r<br />
RS0−RS1<br />
AD0P/AD0N−AD15P/AD15N<br />
EMCCLK<br />
VRN<br />
VRP<br />
VREF<br />
D00−D31<br />
A00−A28<br />
DQS<br />
MRCC<br />
SRCC<br />
Transceiver Pins<br />
E<br />
MGTAVCC_G#<br />
V<br />
MGTAVTT_G#<br />
V<br />
MGTVCCAUX_G#<br />
V<br />
MGTAVTTRCAL<br />
G<br />
MGTRREF<br />
MGTREFCLK1/0P<br />
MGTREFCLK1/0N<br />
MGTXRXP<br />
MGTXRXN<br />
MGTXTXP<br />
MGTXTXN<br />
E<br />
MGTHAVCC_G#<br />
V<br />
MGTHAVTT_G#<br />
MGTHRXP<br />
MGTHRXN<br />
MGTHTXP<br />
MGTHTXN<br />
Dedicated Pins<br />
C<br />
CCLK_0<br />
CFGBVS_0<br />
D<br />
DONE_0<br />
J<br />
DXP_0<br />
L<br />
DXN_0<br />
GNDADC_0<br />
Y<br />
INIT_B_0<br />
0 M0_0<br />
1 M1_0<br />
2 M2_0<br />
P<br />
PROGRAM_B_0<br />
K<br />
TCK_0<br />
I<br />
TDI_0<br />
O<br />
TDO_0<br />
M<br />
TMS_0<br />
VCCADC_0<br />
VCCBATT_0<br />
S<br />
VP_0<br />
S<br />
VN_0<br />
S<br />
VREFP_0<br />
S<br />
VREFN_0<br />
Other Pins<br />
GND<br />
VCCAUX_IO_G#<br />
VCCAUX<br />
VCCINT<br />
VCCO_#<br />
VCCBRAM<br />
n<br />
NC<br />
L<br />
J<br />
S<br />
S<br />
S<br />
S<br />
C K M<br />
I<br />
Y<br />
P<br />
D<br />
2<br />
0<br />
1<br />
O<br />
B<br />
B<br />
B<br />
U<br />
B<br />
B<br />
B<br />
B<br />
B<br />
r<br />
r<br />
V<br />
G<br />
V<br />
G<br />
V<br />
V<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
1<br />
1<br />
2<br />
2<br />
3<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
6<br />
7<br />
7<br />
8<br />
8<br />
9<br />
9<br />
10<br />
10<br />
11<br />
11<br />
12<br />
12<br />
13<br />
13<br />
14<br />
14<br />
15<br />
15<br />
16<br />
16<br />
17<br />
17<br />
18<br />
18<br />
19<br />
19<br />
20<br />
20<br />
21<br />
21<br />
22<br />
22<br />
23<br />
23<br />
24<br />
24<br />
25<br />
25<br />
26<br />
26<br />
27<br />
27<br />
28<br />
28<br />
29<br />
29<br />
30<br />
30<br />
31<br />
31<br />
32<br />
32<br />
33<br />
33<br />
34<br />
34<br />
35<br />
35<br />
36<br />
36<br />
37<br />
37<br />
38<br />
38<br />
39<br />
39<br />
40<br />
40<br />
41<br />
41<br />
42<br />
42<br />
43<br />
43<br />
44<br />
44<br />
A<br />
A<br />
B<br />
B<br />
C<br />
C<br />
D<br />
D<br />
E<br />
E<br />
F<br />
F<br />
G<br />
G<br />
H<br />
H<br />
J<br />
J<br />
K<br />
K<br />
L<br />
L<br />
M<br />
M<br />
N<br />
N<br />
P<br />
P<br />
R<br />
R<br />
T<br />
T<br />
U<br />
U<br />
V<br />
V<br />
W<br />
W<br />
Y<br />
Y<br />
AA<br />
AA<br />
AB<br />
AB<br />
AC<br />
AC<br />
AD<br />
AD<br />
AE<br />
AE<br />
AF<br />
AF<br />
AG<br />
AG<br />
AH<br />
AH<br />
AJ<br />
AJ<br />
AK<br />
AK<br />
AL<br />
AL<br />
AM<br />
AM<br />
AN<br />
AN<br />
AP<br />
AP<br />
AR<br />
AR<br />
AT<br />
AT<br />
AU<br />
AU<br />
AV<br />
AV<br />
AW<br />
AW<br />
AY<br />
AY<br />
BA<br />
BA<br />
BB<br />
BB<br />
BC<br />
BC<br />
BD<br />
BD<br />
www.BDTIC.com/XILINX
Virtex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-62<br />
A<br />
B<br />
C 39 39 39 39<br />
D 39<br />
38<br />
K 38 38 38<br />
M 38 38<br />
U 37 37<br />
37 37 37 37<br />
V 37 37 37 37<br />
W 37<br />
38 38 38 38<br />
Y 37 37 37<br />
38 38 38 39<br />
N 38 38 38 38<br />
P 38<br />
39<br />
E 39 39 39<br />
F<br />
G 39 39<br />
39 39 39 39<br />
R 38 38 38<br />
39 39 39<br />
39<br />
38 38 38 37 38 42 42 42<br />
37 37 37 37<br />
37 37 37 37<br />
37 37 37 37<br />
39 39 39<br />
39 39 39 39<br />
H 39 39 39 39<br />
J<br />
L<br />
T<br />
AA<br />
AB<br />
AC<br />
39 39 39 42<br />
39 39 39 39<br />
39 39 39 39<br />
38 38 38 38<br />
38 38 38 38<br />
39 42 42 42<br />
39 42 42 42<br />
39 39 42 42<br />
39 39 39 42<br />
39 42 42 42<br />
38 38 38 38<br />
38 38 38 38<br />
38 38 42 42<br />
38 38 38 38 38 38 38 42<br />
AD 115 115 115 115<br />
AE<br />
AH 114 114<br />
AP 113 113 113 113<br />
AT 113 113<br />
AY 112 112<br />
114 114<br />
AK 114 114 114 114<br />
AM 114 114<br />
37 37 37 37<br />
37 37<br />
37 37 37 37 37<br />
37 37 37<br />
37 37 37 37 37<br />
37 37 37 37<br />
115 115 115 115<br />
AF 115 115 115 115<br />
AG<br />
AJ<br />
AL<br />
AN<br />
AR<br />
AU<br />
113 113 113 113<br />
113 113<br />
112 112<br />
112 112<br />
112 112<br />
BB 112 112 112 112<br />
112 112<br />
113 113<br />
AV 113 113 113 113<br />
AW<br />
BA<br />
BC<br />
BD<br />
1<br />
1<br />
2<br />
2<br />
3<br />
115 115<br />
114 114<br />
114 114<br />
3<br />
4<br />
4<br />
5<br />
115 115<br />
114 114<br />
112 112<br />
5<br />
6<br />
6<br />
7<br />
115 115<br />
115 115<br />
114 114<br />
114 114<br />
113 113<br />
112 112<br />
112 112<br />
112 112<br />
7<br />
8<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44<br />
42 42 42 42<br />
31 31<br />
31 31 31 31<br />
31<br />
31 31 31<br />
31 31<br />
31 32 32 32<br />
31 31 32 32<br />
31 31 31<br />
31 31 31 31<br />
31<br />
31 31 31<br />
31 32 32 32<br />
31 31 32 32<br />
40 40 40 17<br />
40 40 17 17<br />
40 40 40 17<br />
17 17 17 18 18 18 19 19<br />
40 17 17 17<br />
40 40 40 17<br />
40 40 40 17<br />
31 31 31 32 32 32 33 33<br />
31 31<br />
31 31 31 31<br />
31<br />
42 42 42 41 41 41 40 40<br />
31 31 31<br />
31 32 32 32<br />
31 32 32 32<br />
31 31 31 32<br />
31 31<br />
42 41 41 41<br />
42 42 42 41<br />
41<br />
42 42 41 41<br />
42 42 42 42<br />
41 41 41 41<br />
42 41 41 41<br />
42 42 42 42<br />
115 115<br />
42 42 41 41<br />
41 41 41 40<br />
32 32 32 32<br />
32<br />
32<br />
41 41 41<br />
41 41 40 40<br />
32 32 33 33<br />
32 32 32 33<br />
32 32 32<br />
32 32 32 33<br />
32 32 32 32<br />
31 32 32 32<br />
41 40 40 40<br />
41 41 40 40<br />
41 41 41 40<br />
41 41 41 41<br />
42 41 41 41<br />
42 42 42 41<br />
42 41 41 41<br />
42 42 41 41<br />
40 40 40 40<br />
41 40 40 40<br />
40 40 40 40<br />
41 40 40 40<br />
41 41 40 40<br />
32 32 33 33<br />
32 32 33 33<br />
17 17 17 17<br />
17 17 17 17<br />
40 17 17 17<br />
40 40 17 17<br />
40 40 40 40<br />
33 33 33 33<br />
33 33 33<br />
32 33 33 33<br />
32 33 33 33<br />
17 17 17 17<br />
40 17 17 17<br />
33 33 33 34<br />
33 33 34 34<br />
33<br />
33 33 33 34<br />
33 33 33 33<br />
17 18 18 18<br />
17 17 17 18<br />
17 18 18 18<br />
17 17 18 18<br />
17 17 18 18<br />
17 17 17 18<br />
17 18 18 18<br />
17 17 18 18<br />
18 18 18 19<br />
18 18 18 19<br />
18 18 18 19<br />
18 18 18 18<br />
18 18 18 19<br />
18 18 18 18<br />
19 19 19 19<br />
18 18 19 19<br />
18 19 19 19<br />
18 19 19 19<br />
18 18 19 19<br />
19 19 19 19<br />
18 19 20 20<br />
17 17 17 18 18 18 20 20<br />
33 34 34 34<br />
33 33 34 34<br />
33 34 34 34<br />
33 33 34 34<br />
33 33 33 34<br />
33 33 33 33<br />
34 34 35 35<br />
34 34 34 35<br />
34 34 34 34<br />
34 34 35 35<br />
34 34 34 34<br />
34 34 34 35<br />
34 34 34 34<br />
33 34 34 34<br />
34 35 35 35<br />
34 34 35 35<br />
34 34 35 35<br />
34 34 34 35<br />
16 16 16 16<br />
16<br />
16 16 16<br />
15 15 15 15 15<br />
14 14 14 14<br />
14 14 14 14<br />
14 14<br />
35 35 35 35<br />
34 35 35 35<br />
34 35 35 35<br />
15 15<br />
15<br />
15 15 15<br />
14 14<br />
14 14 14 13<br />
35 35 36 36<br />
35 35 35 36<br />
35 35 35 36<br />
35 35 35 35<br />
35 35 35 36<br />
35 35 35 35<br />
19 19 22 22<br />
19 19 19 22<br />
19 19 19 19<br />
19 19 21 21<br />
19 19 19 20<br />
16 16 16 16<br />
16 16 16 16<br />
15 15 15 15<br />
15 15 15 15<br />
14 14 14 14<br />
14 13 13 13<br />
36 36 36 13<br />
19 22 22 22<br />
19 19 22 22<br />
19 19 19 21<br />
19 19 19 19<br />
20 20 20 20<br />
36 36 36 36<br />
35 36 36 36<br />
35 35 36 36<br />
19 21 21 21<br />
20 20 20 20<br />
20 20 20 20<br />
13 13 13 13<br />
36 13 13 13<br />
36 36 36 12<br />
36 36 36 36<br />
35 36 36 36<br />
35 36 36 36<br />
35 35 36 36<br />
36 11 11 11 11 11 11 11<br />
36 36 11 11<br />
36 36 36 11<br />
22 22 22 22<br />
21 21 21 21<br />
16 16 16 16<br />
16 16 16 16<br />
15 15 15 15<br />
15 15 15 15<br />
12 12 12 12<br />
11 11 11 11<br />
11 11 11 11<br />
36 11 11 11<br />
12 12 12 12<br />
36 12 12 12 12 12 12 12 12 12 AP<br />
36 36 12 12<br />
36 36 36<br />
36 36 36 36<br />
22 22 22 22<br />
22 22 22 22<br />
21 21 21 21<br />
21 21 21 21<br />
21 21 21 21<br />
20 20 20 20<br />
20 20 20 20<br />
16 16 16 16<br />
16 16 16 16 16 16 16 16<br />
14 14 14 14<br />
14 14 14 14<br />
13 13 13 14<br />
13 13 13 13<br />
13 13 13 13<br />
12 12 12 12<br />
22 22 22 22<br />
22 22 22 22<br />
15 15 15 15<br />
15 15 15 15<br />
14 14 14 14<br />
12 12 12 12<br />
12 12 12 12 12<br />
22 22 22 22<br />
15 15 15 14<br />
13 13 13 13<br />
13 13 13 13<br />
11 11 11 11<br />
11 11 11 11<br />
22 22 22 22<br />
21 21 21 21<br />
21 21 21 21<br />
21 21 21 21<br />
20 20 20 21<br />
20 20 20 20<br />
20 20 20 20<br />
16 16 16 16<br />
16 16 16 16<br />
15 15 15 15<br />
14 14 14 14<br />
14 14 14 14<br />
13 13 13 13<br />
11 11 11 11<br />
11 11 11 11<br />
11 11 11 11<br />
22<br />
22 22 22 22 C<br />
22 22 22 22<br />
21 21 21 21 H<br />
21 21 21 21<br />
20 20 20 20 N<br />
20 20 20 20<br />
16 16 16 16 V<br />
15 15 15 15 AC<br />
14 14 13 13 AH<br />
13 13 13 13<br />
12 13 13 13 AN<br />
12 12 12 12<br />
12 12 12 12<br />
20 20 20 T<br />
15 15 15 AA<br />
14 14 14 AF<br />
12 12 12 AT<br />
12 12 12 12 AV<br />
11 11 AW<br />
11 11 11 BA<br />
11 11 11<br />
22 22 D<br />
22 22 22 F<br />
21 G<br />
21 21<br />
21 M<br />
20 20 P<br />
20 U<br />
16 16 W<br />
15 AB<br />
14 14 AD<br />
14 AG<br />
13 13 AJ<br />
13 13 13 AL<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44<br />
A<br />
B<br />
E<br />
J<br />
K<br />
21 21 21 L<br />
R<br />
Y<br />
AE<br />
AK<br />
13 AM<br />
AR<br />
12 AU<br />
AY<br />
11 BB<br />
BC<br />
BD<br />
ug475_c3_201_052311<br />
Figure 3-62:<br />
FLG1925 Package—XC7V2000T I/O Banks<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 107<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-63<br />
A<br />
B<br />
C 39 39 39 39<br />
D 39<br />
38<br />
K 38 38 38<br />
M 38 38<br />
U 37 37<br />
37 37 37 37<br />
V 37 37 37 37<br />
W 37<br />
38 38 38 38<br />
Y 37 37 37<br />
38 38 38 39<br />
N 38 38 38 38<br />
P 38<br />
39<br />
E 39 39 39<br />
F<br />
G 39 39<br />
39 39 39 39<br />
R 38 38 38<br />
39 39 39<br />
39<br />
38 38 38 37 38 42 42 42<br />
37 37 37 37<br />
37 37 37 37<br />
37 37 37 37<br />
39 39 39<br />
39 39 39 39<br />
H 39 39 39 39<br />
J<br />
L<br />
T<br />
AA<br />
AB<br />
AC<br />
AD<br />
AE<br />
AF<br />
AG<br />
AH<br />
AJ<br />
AK<br />
AL<br />
AM<br />
AN<br />
AP<br />
AR<br />
AT<br />
AU<br />
AV<br />
AW<br />
AY<br />
BA<br />
BB<br />
BC<br />
BD<br />
1<br />
1<br />
2<br />
2<br />
3<br />
39 39 39 42<br />
39 39 39 39<br />
39 39 39 39<br />
38 38 38 38<br />
38 38 38 38<br />
39 42 42 42<br />
39 42 42 42<br />
39 39 42 42<br />
39 39 39 42<br />
39 42 42 42<br />
38 38 38 38<br />
38 38 38 38<br />
38 38 42 42<br />
38 38 38 38 38 38 38 42<br />
3<br />
4<br />
4<br />
5<br />
37 37 37 37<br />
37 37<br />
37 37 37 37 37<br />
37 37 37<br />
37 37 37 37 37<br />
5<br />
6<br />
6<br />
7<br />
37 37 37 37<br />
7<br />
8<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44<br />
42 42 42 42<br />
31 31<br />
31 31 31 31<br />
31<br />
31 31 31<br />
31 31<br />
31 32 32 32<br />
31 31 32 32<br />
31 31 31<br />
31 31 31 31<br />
31<br />
31 31 31<br />
31 32 32 32<br />
31 31 32 32<br />
40 40 40 17<br />
40 40 17 17<br />
40 40 40 17<br />
17 17 17 18 18 18 19 19<br />
40 17 17 17<br />
40 40 40 17<br />
40 40 40 17<br />
31 31 31 32 32 32 33 33<br />
31 31<br />
31 31 31 31<br />
31<br />
42 42 42 41 41 41 40 40<br />
31 31 31<br />
31 32 32 32<br />
31 32 32 32<br />
31 31 31 32<br />
31 31<br />
42 41 41 41<br />
42 42 42 41<br />
41<br />
42 42 41 41<br />
42 42 42 42<br />
41 41 41 41<br />
42 41 41 41<br />
42 42 42 42<br />
42 42 41 41<br />
41 41 41 40<br />
32 32 32 32<br />
32<br />
32<br />
41 41 41<br />
41 41 40 40<br />
32 32 33 33<br />
32 32 32 33<br />
32 32 32<br />
32 32 32 33<br />
32 32 32 32<br />
31 32 32 32<br />
41 40 40 40<br />
41 41 40 40<br />
41 41 41 40<br />
41 41 41 41<br />
42 41 41 41<br />
42 42 42 41<br />
42 41 41 41<br />
42 42 41 41<br />
40 40 40 40<br />
41 40 40 40<br />
40 40 40 40<br />
41 40 40 40<br />
41 41 40 40<br />
32 32 33 33<br />
32 32 33 33<br />
17 17 17 17<br />
17 17 17 17<br />
40 17 17 17<br />
40 40 17 17<br />
40 40 40 40<br />
33 33 33 33<br />
33 33 33<br />
32 33 33 33<br />
32 33 33 33<br />
17 17 17 17<br />
40 17 17 17<br />
33 33 33 34<br />
33 33 34 34<br />
33<br />
33 33 33 34<br />
33 33 33 33<br />
17 18 18 18<br />
17 17 17 18<br />
17 18 18 18<br />
17 17 18 18<br />
17 17 18 18<br />
17 17 17 18<br />
17 18 18 18<br />
17 17 18 18<br />
18 18 18 19<br />
18 18 18 19<br />
18 18 18 19<br />
18 18 18 18<br />
18 18 18 19<br />
18 18 18 18<br />
19 19 19 19<br />
18 18 19 19<br />
18 19 19 19<br />
18 19 19 19<br />
18 18 19 19<br />
19 19 19 19<br />
18 19 20 20<br />
17 17 17 18 18 18 20 20<br />
33 34 34 34<br />
33 33 34 34<br />
33 34 34 34<br />
33 33 34 34<br />
33 33 33 34<br />
33 33 33 33<br />
34 34 35 35<br />
34 34 34 35<br />
34 34 34 34<br />
34 34 35 35<br />
34 34 34 34<br />
34 34 34 35<br />
34 34 34 34<br />
33 34 34 34<br />
34 35 35 35<br />
34 34 35 35<br />
34 34 35 35<br />
34 34 34 35<br />
16 16 16 16<br />
16<br />
16 16 16<br />
15 15 15 15 15<br />
14 14 14 14<br />
14 14 14 14<br />
14 14<br />
35 35 35 35<br />
34 35 35 35<br />
34 35 35 35<br />
15 15<br />
15<br />
15 15 15<br />
14 14<br />
14 14 14 13<br />
35 35 36 36<br />
35 35 35 36<br />
35 35 35 36<br />
35 35 35 35<br />
35 35 35 36<br />
35 35 35 35<br />
19 19 22 22<br />
19 19 19 22<br />
19 19 19 19<br />
19 19 21 21<br />
19 19 19 20<br />
16 16 16 16<br />
16 16 16 16<br />
15 15 15 15<br />
15 15 15 15<br />
14 14 14 14<br />
14 13 13 13<br />
36 36 36 13<br />
19 22 22 22<br />
19 19 22 22<br />
19 19 19 21<br />
19 19 19 19<br />
20 20 20 20<br />
36 36 36 36<br />
35 36 36 36<br />
35 35 36 36<br />
19 21 21 21<br />
20 20 20 20<br />
20 20 20 20<br />
13 13 13 13<br />
36 13 13 13<br />
36 36 36 12<br />
36 36 36 36<br />
35 36 36 36<br />
35 36 36 36<br />
35 35 36 36<br />
36 11 11 11 11 11 11 11<br />
36 36 11 11<br />
36 36 36 11<br />
22 22 22 22<br />
21 21 21 21<br />
16 16 16 16<br />
16 16 16 16<br />
15 15 15 15<br />
15 15 15 15<br />
12 12 12 12<br />
11 11 11 11<br />
11 11 11 11<br />
36 11 11 11<br />
12 12 12 12<br />
36 12 12 12 12 12 12 12 12 12 AP<br />
36 36 12 12<br />
36 36 36<br />
36 36 36 36<br />
22 22 22 22<br />
22 22 22 22<br />
21 21 21 21<br />
21 21 21 21<br />
21 21 21 21<br />
20 20 20 20<br />
20 20 20 20<br />
16 16 16 16<br />
16 16 16 16 16 16 16 16<br />
14 14 14 14<br />
14 14 14 14<br />
13 13 13 14<br />
13 13 13 13<br />
13 13 13 13<br />
12 12 12 12<br />
22 22 22 22<br />
22 22 22 22<br />
15 15 15 15<br />
15 15 15 15<br />
14 14 14 14<br />
12 12 12 12<br />
12 12 12 12 12<br />
22 22 22 22<br />
15 15 15 14<br />
13 13 13 13<br />
13 13 13 13<br />
11 11 11 11<br />
11 11 11 11<br />
22 22 22 22<br />
21 21 21 21<br />
21 21 21 21<br />
21 21 21 21<br />
20 20 20 21<br />
20 20 20 20<br />
20 20 20 20<br />
16 16 16 16<br />
16 16 16 16<br />
15 15 15 15<br />
14 14 14 14<br />
14 14 14 14<br />
13 13 13 13<br />
11 11 11 11<br />
11 11 11 11<br />
11 11 11 11<br />
22<br />
22 22 22 22 C<br />
22 22 22 22<br />
21 21 21 21 H<br />
21 21 21 21<br />
20 20 20 20 N<br />
20 20 20 20<br />
16 16 16 16 V<br />
15 15 15 15 AC<br />
14 14 13 13 AH<br />
13 13 13 13<br />
12 13 13 13 AN<br />
12 12 12 12<br />
12 12 12 12<br />
20 20 20 T<br />
15 15 15 AA<br />
14 14 14 AF<br />
12 12 12 AT<br />
12 12 12 12 AV<br />
11 11 AW<br />
11 11 11 BA<br />
11 11 11<br />
22 22 D<br />
22 22 22 F<br />
21 G<br />
21 21<br />
21 M<br />
20 20 P<br />
20 U<br />
16 16 W<br />
15 AB<br />
14 14 AD<br />
14 AG<br />
13 13 AJ<br />
13 13 13 AL<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44<br />
Memory Groupings Pins<br />
A<br />
B<br />
E<br />
J<br />
K<br />
21 21 21 L<br />
R<br />
Y<br />
AE<br />
AK<br />
13 AM<br />
AR<br />
12 AU<br />
AY<br />
11 BB<br />
BC<br />
BD<br />
# HP I/O<br />
# HR I/O<br />
# HP I/O − VCCAUX Group 0<br />
# HP I/O − VCCAUX Group 1<br />
# HP I/O − VCCAUX Group 2<br />
# HP I/O − VCCAUX Group 3<br />
# HP I/O − VCCAUX Group 4<br />
# HP I/O − VCCAUX Group 5<br />
# HP I/O − VCCAUX Group 6<br />
# HP I/O − VCCAUX Group 7<br />
# DQS pin<br />
# DCI pin<br />
# Memory Byte Group 0<br />
# Memory Byte Group 1<br />
# Memory Byte Group 2<br />
# Memory Byte Group 3<br />
# Bank Number<br />
ug475_c3_202_052311<br />
Figure 3-63:<br />
FLG1925 Package—XC7V2000T Memory Groupings<br />
www.BDTIC.com/XILINX<br />
108 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Virtex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-64<br />
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44<br />
A<br />
39<br />
41<br />
18<br />
22<br />
A<br />
B 39<br />
41<br />
17<br />
19<br />
22 B<br />
C<br />
42<br />
40<br />
19<br />
22<br />
C<br />
D<br />
39<br />
41<br />
18<br />
22<br />
D<br />
E<br />
39<br />
41<br />
17<br />
22 22 E<br />
F 39<br />
42<br />
40<br />
19<br />
22<br />
F<br />
G<br />
39<br />
40<br />
18<br />
21<br />
G<br />
H<br />
39<br />
41<br />
18<br />
21<br />
H<br />
J 38<br />
42<br />
17<br />
19<br />
21<br />
J<br />
K<br />
42<br />
40<br />
19<br />
21<br />
K<br />
L<br />
38<br />
41<br />
18<br />
21<br />
L<br />
M 38<br />
42<br />
17<br />
19<br />
21 M<br />
N<br />
38<br />
40<br />
19 20<br />
N<br />
P<br />
38<br />
40<br />
18<br />
20<br />
P<br />
R<br />
38<br />
41<br />
17<br />
20 20 R<br />
T 37<br />
42<br />
17<br />
20 20<br />
T<br />
U<br />
37<br />
7<br />
3<br />
16<br />
U<br />
V<br />
37<br />
7<br />
3<br />
16<br />
V<br />
W 37<br />
7<br />
3<br />
16 16 W<br />
Y<br />
37<br />
6<br />
2 16 16<br />
Y<br />
AA<br />
37<br />
6<br />
2<br />
15<br />
AA<br />
AB<br />
0<br />
6<br />
2<br />
15 15 AB<br />
AC<br />
0<br />
5<br />
1<br />
15 15<br />
AC<br />
AD<br />
11<br />
5<br />
1<br />
15<br />
AD<br />
AE<br />
11<br />
5<br />
1<br />
14 14 AE<br />
AF 11<br />
11<br />
4<br />
0<br />
14 14<br />
AF<br />
AG<br />
4<br />
0<br />
14<br />
AG<br />
AH<br />
11<br />
4<br />
0<br />
13<br />
AH<br />
AJ<br />
11<br />
31<br />
34<br />
13 13 AJ<br />
AK 11<br />
11<br />
33<br />
14<br />
13<br />
AK<br />
AL<br />
32<br />
35<br />
13<br />
AL<br />
AM<br />
11<br />
31<br />
34<br />
36<br />
13 AM<br />
AN<br />
11<br />
31<br />
33<br />
36<br />
12<br />
AN<br />
AP 10<br />
10<br />
32<br />
35<br />
12<br />
AP<br />
AR<br />
32<br />
34<br />
12 12 AR<br />
AT<br />
10 31<br />
33<br />
36<br />
12<br />
AT<br />
AU<br />
10<br />
33<br />
35<br />
12<br />
AU<br />
AV 10<br />
10<br />
32<br />
34<br />
12<br />
AV<br />
AW<br />
31<br />
34<br />
36<br />
11 AW<br />
AY<br />
10<br />
33<br />
35<br />
11<br />
AY<br />
BA<br />
10<br />
32<br />
35<br />
11<br />
BA<br />
BB 10<br />
10<br />
31<br />
34<br />
36<br />
11 BB<br />
BC<br />
31<br />
33<br />
36<br />
11<br />
BC<br />
BD<br />
32<br />
35<br />
11<br />
BD<br />
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44<br />
Power Pins<br />
# VCCO_#<br />
VCCINT<br />
VCCAUX<br />
# VCCAUX_IO_G#<br />
VCCBRAM<br />
VCCBATT_0<br />
VCCADC_0<br />
GNDADC_0<br />
MGTVCCAUX<br />
# MGTVCCAUX_G# or MGTHVCCAUX_G#<br />
MGTAVCC<br />
# MGTAVCC_G# or MGTHAVCC_G#<br />
MGTAVTT<br />
# MGTAVTT_G# or MGTHAVTT_G#<br />
GND<br />
ug475_c3_203_052311<br />
Figure 3-64:<br />
FLG1925 Package—XC7V2000T Power <strong>and</strong> GND Placement<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 109<br />
<strong>UG475</strong> (v1.4) October 17, 2011
110 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011<br />
Chapter 3: Device Diagrams<br />
FHG1761 Package—XC7V2000T<br />
X-Ref Target - Figure 3-65<br />
Figure 3-65:<br />
FHG1761 Package—XC7V2000T <strong>Pinout</strong> Diagram<br />
ug475_c3_204_090511<br />
User I/O Pins<br />
IO_LXXY_#<br />
s<br />
IO_XX_#<br />
Multi−Function Pins<br />
B<br />
ADV_B<br />
B<br />
FCS_B<br />
B<br />
FOE_B<br />
B<br />
MOSI<br />
B<br />
FWE_B<br />
B<br />
DOUT_CSO_B<br />
B<br />
CSI_B<br />
B<br />
PUDC_B<br />
U<br />
RDWR_B<br />
r<br />
RS0−RS1<br />
AD0P/AD0N−AD15P/AD15N<br />
EMCCLK<br />
VRN<br />
VRP<br />
VREF<br />
D00−D31<br />
A00−A28<br />
DQS<br />
MRCC<br />
SRCC<br />
Transceiver Pins<br />
E<br />
MGTAVCC_G#<br />
V<br />
MGTAVTT_G#<br />
V<br />
MGTVCCAUX_G#<br />
V<br />
MGTAVTTRCAL<br />
G<br />
MGTRREF<br />
MGTREFCLK1/0P<br />
MGTREFCLK1/0N<br />
MGTXRXP<br />
MGTXRXN<br />
MGTXTXP<br />
MGTXTXN<br />
E<br />
MGTHAVCC_G#<br />
V<br />
MGTHAVTT_G#<br />
MGTHRXP<br />
MGTHRXN<br />
MGTHTXP<br />
MGTHTXN<br />
Dedicated Pins<br />
C<br />
CCLK_0<br />
CFGBVS_0<br />
D<br />
DONE_0<br />
J<br />
DXP_0<br />
L<br />
DXN_0<br />
GNDADC_0<br />
Y<br />
INIT_B_0<br />
0 M0_0<br />
1 M1_0<br />
2 M2_0<br />
P<br />
PROGRAM_B_0<br />
K<br />
TCK_0<br />
I<br />
TDI_0<br />
O<br />
TDO_0<br />
M<br />
TMS_0<br />
VCCADC_0<br />
VCCBATT_0<br />
S<br />
VP_0<br />
S<br />
VN_0<br />
S<br />
VREFP_0<br />
S<br />
VREFN_0<br />
Other Pins<br />
GND<br />
VCCAUX_IO_G#<br />
VCCAUX<br />
VCCINT<br />
VCCO_#<br />
VCCBRAM<br />
n<br />
NC<br />
L<br />
J<br />
S<br />
S<br />
S<br />
S<br />
C<br />
K<br />
M<br />
I<br />
Y<br />
P<br />
D<br />
2<br />
0<br />
1<br />
O<br />
B<br />
B<br />
B<br />
U<br />
B<br />
B<br />
B<br />
B<br />
B<br />
r<br />
r<br />
V<br />
G<br />
V<br />
G<br />
V<br />
G<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
1<br />
1<br />
2<br />
2<br />
3<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
6<br />
7<br />
7<br />
8<br />
8<br />
9<br />
9<br />
10<br />
10<br />
11<br />
11<br />
12<br />
12<br />
13<br />
13<br />
14<br />
14<br />
15<br />
15<br />
16<br />
16<br />
17<br />
17<br />
18<br />
18<br />
19<br />
19<br />
20<br />
20<br />
21<br />
21<br />
22<br />
22<br />
23<br />
23<br />
24<br />
24<br />
25<br />
25<br />
26<br />
26<br />
27<br />
27<br />
28<br />
28<br />
29<br />
29<br />
30<br />
30<br />
31<br />
31<br />
32<br />
32<br />
33<br />
33<br />
34<br />
34<br />
35<br />
35<br />
36<br />
36<br />
37<br />
37<br />
38<br />
38<br />
39<br />
39<br />
40<br />
40<br />
41<br />
41<br />
42<br />
42<br />
A<br />
A<br />
B<br />
B<br />
C<br />
C<br />
D<br />
D<br />
E<br />
E<br />
F<br />
F<br />
G<br />
G<br />
H<br />
H<br />
J<br />
J<br />
K<br />
K<br />
L<br />
L<br />
M<br />
M<br />
N<br />
N<br />
P<br />
P<br />
R<br />
R<br />
T<br />
T<br />
U<br />
U<br />
V<br />
V<br />
W<br />
W<br />
Y<br />
Y<br />
AA<br />
AA<br />
AB<br />
AB<br />
AC<br />
AC<br />
AD<br />
AD<br />
AE<br />
AE<br />
AF<br />
AF<br />
AG<br />
AG<br />
AH<br />
AH<br />
AJ<br />
AJ<br />
AK<br />
AK<br />
AL<br />
AL<br />
AM<br />
AM<br />
AN<br />
AN<br />
AP<br />
AP<br />
AR<br />
AR<br />
AT<br />
AT<br />
AU<br />
AU<br />
AV<br />
AV<br />
AW<br />
AW<br />
AY<br />
AY<br />
BA<br />
BA<br />
BB<br />
BB<br />
www.BDTIC.com/XILINX
Virtex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-66<br />
A<br />
B<br />
C 119 119<br />
D<br />
E 119 119<br />
F<br />
G 118 118<br />
H<br />
J 118 118<br />
K<br />
R 116 116<br />
U 116 116<br />
W 115 115<br />
AG 114 114<br />
AJ 114 114<br />
AL 113 113<br />
AN 113 113<br />
AR 112 112<br />
115 115<br />
AA 115 115 115 115<br />
AC 115 115<br />
AE 115 115<br />
117 117<br />
116 116<br />
116 116<br />
116 116<br />
115 115<br />
114 114<br />
114 114<br />
114 114<br />
114 114<br />
113 113<br />
113 113<br />
117 117<br />
L 117 117 117 117<br />
M<br />
N 117 117<br />
P<br />
T<br />
V<br />
Y<br />
AB<br />
AD<br />
AF<br />
AH<br />
AK<br />
AM<br />
AP<br />
AT<br />
112 112<br />
AW 111 111 111 111<br />
111 111 111 111<br />
BA 111 111 111 111<br />
112 112<br />
112 112 112 112<br />
AU 112 112 112 112<br />
AV<br />
AY<br />
BB<br />
1<br />
1<br />
2<br />
2<br />
3<br />
119 119<br />
119 119<br />
118 118<br />
118 118<br />
117 117<br />
113 113<br />
113 113<br />
113 113<br />
112 112 112 112<br />
111 111 111 111<br />
3<br />
4<br />
4<br />
5<br />
119 119<br />
119 119<br />
118 118<br />
118 118<br />
117 117<br />
116 116<br />
116 116<br />
116 116<br />
115 115<br />
114 114<br />
114 114<br />
113 113<br />
5<br />
6<br />
6<br />
7<br />
119 119<br />
119 119<br />
118 118<br />
118 118<br />
117 117<br />
117 117<br />
117 117<br />
116 116<br />
116 116<br />
115 115<br />
115 115<br />
114 114<br />
114 114<br />
113 113<br />
113 113<br />
7<br />
8<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42<br />
119 119<br />
119 119<br />
118 118<br />
118 118<br />
112 112<br />
118 118<br />
112 112<br />
111 111<br />
111 111<br />
115<br />
31 31<br />
31<br />
31<br />
31 31 31<br />
31 31 31 31<br />
31<br />
115<br />
31 31 31<br />
31 31 32 32<br />
31 31 31 32<br />
31 31 31 32<br />
31 31 31 31<br />
31<br />
31 31 31<br />
31 31 32 32<br />
31 31 31 32<br />
31 31<br />
31 31 31 31<br />
31<br />
31 31 31<br />
39 38 38 38 38 38 38 37 37 37 37 37<br />
39<br />
39 39 39 39<br />
39 39<br />
39 39 39 39<br />
39 39 39<br />
39 39 39<br />
39 39 39<br />
39 38 38 38<br />
39 39 38 38<br />
39 38<br />
39 39 39 39<br />
39 39 39 39<br />
39 39<br />
39 39 39 39<br />
32 32 32 32<br />
31 32 32 32<br />
31 31 32 32<br />
38 38 38 38<br />
38 38 38 38<br />
39 38 38 38<br />
38 38 38 36 36 36 36 36<br />
39 39 38 38 38 36 36 36<br />
39 39 39 38<br />
39 39 39 39<br />
32 32 32 33<br />
32 33 33 33<br />
32 32 33 33<br />
32 32 32 32<br />
32 32 32 32<br />
32 32 33 33<br />
32 32 32 33<br />
32 32 32 32<br />
32 32 32 32<br />
38 38 37 37<br />
38 38 38 38<br />
39 38 38 38<br />
36 36 36 36<br />
33 33 33 33<br />
12 12<br />
33 33 12 12<br />
33 33 33 33<br />
31 32 32 32 32 33 33 33<br />
36 36 36 36 36 36 36 36<br />
33 12 12 12<br />
33 33 12 12<br />
33 33 33 12<br />
33 33 33 33<br />
32 33 33 33<br />
32 32 33 33<br />
36 36 36 36<br />
12 12 12 12<br />
33 12 12 12<br />
33 33 12 12<br />
33 33 33 33<br />
33 33 33 33<br />
36 36 36 36<br />
38 38 36 36 36 36 36 36<br />
38 38 38 36<br />
38 38<br />
38 37 37 37 37 37 37 37<br />
38 36 36 36<br />
37 37 37 37<br />
38 38 37 37 37 37 37 37<br />
37 37 37 37<br />
36 36 36 36<br />
12 12 12 12<br />
12 12 13 13<br />
12 12 12 12<br />
12 12 12 12<br />
33 33 12 12<br />
36 36 34 34<br />
36 36 34 34<br />
36 36 34 34<br />
36 36<br />
37 37 37 37<br />
34 34 34<br />
14 14 14 14<br />
14<br />
12 14 14 14<br />
12 12 12 13<br />
12 12 13 13<br />
12 12 12 13<br />
12 12 12 12<br />
34 34 34 18<br />
16 16 16 16<br />
16<br />
16 16 16<br />
14 14 16 16<br />
14<br />
34 34 34 34<br />
34 34 34 34<br />
34 34 34 34<br />
34<br />
37 37 37 37<br />
37 37 37 37<br />
34 34<br />
34 34 18 18<br />
34 34 34<br />
14 14 14 16<br />
14 14 14 14<br />
14 14 14 14<br />
13 13 13 13<br />
12 13 13 13<br />
12 13 13 13<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
16 16<br />
34 34 34 34<br />
34 34 34 34<br />
13 13 13 13<br />
13 13 13 13<br />
13 13 13 13<br />
18 18 18 19<br />
18 18 18 18<br />
34 18 18 18<br />
34 34 18 18<br />
34 34<br />
37 35 35 35<br />
37 37 35 35<br />
37 37 37 37 37 37 37<br />
35 35 35 35<br />
35 34 34 35<br />
16 16 16 16<br />
14 14 14 16<br />
14 14 14 14<br />
14 14 14 14<br />
14 14 14 14<br />
13 13 13 13<br />
13 13 13 13<br />
13 13 13 13<br />
35 35 35 35<br />
35 35 35 35<br />
35 35 35 35<br />
34 34 19 19<br />
18 18 18 18<br />
16 16 16 16<br />
16 16 16 16<br />
18 18 18 18<br />
18 18 18 18<br />
35 35 35 35<br />
35 35 35 35<br />
35 35 35 35 35<br />
16 16 16 17<br />
16 16 16 16<br />
14 14 14 17<br />
14 14 14 14<br />
14 14 15 15<br />
14 14 14 15<br />
13 13 13 15<br />
13 15 15 15<br />
13 13 15 15<br />
13 13 13 15<br />
35 35 35 19<br />
18 18 18 19<br />
18 18 18 18<br />
18 18 18 18<br />
16 17 17 17<br />
16 16 17 17<br />
16 17 17 17<br />
16 17 17 17<br />
14 17 17 17<br />
15 15 15 15<br />
15 15 15 15<br />
13 15 15 15<br />
35 19 19<br />
35 35 19 19<br />
18 18 18 18 T<br />
18 18 18 18<br />
15 15 AM<br />
15 15 15 AP<br />
15 AR<br />
15 15 15 15 AT<br />
15 15 15 15<br />
15 15 15 15<br />
19 19 19 D<br />
17 18 18 W<br />
17 17 17 17 AA<br />
17 17 17 17<br />
17 17 AB<br />
15 15 AU<br />
15 15 15 AW<br />
15 AY<br />
15 15 15 15 BA<br />
15<br />
17 Y<br />
17 17 17 AD<br />
17 AE<br />
17 17 17 17 AF<br />
17 17 17 17<br />
19 19 B<br />
19 E<br />
35 19 19 19 F<br />
35 35 35 19 19 19 G<br />
34 35 35 35<br />
35 19 19 19<br />
19 19 19 19<br />
19 19 19 19<br />
19 19 19 19<br />
19 K<br />
19 19 M<br />
19 19 19 P<br />
19 R<br />
18 18 U<br />
17 17 AG<br />
17 17 17 AJ<br />
17 AK<br />
17 17 17 17 AL<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42<br />
A<br />
C<br />
H<br />
19 19 19 J<br />
19 19 19 19 L<br />
N<br />
V<br />
AC<br />
AH<br />
AN<br />
AV<br />
BB<br />
ug475_c3_205_052311<br />
Figure 3-66:<br />
FHG1761 Package—XC7V2000T I/O Banks<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 111<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-67<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42<br />
A<br />
39 38 38 38 38 38 38 37 37 37 37 37<br />
37 37 37 37<br />
35 35 35 35<br />
35 19 19<br />
A<br />
B<br />
39<br />
39 38 38 38<br />
38 37 37 37 37 37 37 37<br />
37 35 35 35<br />
35 35 35 35<br />
19 19<br />
B<br />
C<br />
39 39 39 39<br />
38 38 38 38<br />
37 37 37 37<br />
37 37 37 37<br />
35 35 35 35<br />
35 35 19 19<br />
C<br />
D<br />
39 39<br />
39 39 38 38<br />
38 38 37 37 37 37 37 37<br />
37 37 35 35<br />
35 35 35 35<br />
19 19 19<br />
D<br />
E<br />
39 39 39 39<br />
38 38 38 38<br />
37 37 37 37<br />
37 37 37 37<br />
35 35 35 35<br />
35 35 35 19<br />
19<br />
E<br />
F<br />
39 39 39<br />
39 38<br />
38 38 37 37<br />
37 37 37 37 37 37 37<br />
35 35 35 35 35<br />
35 19 19 19<br />
F<br />
G<br />
39 39 39<br />
39 38 38 38<br />
36 36 36 36 36 36 36 36<br />
35 35 35 35<br />
35 35 35 19 19 19 G<br />
H<br />
39 39 39 39<br />
38 38 38 36 36 36 36 36<br />
36 36 34 34<br />
35 34 34 35<br />
35 19 19 19<br />
H<br />
J<br />
39 39 39<br />
39 39 38 38 38 36 36 36<br />
36 36 36 36<br />
34 34 34 34<br />
34 35 35 35<br />
19 19 19<br />
J<br />
K<br />
39 39 39 39<br />
38 38 38 38<br />
36 36 36 36<br />
36 36 34 34<br />
34 34 34 34<br />
19 19 19 19<br />
19<br />
K<br />
L<br />
39 39<br />
39 39 39 38<br />
38 38 36 36 36 36 36 36<br />
34 34 34 34<br />
34 34 19 19<br />
19 19 19 19<br />
L<br />
M<br />
39 39 39 39<br />
39 38 38 38<br />
36 36 36 36<br />
36 36 34 34<br />
34 34 34 34<br />
19 19 19 19<br />
19 19 M<br />
N<br />
39 39 39 39<br />
38 38 38 36<br />
36 36 36 36<br />
34 34 34 34<br />
18 18 18 19<br />
19 19 19 19<br />
N<br />
P<br />
38 38<br />
38 36 36 36<br />
36 36<br />
34<br />
34 34 18 18<br />
18 18 18 18<br />
19 19 19<br />
P<br />
R<br />
34 34 34<br />
18 18 18 18<br />
18 18 18 19<br />
19<br />
R<br />
T<br />
34 34 34 18<br />
18 18 18 18<br />
18 18 18 18<br />
T<br />
U<br />
34 34<br />
34 18 18 18<br />
18 18 18 18<br />
18 18<br />
U<br />
V<br />
34 34 34<br />
18 18 18 18<br />
18 18 18 18<br />
V<br />
W<br />
34 34 18 18<br />
18 18 18 18<br />
17 18 18 W<br />
Y<br />
34 34<br />
16 16 16 16<br />
16 17 17 17<br />
17<br />
Y<br />
AA<br />
16 16 16 16<br />
16 16 16 16<br />
17 17 17 17 AA<br />
AB<br />
16<br />
16 16 16 16<br />
16 16 17 17<br />
17 17 AB<br />
AC<br />
16 16 16<br />
16 16 16 16<br />
17 17 17 17<br />
AC<br />
AD<br />
16 16 16 16<br />
16 16 16 17<br />
17 17 17 AD<br />
AE<br />
16 16<br />
16 16 16 16<br />
16 17 17 17<br />
17 AE<br />
AF<br />
14 14 16 16<br />
16 16 16 16<br />
17 17 17 17 AF<br />
AG<br />
14<br />
14 14 14 16<br />
16 17 17 17<br />
17 17 AG<br />
AH<br />
14 14 14 14<br />
14 14 14 16<br />
17 17 17 17<br />
AH<br />
AJ<br />
31 31<br />
31 31 32 32<br />
33 33 33 33<br />
12 12<br />
14<br />
14 14 14 14<br />
14 14 14 17<br />
17 17 17 AJ<br />
AK<br />
31<br />
31 31 31<br />
32 32 32 33<br />
33 33 12 12<br />
12 14 14 14<br />
14 14 14 14<br />
14 17 17 17<br />
17 AK<br />
AL<br />
31<br />
31 31 31 32<br />
32 33 33 33<br />
33 12 12 12<br />
14 14 14 14<br />
14 14 14 14<br />
17 17 17 17 AL<br />
AM<br />
31 31 31 31<br />
32 32 32 32<br />
33 33 33 33<br />
12 12 12 12<br />
14 14 14 14<br />
14 14 15 15<br />
15 15 AM<br />
AN<br />
31<br />
31 31 31 32<br />
32 32 33 33<br />
33 33 12 12<br />
12 12 13 13<br />
14 14 14 14<br />
15 15 15 15<br />
AN<br />
AP<br />
31 31 31<br />
31 32 32 32 32 33 33 33<br />
12 12 12 12<br />
13 13 13 13<br />
14 14 14 15<br />
15 15 15 AP<br />
AR<br />
31 31 31 31<br />
32 32 32 32<br />
33 33 33 12<br />
12 12 12 13<br />
13 13 13 13<br />
15 15 15 15<br />
15 AR<br />
AT<br />
31<br />
31 31 32 32<br />
32 32 33 33<br />
33 12 12 12<br />
12 13 13 13<br />
13 13 13 15<br />
15 15 15 15 AT<br />
AU<br />
31 31 31<br />
32 32 32 32<br />
33 33 33 33<br />
12 12 12 12<br />
13 13 13 13<br />
13 15 15 15<br />
15 15 AU<br />
AV<br />
31 31 31 32<br />
32 32 32 33<br />
33 33 12 12<br />
12 12 13 13<br />
13 13 13 13<br />
15 15 15 15<br />
AV<br />
AW<br />
31 31<br />
31 32 32 32<br />
32 33 33 33<br />
12 12 12 12<br />
13 13 13 13<br />
13 13 15 15<br />
15 15 15 AW<br />
AY<br />
31 31 31 31<br />
32 32 32 32<br />
33 33 33 33<br />
12 12 12 13<br />
13 13 13 13<br />
15 15 15 15<br />
15 AY<br />
BA<br />
31<br />
31 31 32 32<br />
32 32 33 33<br />
33 33 12 12<br />
12 13 13 13<br />
13 13 13 15<br />
15 15 15 15 BA<br />
BB<br />
31 31 31<br />
32 32 32 32<br />
33 33 33 33<br />
12 12 12 12<br />
13 13 13 13<br />
13 15 15 15<br />
15<br />
BB<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42<br />
Memory Groupings Pins<br />
# HP I/O<br />
# HR I/O<br />
# HP I/O − VCCAUX Group 0<br />
# HP I/O − VCCAUX Group 1<br />
# HP I/O − VCCAUX Group 2<br />
# HP I/O − VCCAUX Group 3<br />
# HP I/O − VCCAUX Group 4<br />
# HP I/O − VCCAUX Group 5<br />
# HP I/O − VCCAUX Group 6<br />
# HP I/O − VCCAUX Group 7<br />
# DQS pin<br />
# DCI pin<br />
# Memory Byte Group 0<br />
# Memory Byte Group 1<br />
# Memory Byte Group 2<br />
# Memory Byte Group 3<br />
# Bank Number<br />
ug475_c3_206_052311<br />
Figure 3-67:<br />
FHG1761 Package—XC7V2000T Memory Groupings<br />
www.BDTIC.com/XILINX<br />
112 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 113<br />
<strong>UG475</strong> (v1.4) October 17, 2011<br />
Virtex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-68<br />
Figure 3-68:<br />
FHG1761 Package—XC7V2000T Power <strong>and</strong> GND Placement<br />
11<br />
11<br />
11<br />
11<br />
11<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
11<br />
10<br />
10<br />
0<br />
0<br />
1<br />
1<br />
1<br />
2<br />
2<br />
2<br />
3<br />
3<br />
3<br />
4<br />
4<br />
4<br />
5<br />
5<br />
5<br />
14<br />
14<br />
14<br />
14<br />
14<br />
14<br />
14<br />
15<br />
15<br />
15<br />
15<br />
15<br />
15<br />
16<br />
16<br />
16<br />
16<br />
16<br />
16<br />
17<br />
17<br />
17<br />
17<br />
17<br />
17<br />
18<br />
18<br />
18<br />
18 18<br />
18<br />
19<br />
19<br />
19<br />
19<br />
19<br />
19<br />
19<br />
31<br />
31<br />
31<br />
31<br />
31<br />
31<br />
31<br />
32<br />
32<br />
32<br />
32<br />
32<br />
32<br />
33<br />
33<br />
33<br />
33<br />
33<br />
33<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
35<br />
35<br />
35<br />
35<br />
35<br />
35<br />
35<br />
36<br />
36<br />
36<br />
36<br />
36<br />
36<br />
36<br />
37<br />
37<br />
37<br />
37<br />
37<br />
37<br />
38<br />
38<br />
38<br />
38<br />
38<br />
38<br />
39<br />
39<br />
39<br />
39<br />
39<br />
39<br />
0<br />
0<br />
12<br />
12<br />
12<br />
12<br />
12<br />
12<br />
13<br />
13<br />
13<br />
13<br />
13<br />
13<br />
13<br />
1<br />
1<br />
2<br />
2<br />
3<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
6<br />
7<br />
7<br />
8<br />
8<br />
9<br />
9<br />
10<br />
10<br />
11<br />
11<br />
12<br />
12<br />
13<br />
13<br />
14<br />
14<br />
15<br />
15<br />
16<br />
16<br />
17<br />
17<br />
18<br />
18<br />
19<br />
19<br />
20<br />
20<br />
21<br />
21<br />
22<br />
22<br />
23<br />
23<br />
24<br />
24<br />
25<br />
25<br />
26<br />
26<br />
27<br />
27<br />
28<br />
28<br />
29<br />
29<br />
30<br />
30<br />
31<br />
31<br />
32<br />
32<br />
33<br />
33<br />
34<br />
34<br />
35<br />
35<br />
36<br />
36<br />
37<br />
37<br />
38<br />
38<br />
39<br />
39<br />
40<br />
40<br />
41<br />
41<br />
42<br />
42<br />
A<br />
A<br />
B<br />
B<br />
C<br />
C<br />
D<br />
D<br />
E<br />
E<br />
F<br />
F<br />
G<br />
G<br />
H<br />
H<br />
J<br />
J<br />
K<br />
K<br />
L<br />
L<br />
M<br />
M<br />
N<br />
N<br />
P<br />
P<br />
R<br />
R<br />
T<br />
T<br />
U<br />
U<br />
V<br />
V<br />
W<br />
W<br />
Y<br />
Y<br />
AA<br />
AA<br />
AB<br />
AB<br />
AC<br />
AC<br />
AD<br />
AD<br />
AE<br />
AE<br />
AF<br />
AF<br />
AG<br />
AG<br />
AH<br />
AH<br />
AJ<br />
AJ<br />
AK<br />
AK<br />
AL<br />
AL<br />
AM<br />
AM<br />
AN<br />
AN<br />
AP<br />
AP<br />
AR<br />
AR<br />
AT<br />
AT<br />
AU<br />
AU<br />
AV<br />
AV<br />
AW<br />
AW<br />
AY<br />
AY<br />
BA<br />
BA<br />
BB<br />
BB<br />
Power Pins<br />
# VCCO_#<br />
VCCINT<br />
VCCAUX<br />
# VCCAUX_IO_G#<br />
VCCBRAM<br />
VCCBATT_0<br />
VCCADC_0<br />
GNDADC_0<br />
MGTVCCAUX<br />
# MGTVCCAUX_G# or MGTHVCCAUX_G#<br />
MGTAVCC<br />
# MGTAVCC_G# or MGTHAVCC_G#<br />
MGTAVTT<br />
# MGTAVTT_G# or MGTHAVTT_G#<br />
GND<br />
ug475_c3_207_052311<br />
www.BDTIC.com/XILINX
114 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011<br />
Chapter 3: Device Diagrams<br />
FFG1157 Package—XC7VX485T<br />
X-Ref Target - Figure 3-69<br />
Figure 3-69:<br />
FFG1157 Package—XC7VX485T <strong>Pinout</strong> Diagram<br />
ug475_c3_100_090511<br />
User I/O Pins<br />
IO_LXXY_#<br />
s<br />
IO_XX_#<br />
Multi−Function Pins<br />
B<br />
ADV_B<br />
B<br />
FCS_B<br />
B<br />
FOE_B<br />
B<br />
MOSI<br />
B<br />
FWE_B<br />
B<br />
DOUT_CSO_B<br />
B<br />
CSI_B<br />
B<br />
PUDC_B<br />
U<br />
RDWR_B<br />
r<br />
RS0−RS1<br />
AD0P/AD0N−AD15P/AD15N<br />
EMCCLK<br />
VRN<br />
VRP<br />
VREF<br />
D00−D31<br />
A00−A28<br />
DQS<br />
MRCC<br />
SRCC<br />
Transceiver Pins<br />
E<br />
MGTAVCC_G#<br />
V<br />
MGTAVTT_G#<br />
V<br />
MGTVCCAUX_G#<br />
V<br />
MGTAVTTRCAL<br />
G<br />
MGTRREF<br />
MGTREFCLK1/0P<br />
MGTREFCLK1/0N<br />
MGTXRXP<br />
MGTXRXN<br />
MGTXTXP<br />
MGTXTXN<br />
E<br />
MGTHAVCC_G#<br />
V<br />
MGTHAVTT_G#<br />
MGTHRXP<br />
MGTHRXN<br />
MGTHTXP<br />
MGTHTXN<br />
Dedicated Pins<br />
C<br />
CCLK_0<br />
CFGBVS_0<br />
D<br />
DONE_0<br />
J<br />
DXP_0<br />
L<br />
DXN_0<br />
GNDADC_0<br />
Y<br />
INIT_B_0<br />
0 M0_0<br />
1 M1_0<br />
2 M2_0<br />
P<br />
PROGRAM_B_0<br />
K<br />
TCK_0<br />
I<br />
TDI_0<br />
O<br />
TDO_0<br />
M<br />
TMS_0<br />
VCCADC_0<br />
VCCBATT_0<br />
S<br />
VP_0<br />
S<br />
VN_0<br />
S<br />
VREFP_0<br />
S<br />
VREFN_0<br />
Other Pins<br />
GND<br />
VCCAUX_IO_G#<br />
VCCAUX<br />
VCCINT<br />
VCCO_#<br />
VCCBRAM<br />
n<br />
NC<br />
L<br />
J<br />
S<br />
S<br />
S<br />
S<br />
C<br />
K<br />
M<br />
O<br />
I<br />
Y<br />
P<br />
D<br />
2<br />
0<br />
1<br />
B<br />
B<br />
B<br />
U<br />
B<br />
B<br />
B<br />
B<br />
B<br />
r<br />
r<br />
V<br />
G<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
n<br />
n<br />
1<br />
1<br />
2<br />
2<br />
3<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
6<br />
7<br />
7<br />
8<br />
8<br />
9<br />
9<br />
10<br />
10<br />
11<br />
11<br />
12<br />
12<br />
13<br />
13<br />
14<br />
14<br />
15<br />
15<br />
16<br />
16<br />
17<br />
17<br />
18<br />
18<br />
19<br />
19<br />
20<br />
20<br />
21<br />
21<br />
22<br />
22<br />
23<br />
23<br />
24<br />
24<br />
25<br />
25<br />
26<br />
26<br />
27<br />
27<br />
28<br />
28<br />
29<br />
29<br />
30<br />
30<br />
31<br />
31<br />
32<br />
32<br />
33<br />
33<br />
34<br />
34<br />
A<br />
A<br />
B<br />
B<br />
C<br />
C<br />
D<br />
D<br />
E<br />
E<br />
F<br />
F<br />
G<br />
G<br />
H<br />
H<br />
J<br />
J<br />
K<br />
K<br />
L<br />
L<br />
M<br />
M<br />
N<br />
N<br />
P<br />
P<br />
R<br />
R<br />
T<br />
T<br />
U<br />
U<br />
V<br />
V<br />
W<br />
W<br />
Y<br />
Y<br />
AA<br />
AA<br />
AB<br />
AB<br />
AC<br />
AC<br />
AD<br />
AD<br />
AE<br />
AE<br />
AF<br />
AF<br />
AG<br />
AG<br />
AH<br />
AH<br />
AJ<br />
AJ<br />
AK<br />
AK<br />
AL<br />
AL<br />
AM<br />
AM<br />
AN<br />
AN<br />
AP<br />
AP<br />
www.BDTIC.com/XILINX
Virtex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-70<br />
A<br />
B 118 118<br />
C<br />
D 118 118<br />
E<br />
F 117 117<br />
G<br />
H 117 117<br />
J<br />
K 117 117<br />
L<br />
M 117 117<br />
N<br />
P 116 116<br />
R<br />
AB 115 115<br />
AD 115 115<br />
AK 114 114<br />
AM 114 114<br />
115 115<br />
115 115<br />
114 114<br />
114 114<br />
114 114<br />
115 115<br />
115 115<br />
AF 115 115 115 115<br />
AH 115 115<br />
116 116<br />
T 116 116 116 116<br />
U<br />
V 116 116<br />
W<br />
Y 116 116<br />
AA<br />
AC<br />
AE<br />
AG<br />
AJ<br />
AL<br />
AN<br />
1<br />
114 114<br />
114 114<br />
114 114<br />
AP 114 114 114 114 115<br />
1<br />
2<br />
2<br />
3<br />
118 118<br />
118 118<br />
118 118<br />
118 118<br />
117 117<br />
117 117<br />
117 117<br />
116 116<br />
116 116<br />
116 116<br />
115 115<br />
3<br />
4<br />
4<br />
5<br />
118 118<br />
118 118<br />
118 118<br />
118 118<br />
117 117<br />
117 117<br />
117 117<br />
116 116<br />
5<br />
6<br />
6<br />
7<br />
115<br />
7<br />
8<br />
39 39 39 39<br />
39 39 39<br />
34 34<br />
34 34<br />
34<br />
34 34 34 34<br />
34 34 34 34<br />
34<br />
34 34 34<br />
34 34 35 35<br />
34 34 34 35<br />
34 34 34 34<br />
34 34<br />
34 34 34 34<br />
34 34 35 35<br />
34 34 34 35<br />
34 34 34 34<br />
34 34<br />
34<br />
34 34 34<br />
39 39 38 38 38 37 37 37<br />
39 39 39 38 38 38 37 37<br />
34 34 35 35<br />
38 38 38 37<br />
37 37 19 19<br />
37 37 37 19<br />
37 37 37 19<br />
37 19 19 19<br />
37 37 18 18<br />
18 18 18 18<br />
16 16 16<br />
35 35 36 36 36 15 15 15<br />
35 35 35 35<br />
35 35 35 35<br />
34 35 35 35<br />
35 35 35 36<br />
35 35 35 35<br />
35 35 35 35<br />
35 35 35 36<br />
35 35 35 35<br />
35 35 35 35<br />
38 37 37 37<br />
39 39 39 39 38 38 38 38 38 37 37<br />
39 39 39 39<br />
39 39 39 39 38 38<br />
39 39 39 39<br />
39<br />
39 39 39<br />
39 38 38 38 38 38<br />
39 39 39 38<br />
39 39 39 39<br />
39 39<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
39 39 39<br />
39 39 39 39<br />
38 38 38 38<br />
38 38 38 38<br />
38 38 38 38<br />
39 38 38 38<br />
38 38 38 37<br />
38 38 38 38<br />
38 38 38 38<br />
37 37 37 37<br />
37 37 37 37<br />
37 37 37 37<br />
37<br />
36 36 36 36<br />
35 36 36 36<br />
35 35 35 36<br />
35 36 36 36<br />
35 35 36 36<br />
37 37 37 37<br />
38 37 37 37<br />
37 37 37 37<br />
17 17 17 17 17 17 17<br />
17 17<br />
17<br />
36 36 15 15<br />
36 36 36 36<br />
36 36 36 36<br />
19 19 19 18<br />
17 17 17 17<br />
17 17 17<br />
16 16 16 16<br />
16<br />
16 16 16 16<br />
15 15 15 15<br />
36 14 14 15<br />
36 36 14 14<br />
14 15 15 15<br />
36 14 14 14<br />
36 36 14 14<br />
36 36 36 14<br />
19 19 19 19<br />
37 19 19 19<br />
37 37 19 19<br />
36 36 36 36<br />
36 36 36 36<br />
36 36 36 36<br />
19 19 19 19<br />
19 19 19 18<br />
17 17 17 17<br />
17 17 17 17<br />
14 14 14 14<br />
14 14 14 14<br />
36 14 14 14<br />
19 19 19 19<br />
18 18 18 18<br />
18 18 18 18 18 18 18 18 K<br />
18 18 18 18<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
19 19 19 19<br />
19 18 18 18 18 18 F<br />
18 18 18 18<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
15 15 15 15<br />
14 14 15 15<br />
14 14 14 14<br />
14 14 14 14<br />
19 19 19 19 19 B<br />
19 19 19 19<br />
18 18 18 18<br />
17 17 17 17<br />
17 17 17 17<br />
17 17 17 17<br />
16 17 17 17<br />
16 16 16 16<br />
16 16 16 16<br />
19 18 18 18 E<br />
18 18 18 18<br />
19<br />
19 19 19 C<br />
18 18 18 H<br />
18 18<br />
17 17 17 N<br />
17 17 17 17 R<br />
16 16 16 V<br />
16 16 16 16<br />
14 14 14 14 AK<br />
14 14 14 14<br />
14 14 AL<br />
14 14 14 AN<br />
14 14 14 14 14<br />
15 AD<br />
15 15 15 15 AE<br />
15 15 15 15<br />
19 D<br />
18<br />
17 P<br />
17 17 T<br />
16 W<br />
16 16 16 16 Y<br />
16 16 AA<br />
16 16 16 AC<br />
15 15 AF<br />
15 15 15 AH<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
A<br />
G<br />
J<br />
L<br />
M<br />
U<br />
AB<br />
AG<br />
15 AJ<br />
AM<br />
AP<br />
ug475_c3_101_052311<br />
Figure 3-70:<br />
FFG1157 Package—XC7VX485T I/O Banks<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 115<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-71<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
A<br />
39 39 39 39<br />
38 38 38 38<br />
38 37 37 37<br />
37 37 19 19<br />
19 19 19 19<br />
19<br />
A<br />
B<br />
39 39 39<br />
39 38 38 38 38 38<br />
37 37 37 37<br />
19 19 19 19<br />
19 19 19 19 19<br />
B<br />
C<br />
39 39 39 39 38 38 38 38 38 37 37<br />
37 37 37 19<br />
19 19 19 19<br />
19 19 19<br />
C<br />
D<br />
39 39 39 39<br />
38 38 38 38<br />
37 37 37 37<br />
37 19 19 19<br />
19 19 19 19<br />
19<br />
D<br />
E<br />
39 39 39 39 38 38<br />
38 38 38 37<br />
37 37 37 19<br />
19 19 19 19<br />
19 18 18 18<br />
E<br />
F<br />
39 39 39 39<br />
38 38 38 38<br />
38 37 37 37<br />
37 19 19 19<br />
19 18 18 18 18 18<br />
F<br />
G<br />
39<br />
39 39 39 38<br />
38 38 38 38<br />
37 37 37 37<br />
19 19 19 18<br />
18 18 18 18<br />
G<br />
H<br />
39 39 39<br />
39 39 38 38 38 37 37 37<br />
37 37 19 19<br />
18 18 18 18<br />
18 18 18<br />
H<br />
J<br />
39 39 39 39<br />
38 38 38 38<br />
37 37 37 37<br />
19 19 19 18<br />
18 18 18 18<br />
18<br />
J<br />
K<br />
39 39<br />
39 39 39 38 38 38 37 37<br />
37 37 18 18<br />
18 18 18 18 18 18 18 18<br />
K<br />
L<br />
39 39 39<br />
39 38 38 38<br />
37 37 37 37<br />
18 18 18 18<br />
18 18 18 18<br />
18 18<br />
L<br />
M<br />
39 39 39 39<br />
38 38 38 37<br />
37<br />
18 18 18 18<br />
17 17 17 17<br />
M<br />
N<br />
17 17 17 17 17 17 17<br />
17 17 17<br />
N<br />
P<br />
17 17 17 17<br />
17 17 17 17<br />
17<br />
P<br />
R<br />
17 17<br />
17 17 17 17<br />
17 17 17 17<br />
R<br />
T<br />
17 17 17<br />
17 17 17 17<br />
17 17<br />
T<br />
U<br />
17<br />
17 17 17 17<br />
16 17 17 17<br />
U<br />
V<br />
16 16 16<br />
16 16 16 16<br />
16 16 16<br />
V<br />
W<br />
16 16 16 16<br />
16 16 16 16<br />
16 W<br />
Y<br />
16<br />
16 16 16 16<br />
16 16 16 16<br />
Y<br />
AA<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 AA<br />
AB<br />
16 16 16 16<br />
16 16 16 16<br />
AB<br />
AC<br />
34 34<br />
34<br />
35 35 36 36 36 15 15 15<br />
15 15 15 15<br />
16 16 16 AC<br />
AD<br />
34 34 34 34<br />
35 35 35 35<br />
36 36 36 36<br />
15 15 15 15<br />
15 15 15 15<br />
15 AD<br />
AE<br />
34 34<br />
34 34 35 35<br />
35 35 35 36<br />
36 36 15 15<br />
15 15 15 15<br />
15 15 15 15 AE<br />
AF<br />
34 34 34 34<br />
35 35 35 35<br />
35 36 36 36<br />
36 14 14 15<br />
15 15 15 15<br />
15 15 AF<br />
AG<br />
34<br />
34 34 34 35<br />
35 35 35 35<br />
36 36 36 36<br />
14 15 15 15<br />
15 15 15 15<br />
AG<br />
AH<br />
34 34 34<br />
34 34 35 35<br />
35 35 35 36<br />
36 36 14 14<br />
15 15 15 15<br />
15 15 15 AH<br />
AJ<br />
34 34 34 34<br />
35 35 35 35<br />
36 36 36 36<br />
36 14 14 14<br />
14 14 15 15<br />
15 AJ<br />
AK<br />
34 34<br />
34 34 34 35<br />
35 35 35 36<br />
36 36 36 36<br />
14 14 14 14<br />
14 14 14 14 AK<br />
AL<br />
34 34 34 34<br />
34 35 35 35<br />
35 36 36 36<br />
36 36 14 14<br />
14 14 14 14<br />
14 14 AL<br />
AM<br />
34 34 34 34<br />
35 35 35 35<br />
36 36 36 36<br />
14 14 14 14<br />
14 14 14 14<br />
AM<br />
AN<br />
34 34<br />
34 34 35 35<br />
35 35 36 36<br />
36 36 36 14<br />
14 14 14 14<br />
14 14 14 AN<br />
AP<br />
34<br />
34 34 34<br />
35 35 35 35<br />
36 36 36 36<br />
36 14 14 14<br />
14 14 14 14 14<br />
AP<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
Memory Groupings Pins<br />
# HP I/O<br />
# HR I/O<br />
# HP I/O − VCCAUX Group 0<br />
# HP I/O − VCCAUX Group 1<br />
# HP I/O − VCCAUX Group 2<br />
# HP I/O − VCCAUX Group 3<br />
# HP I/O − VCCAUX Group 4<br />
# HP I/O − VCCAUX Group 5<br />
# HP I/O − VCCAUX Group 6<br />
# HP I/O − VCCAUX Group 7<br />
# DQS pin<br />
# DCI pin<br />
# Memory Byte Group 0<br />
# Memory Byte Group 1<br />
# Memory Byte Group 2<br />
# Memory Byte Group 3<br />
# Bank Number<br />
ug475_c3_102_052311<br />
Figure 3-71:<br />
FFG1157 Package—XC7VX485T Memory Groupings<br />
www.BDTIC.com/XILINX<br />
116 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Virtex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-72<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
A<br />
38<br />
37<br />
19<br />
A<br />
B<br />
39<br />
37<br />
19<br />
B<br />
C<br />
11<br />
11<br />
38<br />
19<br />
C<br />
D<br />
11<br />
38<br />
37<br />
19<br />
D<br />
E<br />
11<br />
39<br />
37<br />
19<br />
E<br />
F<br />
38<br />
19<br />
F<br />
G<br />
11<br />
11<br />
38<br />
19<br />
18<br />
G<br />
H<br />
11<br />
39<br />
37<br />
18<br />
H<br />
J<br />
11<br />
39<br />
37<br />
18<br />
J<br />
K<br />
38<br />
18<br />
K<br />
L<br />
11<br />
11<br />
39<br />
18 18<br />
L<br />
M<br />
11<br />
39<br />
37<br />
18<br />
M<br />
N<br />
11<br />
3<br />
1<br />
17<br />
N<br />
P<br />
17 17<br />
P<br />
R<br />
10<br />
10<br />
3<br />
1<br />
17<br />
R<br />
T<br />
10<br />
17<br />
T<br />
U<br />
10<br />
3<br />
1<br />
16<br />
17<br />
U<br />
V<br />
16<br />
V<br />
W<br />
10<br />
10<br />
0<br />
2<br />
0<br />
16<br />
W<br />
Y<br />
10<br />
16<br />
Y<br />
AA<br />
10<br />
2<br />
0<br />
16<br />
AA<br />
AB<br />
0<br />
16<br />
AB<br />
AC<br />
10<br />
10<br />
2<br />
35<br />
0<br />
15<br />
AC<br />
AD<br />
10<br />
34<br />
15 15<br />
AD<br />
AE<br />
10<br />
34<br />
36<br />
15<br />
AE<br />
AF<br />
35<br />
15<br />
AF<br />
AG<br />
10<br />
10<br />
35<br />
14<br />
15 AG<br />
AH<br />
10<br />
34<br />
36<br />
15<br />
AH<br />
AJ<br />
10<br />
34<br />
35<br />
14<br />
AJ<br />
AK<br />
35<br />
36<br />
AK<br />
AL<br />
10<br />
10<br />
34<br />
36<br />
14<br />
AL<br />
AM<br />
10<br />
34<br />
36<br />
14<br />
AM<br />
AN<br />
10<br />
35<br />
14<br />
AN<br />
AP<br />
34<br />
36<br />
14 AP<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
Power Pins<br />
# VCCO_#<br />
VCCINT<br />
VCCAUX<br />
# VCCAUX_IO_G#<br />
VCCBRAM<br />
VCCBATT_0<br />
VCCADC_0<br />
GNDADC_0<br />
MGTVCCAUX<br />
# MGTVCCAUX_G# or MGTHVCCAUX_G#<br />
MGTAVCC<br />
# MGTAVCC_G# or MGTHAVCC_G#<br />
MGTAVTT<br />
# MGTAVTT_G# or MGTHAVTT_G#<br />
GND<br />
ug475_c3_103_052311<br />
Figure 3-72:<br />
FFG1157 Package—XC7VX485T Power <strong>and</strong> GND Placement<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 117<br />
<strong>UG475</strong> (v1.4) October 17, 2011
118 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011<br />
Chapter 3: Device Diagrams<br />
FFG1158 Package—XC7VX485T<br />
X-Ref Target - Figure 3-73<br />
Figure 3-73:<br />
FFG1158 Package—XC7VX485T <strong>Pinout</strong> Diagram<br />
ug475_c3_104_090511<br />
User I/O Pins<br />
IO_LXXY_#<br />
s<br />
IO_XX_#<br />
Multi−Function Pins<br />
B<br />
ADV_B<br />
B<br />
FCS_B<br />
B<br />
FOE_B<br />
B<br />
MOSI<br />
B<br />
FWE_B<br />
B<br />
DOUT_CSO_B<br />
B<br />
CSI_B<br />
B<br />
PUDC_B<br />
U<br />
RDWR_B<br />
r<br />
RS0−RS1<br />
AD0P/AD0N−AD15P/AD15N<br />
EMCCLK<br />
VRN<br />
VRP<br />
VREF<br />
D00−D31<br />
A00−A28<br />
DQS<br />
MRCC<br />
SRCC<br />
Transceiver Pins<br />
E<br />
MGTAVCC_G#<br />
V<br />
MGTAVTT_G#<br />
V<br />
MGTVCCAUX_G#<br />
V<br />
MGTAVTTRCAL<br />
G<br />
MGTRREF<br />
MGTREFCLK1/0P<br />
MGTREFCLK1/0N<br />
MGTXRXP<br />
MGTXRXN<br />
MGTXTXP<br />
MGTXTXN<br />
E<br />
MGTHAVCC_G#<br />
V<br />
MGTHAVTT_G#<br />
MGTHRXP<br />
MGTHRXN<br />
MGTHTXP<br />
MGTHTXN<br />
Dedicated Pins<br />
C<br />
CCLK_0<br />
CFGBVS_0<br />
D<br />
DONE_0<br />
J<br />
DXP_0<br />
L<br />
DXN_0<br />
GNDADC_0<br />
Y<br />
INIT_B_0<br />
0 M0_0<br />
1 M1_0<br />
2 M2_0<br />
P<br />
PROGRAM_B_0<br />
K<br />
TCK_0<br />
I<br />
TDI_0<br />
O<br />
TDO_0<br />
M<br />
TMS_0<br />
VCCADC_0<br />
VCCBATT_0<br />
S<br />
VP_0<br />
S<br />
VN_0<br />
S<br />
VREFP_0<br />
S<br />
VREFN_0<br />
Other Pins<br />
GND<br />
VCCAUX_IO_G#<br />
VCCAUX<br />
VCCINT<br />
VCCO_#<br />
VCCBRAM<br />
n<br />
NC<br />
L<br />
J<br />
S<br />
S<br />
S<br />
S<br />
C<br />
K<br />
M<br />
O<br />
I<br />
Y<br />
P<br />
D<br />
2<br />
0<br />
1<br />
B<br />
B<br />
B<br />
U<br />
B<br />
B<br />
B<br />
B<br />
B<br />
r<br />
r<br />
V<br />
G<br />
V<br />
G<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
1<br />
1<br />
2<br />
2<br />
3<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
6<br />
7<br />
7<br />
8<br />
8<br />
9<br />
9<br />
10<br />
10<br />
11<br />
11<br />
12<br />
12<br />
13<br />
13<br />
14<br />
14<br />
15<br />
15<br />
16<br />
16<br />
17<br />
17<br />
18<br />
18<br />
19<br />
19<br />
20<br />
20<br />
21<br />
21<br />
22<br />
22<br />
23<br />
23<br />
24<br />
24<br />
25<br />
25<br />
26<br />
26<br />
27<br />
27<br />
28<br />
28<br />
29<br />
29<br />
30<br />
30<br />
31<br />
31<br />
32<br />
32<br />
33<br />
33<br />
34<br />
34<br />
A<br />
A<br />
B<br />
B<br />
C<br />
C<br />
D<br />
D<br />
E<br />
E<br />
F<br />
F<br />
G<br />
G<br />
H<br />
H<br />
J<br />
J<br />
K<br />
K<br />
L<br />
L<br />
M<br />
M<br />
N<br />
N<br />
P<br />
P<br />
R<br />
R<br />
T<br />
T<br />
U<br />
U<br />
V<br />
V<br />
W<br />
W<br />
Y<br />
Y<br />
AA<br />
AA<br />
AB<br />
AB<br />
AC<br />
AC<br />
AD<br />
AD<br />
AE<br />
AE<br />
AF<br />
AF<br />
AG<br />
AG<br />
AH<br />
AH<br />
AJ<br />
AJ<br />
AK<br />
AK<br />
AL<br />
AL<br />
AM<br />
AM<br />
AN<br />
AN<br />
AP<br />
AP<br />
www.BDTIC.com/XILINX
Virtex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-74<br />
A<br />
B 119 119<br />
C<br />
D<br />
E<br />
116 116 116 116<br />
Y 116 116<br />
AB 116 116<br />
AD 115 115<br />
AK 114 114 114 114<br />
AM 114 114<br />
115 115<br />
114 114<br />
114 114<br />
115 115<br />
114 114<br />
AF 115 115 115 115<br />
AH 115 115<br />
117 117<br />
117 117<br />
P 117 117 117 117<br />
T 117 117<br />
118 118<br />
117 117<br />
117 117<br />
115 115<br />
115 115<br />
115 115<br />
114 114<br />
AP 114 114 114 114<br />
15 15 15 15<br />
15<br />
15 15 15<br />
15 15 15 15<br />
15 15<br />
115 115<br />
116 116 116 116<br />
116 116<br />
116 116<br />
118 118<br />
H 118 118 118 118<br />
K 118 118<br />
M 118 118<br />
119 119<br />
119 119<br />
118 118<br />
119 119<br />
119 119 119 119<br />
F 119 119<br />
G<br />
J<br />
L<br />
N<br />
R<br />
U<br />
V<br />
W<br />
AA<br />
AC<br />
AE<br />
AG<br />
AJ<br />
AL<br />
AN<br />
1<br />
1<br />
2<br />
2<br />
3<br />
119 119<br />
3<br />
4<br />
4<br />
5<br />
118 118<br />
118 118<br />
117 117<br />
116 116<br />
5<br />
6<br />
6<br />
7<br />
119 119<br />
119 119<br />
118 118<br />
117 117<br />
117 117<br />
116 116<br />
115 115<br />
114 114<br />
7<br />
8<br />
15 15 15 15<br />
15 15<br />
15 15 15 15<br />
15<br />
15 15 15<br />
15 15 16 16 16 16 17 17<br />
15 15<br />
17 17 17 14<br />
14 14 14 14<br />
17 14 14 14<br />
14 14 14<br />
14<br />
14 14 14<br />
14<br />
14 14 14 14<br />
17 17 14 14 14 14<br />
17 17 17 14<br />
17 17 17 14<br />
14<br />
14 14 14 14<br />
14 14<br />
17 14 14 14<br />
15 15 15 16 16 16 16 17 17 17 14 14<br />
15<br />
15 15 15<br />
15 15 15<br />
15<br />
15 16 16 16<br />
15 15 16 16<br />
15 16 16 16<br />
15 16 16 16<br />
15 16 16 16<br />
15<br />
16 16 16 17<br />
16 16 16 16<br />
16<br />
16 16 16 16<br />
16 17 17 17<br />
16 16 17 17<br />
16 16 16 17<br />
16 16 16 16<br />
36 36 36 36<br />
36 36 36 36<br />
36 36<br />
36 36<br />
36 36 36 36<br />
36<br />
36 36 36 36<br />
36<br />
36 36 36<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
36 36 36 36<br />
16 16 16 16<br />
36 36 34 34<br />
36 36 36 34<br />
36 36 36 36<br />
36 36 36 36<br />
36<br />
17 17 17 17<br />
17 17 17 17<br />
17 17 17 17<br />
16 17 17 17<br />
17 17 17 17<br />
16 17 17 17<br />
34<br />
34 34 34 34<br />
34 34 34 34<br />
36 34 34 34<br />
36 36 34 34<br />
36 36 36 34<br />
34<br />
17 17 17 14<br />
34 34 34 35<br />
34 34 34 34<br />
34 34 34 34<br />
34 34 34 34<br />
36 34 34 34<br />
14 14 14<br />
14<br />
14 14 14 14<br />
34 35 35 35<br />
34 34 35 35<br />
34 34 34 35<br />
34 34 34 34<br />
34 35 35 35<br />
34 34 35 35<br />
14 14<br />
35 35 35 35<br />
14<br />
35 35 35<br />
35<br />
35 35 35 35<br />
35 35 35 35<br />
35 35 35 35<br />
35 35<br />
35 35 35 35<br />
35 35 35 35<br />
35 35 35<br />
215 215<br />
219 219<br />
219 219<br />
218 218<br />
217 217<br />
217 217<br />
216 216<br />
216 216<br />
215 215<br />
214 214<br />
35<br />
35 35 35 35<br />
218 218<br />
216 216 216 216<br />
216 216<br />
215 215<br />
214 214<br />
214 214 214 214 AK<br />
214 214<br />
215 215<br />
214 214<br />
214 214<br />
215 215 AD<br />
215 215 215 215 AF<br />
215 215<br />
217 217<br />
217 217<br />
217 217 217 217 P<br />
217 217<br />
218 218<br />
218 218 218 218 H<br />
218 218<br />
218 218<br />
219 219<br />
219 219 219 219 B<br />
219 219<br />
219 219 219 219<br />
219 219<br />
218 218<br />
217 217<br />
217 217<br />
216 216<br />
216 216<br />
216 216<br />
215 215<br />
215 215<br />
219 219 F<br />
218 218 K<br />
218 218 M<br />
217 217 T<br />
216 216 Y<br />
216 216 AB<br />
215 215 AH<br />
214 214 AM<br />
214 214 214 214 AP<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
A<br />
C<br />
D<br />
E<br />
G<br />
J<br />
L<br />
N<br />
R<br />
U<br />
V<br />
W<br />
AA<br />
AC<br />
AE<br />
AG<br />
AJ<br />
AL<br />
AN<br />
ug475_c3_105_052311<br />
Figure 3-74:<br />
FFG1158 Package—XC7VX485T I/O Banks<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 119<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-75<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
A<br />
15 15 15 15<br />
15 16 16 16<br />
17 17 17 17<br />
14 14 14 14<br />
A<br />
B<br />
15<br />
15 15 15 15<br />
16 16 16 17<br />
17 17 17 14<br />
14 14 14<br />
B<br />
C<br />
15 15 15<br />
15 15 16 16<br />
16 17 17 17<br />
17 14 14 14<br />
14<br />
C<br />
D<br />
15 15 15 15<br />
16 16 16 16<br />
17 17 17 17<br />
14 14 14 14<br />
D<br />
E<br />
15 15<br />
15 15 15<br />
16<br />
16 16 17 17<br />
17 17 14 14 14 14<br />
E<br />
F<br />
15 15<br />
15 16 16 16<br />
17 17 17 17<br />
14 14 14<br />
F<br />
G<br />
15 15 15 15<br />
16 16 16 17<br />
17 17 17 14<br />
14<br />
G<br />
H<br />
15<br />
15 16 16 16<br />
16 17 17 17<br />
14 14 14 14<br />
H<br />
J<br />
15 15 15<br />
16 16 16 16<br />
17 17 17 14<br />
14 14<br />
J<br />
K<br />
15 15 16 16 16 16 17 17<br />
17 14 14 14<br />
K<br />
L<br />
15 15<br />
16 16 16 16<br />
17 17 17 17<br />
14 14 14<br />
L<br />
M<br />
15 15 15 16 16 16 16 17 17 17 14 14<br />
14<br />
M<br />
N<br />
15<br />
15 16 16 16<br />
16 17 17 17<br />
14 14 14 14<br />
N<br />
P<br />
15 15 15<br />
16 16 16 16<br />
17 17 17 14<br />
14 14<br />
P<br />
R<br />
15<br />
15<br />
14<br />
14<br />
R<br />
T<br />
T<br />
U<br />
U<br />
V<br />
V<br />
W<br />
W<br />
Y<br />
Y<br />
AA<br />
AA<br />
AB<br />
AB<br />
AC<br />
AC<br />
AD<br />
36<br />
34<br />
34<br />
AD<br />
AE<br />
36 36 36 36<br />
34 34 34 34<br />
35 35 35 35<br />
AE<br />
AF<br />
36 36<br />
36 36 34 34<br />
34 34 34 35<br />
35 35 35<br />
AF<br />
AG<br />
36 36 36 36<br />
34 34 34 34<br />
34 35 35 35<br />
35<br />
AG<br />
AH<br />
36<br />
36 36 36 34<br />
34 34 34 34<br />
35 35 35 35<br />
AH<br />
AJ<br />
36 36 36 36<br />
36 34 34 34<br />
34 34 35 35<br />
35 35 35 35<br />
AJ<br />
AK<br />
36 36<br />
36 36 36 36<br />
34 34 34 34<br />
35 35 35 35<br />
35 35<br />
AK<br />
AL<br />
36 36 36 36<br />
36 36 34 34<br />
34 34 34 35<br />
35 35 35 35<br />
AL<br />
AM<br />
36<br />
36 36 36 36<br />
34 34 34 34<br />
34 35 35 35<br />
35 35 35<br />
AM<br />
AN<br />
36 36 36<br />
36 36 36 34<br />
34 34 34 34<br />
35 35 35 35<br />
35<br />
AN<br />
AP<br />
36 36 36 36<br />
36 34 34 34<br />
34 34 35 35<br />
35 35 35 35<br />
AP<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
Memory Groupings Pins<br />
# HP I/O<br />
# HR I/O<br />
# HP I/O − VCCAUX Group 0<br />
# HP I/O − VCCAUX Group 1<br />
# HP I/O − VCCAUX Group 2<br />
# HP I/O − VCCAUX Group 3<br />
# HP I/O − VCCAUX Group 4<br />
# HP I/O − VCCAUX Group 5<br />
# DQS pin<br />
# DCI pin<br />
# Memory Byte Group 0<br />
# Memory Byte Group 1<br />
# Memory Byte Group 2<br />
# Memory Byte Group 3<br />
# Bank Number<br />
ug475_c3_106_052311<br />
Figure 3-75:<br />
FFG1158 Package—XC7VX485T Memory Groupings<br />
www.BDTIC.com/XILINX<br />
120 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Virtex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-76<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
A<br />
15<br />
17<br />
A<br />
B<br />
15<br />
17<br />
B<br />
C<br />
11<br />
11<br />
16<br />
14<br />
21<br />
21<br />
C<br />
D<br />
11<br />
16<br />
14<br />
21<br />
D<br />
E<br />
11<br />
15<br />
17<br />
21<br />
E<br />
F<br />
16<br />
F<br />
G<br />
11<br />
11<br />
16<br />
14<br />
21<br />
21<br />
G<br />
H<br />
11<br />
15<br />
17<br />
21<br />
H<br />
J<br />
11<br />
17<br />
21<br />
J<br />
K<br />
16<br />
14<br />
K<br />
L<br />
11<br />
11<br />
15<br />
14<br />
21<br />
21<br />
L<br />
M<br />
11<br />
17<br />
21<br />
M<br />
N<br />
11<br />
16<br />
21<br />
N<br />
P<br />
15<br />
14<br />
P<br />
R<br />
11<br />
11<br />
21<br />
21<br />
R<br />
T<br />
11<br />
21<br />
T<br />
U<br />
11<br />
0<br />
21<br />
U<br />
V<br />
V<br />
W<br />
10<br />
10<br />
1<br />
0<br />
20<br />
20<br />
W<br />
Y<br />
10<br />
20<br />
Y<br />
AA<br />
10<br />
1<br />
0<br />
20<br />
AA<br />
AB<br />
AB<br />
AC<br />
10<br />
10<br />
0<br />
1<br />
0<br />
20<br />
20<br />
AC<br />
AD<br />
10<br />
20<br />
AD<br />
AE<br />
10<br />
0<br />
34<br />
20<br />
AE<br />
AF<br />
34<br />
AF<br />
AG<br />
10<br />
10<br />
36<br />
35<br />
20<br />
20<br />
AG<br />
AH<br />
10<br />
36<br />
35<br />
20<br />
AH<br />
AJ<br />
10<br />
36<br />
34<br />
20<br />
AJ<br />
AK<br />
34<br />
35<br />
AK<br />
AL<br />
10<br />
10<br />
36<br />
35<br />
20<br />
20<br />
AL<br />
AM<br />
10<br />
36<br />
34<br />
20<br />
AM<br />
AN<br />
10<br />
34<br />
35<br />
20<br />
AN<br />
AP<br />
36<br />
35<br />
AP<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34<br />
Power Pins<br />
# VCCO_#<br />
VCCINT<br />
VCCAUX<br />
# VCCAUX_IO_G#<br />
VCCBRAM<br />
VCCBATT_0<br />
VCCADC_0<br />
MGTVCCAUX<br />
# MGTVCCAUX_G# or MGTHVCCAUX_G#<br />
MGTAVCC<br />
# MGTAVCC_G# or MGTHAVCC_G#<br />
MGTAVTT<br />
# MGTAVTT_G# or MGTHAVTT_G#<br />
GND<br />
ug475_c3_107_052311<br />
Figure 3-76:<br />
FFG1158 Package—XC7VX485T Power <strong>and</strong> GND Placement<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 121<br />
<strong>UG475</strong> (v1.4) October 17, 2011
122 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011<br />
Chapter 3: Device Diagrams<br />
FFG1761 Package—XC7VX485T<br />
X-Ref Target - Figure 3-77<br />
Figure 3-77:<br />
FFG1761 Package—XC7VX485T <strong>Pinout</strong> Diagram<br />
User I/O Pins<br />
IO_LXXY_#<br />
s<br />
IO_XX_#<br />
Multi−Function Pins<br />
B<br />
ADV_B<br />
B<br />
FCS_B<br />
B<br />
FOE_B<br />
B<br />
MOSI<br />
B<br />
FWE_B<br />
B<br />
DOUT_CSO_B<br />
B<br />
CSI_B<br />
B<br />
PUDC_B<br />
U<br />
RDWR_B<br />
r<br />
RS0−RS1<br />
AD0P/AD0N−AD15P/AD15N<br />
EMCCLK<br />
VRN<br />
VRP<br />
VREF<br />
D00−D31<br />
A00−A28<br />
DQS<br />
MRCC<br />
SRCC<br />
Transceiver Pins<br />
E<br />
MGTAVCC_G#<br />
V<br />
MGTAVTT_G#<br />
V<br />
MGTVCCAUX_G#<br />
V<br />
MGTAVTTRCAL<br />
G<br />
MGTRREF<br />
MGTREFCLK1/0P<br />
MGTREFCLK1/0N<br />
MGTXRXP<br />
MGTXRXN<br />
MGTXTXP<br />
MGTXTXN<br />
E<br />
MGTHAVCC_G#<br />
V<br />
MGTHAVTT_G#<br />
MGTHRXP<br />
MGTHRXN<br />
MGTHTXP<br />
MGTHTXN<br />
Dedicated Pins<br />
C<br />
CCLK_0<br />
CFGBVS_0<br />
D<br />
DONE_0<br />
J<br />
DXP_0<br />
L<br />
DXN_0<br />
GNDADC_0<br />
Y<br />
INIT_B_0<br />
0 M0_0<br />
1 M1_0<br />
2 M2_0<br />
P<br />
PROGRAM_B_0<br />
K<br />
TCK_0<br />
I<br />
TDI_0<br />
O<br />
TDO_0<br />
M<br />
TMS_0<br />
VCCADC_0<br />
VCCBATT_0<br />
S<br />
VP_0<br />
S<br />
VN_0<br />
S<br />
VREFP_0<br />
S<br />
VREFN_0<br />
Other Pins<br />
GND<br />
VCCAUX_IO_G#<br />
VCCAUX<br />
VCCINT<br />
VCCO_#<br />
VCCBRAM<br />
n<br />
NC<br />
ug475_c3_108_090511<br />
L<br />
J<br />
S<br />
S<br />
S<br />
S<br />
C<br />
K<br />
M<br />
O<br />
I<br />
Y<br />
P<br />
D<br />
2<br />
0<br />
1<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
B<br />
B<br />
B<br />
U<br />
B<br />
B<br />
B<br />
B<br />
B<br />
r<br />
r<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
V<br />
G<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
n<br />
n<br />
n<br />
n<br />
1<br />
1<br />
2<br />
2<br />
3<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
6<br />
7<br />
7<br />
8<br />
8<br />
9<br />
9<br />
10<br />
10<br />
11<br />
11<br />
12<br />
12<br />
13<br />
13<br />
14<br />
14<br />
15<br />
15<br />
16<br />
16<br />
17<br />
17<br />
18<br />
18<br />
19<br />
19<br />
20<br />
20<br />
21<br />
21<br />
22<br />
22<br />
23<br />
23<br />
24<br />
24<br />
25<br />
25<br />
26<br />
26<br />
27<br />
27<br />
28<br />
28<br />
29<br />
29<br />
30<br />
30<br />
31<br />
31<br />
32<br />
32<br />
33<br />
33<br />
34<br />
34<br />
35<br />
35<br />
36<br />
36<br />
37<br />
37<br />
38<br />
38<br />
39<br />
39<br />
40<br />
40<br />
41<br />
41<br />
42<br />
42<br />
A<br />
A<br />
B<br />
B<br />
C<br />
C<br />
D<br />
D<br />
E<br />
E<br />
F<br />
F<br />
G<br />
G<br />
H<br />
H<br />
J<br />
J<br />
K<br />
K<br />
L<br />
L<br />
M<br />
M<br />
N<br />
N<br />
P<br />
P<br />
R<br />
R<br />
T<br />
T<br />
U<br />
U<br />
V<br />
V<br />
W<br />
W<br />
Y<br />
Y<br />
AA<br />
AA<br />
AB<br />
AB<br />
AC<br />
AC<br />
AD<br />
AD<br />
AE<br />
AE<br />
AF<br />
AF<br />
AG<br />
AG<br />
AH<br />
AH<br />
AJ<br />
AJ<br />
AK<br />
AK<br />
AL<br />
AL<br />
AM<br />
AM<br />
AN<br />
AN<br />
AP<br />
AP<br />
AR<br />
AR<br />
AT<br />
AT<br />
AU<br />
AU<br />
AV<br />
AV<br />
AW<br />
AW<br />
AY<br />
AY<br />
BA<br />
BA<br />
BB<br />
BB<br />
www.BDTIC.com/XILINX
Virtex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-78<br />
A<br />
B<br />
C 119 119<br />
D<br />
E 119 119<br />
F<br />
G 118 118<br />
H<br />
J 118 118<br />
K<br />
R 116 116<br />
U 116 116<br />
W 115 115<br />
AG 114 114<br />
AJ 114 114<br />
AL 113 113<br />
AN 113 113<br />
115 115<br />
AA 115 115 115 115<br />
AC 115 115<br />
AE 115 115<br />
117 117<br />
116 116<br />
116 116<br />
116 116<br />
115 115<br />
114 114<br />
114 114<br />
114 114<br />
114 114<br />
113 113<br />
113 113<br />
117 117<br />
L 117 117 117 117<br />
M<br />
N 117 117<br />
P<br />
T<br />
V<br />
Y<br />
AB<br />
AD<br />
AF<br />
AH<br />
AK<br />
AM<br />
AP<br />
AR<br />
AT<br />
AU<br />
AV<br />
AW<br />
AY<br />
BA<br />
BB<br />
1<br />
1<br />
2<br />
2<br />
3<br />
119 119<br />
119 119<br />
118 118<br />
118 118<br />
117 117<br />
3<br />
4<br />
4<br />
5<br />
119 119<br />
119 119<br />
118 118<br />
118 118<br />
117 117<br />
116 116<br />
116 116<br />
116 116<br />
115 115<br />
114 114<br />
114 114<br />
113 113<br />
113 113<br />
113 113<br />
5<br />
6<br />
6<br />
7<br />
119 119<br />
119 119<br />
118 118<br />
118 118<br />
117 117<br />
117 117<br />
117 117<br />
116 116<br />
116 116<br />
115 115<br />
115 115<br />
114 114<br />
114 114<br />
113 113<br />
113 113<br />
113 113<br />
7<br />
8<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42<br />
119 119<br />
119 119<br />
118 118<br />
118 118<br />
115<br />
115<br />
39 38 38 38 38 38 38 37 37 37 37 37<br />
39<br />
39 39 39 39<br />
39 39<br />
39 39 39 39<br />
39 39 39<br />
39 39 39<br />
39 39 39<br />
39 38 38 38<br />
39 39 38 38<br />
39 38<br />
39 39 39 39<br />
39 39 39 39<br />
39 39<br />
39 39 39 39<br />
38 38 38 38<br />
38 38 38 38<br />
39 38 38 38<br />
38 38 37 37<br />
38 38 38 36 36 36 36 36<br />
39 39 38 38 38 36 36 36<br />
39 39 39 38<br />
39 39 39 39<br />
38 38 38 38<br />
39 38 38 38<br />
33 33 33 33<br />
33<br />
36 36 36 36 36 36 36 36<br />
36 36 36 36<br />
33 33<br />
33 33 33<br />
33<br />
33 33 33 33<br />
33 33<br />
33 33<br />
33 33 33<br />
33 33 33<br />
33 33<br />
33 33 33 33<br />
33<br />
36 36 36 36<br />
33 33<br />
33 33 33<br />
33<br />
33 33 33 33<br />
33 33<br />
33 33<br />
33 33 33 33<br />
36 36 36 36<br />
38 38 36 36 36 36 36 36<br />
38 38 38 36<br />
38 38<br />
38 37 37 37 37 37 37 37<br />
38 36 36 36<br />
37 37 37 37<br />
38 38 37 37 37 37 37 37<br />
37 37 37 37<br />
36 36 36 36<br />
36 36 34 34<br />
36 36 34 34<br />
36 36 34 34<br />
36 36<br />
37 37 37 37<br />
34 34 34<br />
14 14 16 16<br />
14<br />
14 14 14 14<br />
14<br />
34 34 34 18<br />
16 16 16 16<br />
16<br />
16 16 16<br />
14 14 14<br />
34 34 34 34<br />
34 34 34 34<br />
34 34 34 34<br />
34<br />
37 37 37 37<br />
37 37 37 37<br />
34 34<br />
34 34 18 18<br />
34 34 34<br />
13 13<br />
13 13 13 13<br />
13<br />
13 13 13<br />
13 13 13 13<br />
13 13 13 13<br />
13 13<br />
13 13 13 13<br />
13<br />
14 14 14 16<br />
14 14 14 14<br />
14 14 14 14<br />
13 13 13<br />
16 16 16 16<br />
16 16 16 16<br />
16 16 16 16<br />
16 16<br />
34 34 34 34<br />
34 34 34 34<br />
18 18 18 19<br />
18 18 18 18<br />
34 18 18 18<br />
34 34 18 18<br />
34 34<br />
37 35 35 35<br />
37 37 35 35<br />
37 37 37 37 37 37 37<br />
35 35 35 35<br />
35 34 34 35<br />
16 16 16 16<br />
14 14 14 16<br />
14 14 14 14<br />
14 14 14 14<br />
14 14 14 14<br />
13 13 13 13<br />
13 13 13 13<br />
13 13 13 13<br />
35 35 35 35<br />
35 35 35 35<br />
35 35 35 35<br />
34 34 19 19<br />
18 18 18 18<br />
16 16 16 16<br />
16 16 16 16<br />
18 18 18 18<br />
18 18 18 18<br />
35 35 35 35<br />
35 35 35 35<br />
35 35 35 35 35<br />
16 16 16 17<br />
16 16 16 16<br />
14 14 14 17<br />
14 14 14 14<br />
14 14 15 15<br />
14 14 14 15<br />
13 13 13 15<br />
13 15 15 15<br />
13 13 15 15<br />
13 13 13 15<br />
35 35 35 19<br />
18 18 18 19<br />
18 18 18 18<br />
18 18 18 18<br />
16 17 17 17<br />
16 16 17 17<br />
16 17 17 17<br />
16 17 17 17<br />
14 17 17 17<br />
15 15 15 15<br />
15 15 15 15<br />
13 15 15 15<br />
35 19 19<br />
35 35 19 19<br />
18 18 18 18 T<br />
18 18 18 18<br />
15 15 AM<br />
15 15 15 AP<br />
15 AR<br />
15 15 15 15 AT<br />
15 15 15 15<br />
15 15 15 15<br />
19 19 19 D<br />
17 18 18 W<br />
17 17 17 17 AA<br />
17 17 17 17<br />
17 17 AB<br />
15 15 AU<br />
15 15 15 AW<br />
15 AY<br />
15 15 15 15 BA<br />
15<br />
17 Y<br />
17 17 17 AD<br />
17 AE<br />
17 17 17 17 AF<br />
17 17 17 17<br />
19 19 B<br />
19 E<br />
35 19 19 19 F<br />
35 35 35 19 19 19 G<br />
34 35 35 35<br />
35 19 19 19<br />
19 19 19 19<br />
19 19 19 19<br />
19 19 19 19<br />
19 K<br />
19 19 M<br />
19 19 19 P<br />
19 R<br />
18 18 U<br />
17 17 AG<br />
17 17 17 AJ<br />
17 AK<br />
17 17 17 17 AL<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42<br />
A<br />
C<br />
H<br />
19 19 19 J<br />
19 19 19 19 L<br />
N<br />
V<br />
AC<br />
AH<br />
AN<br />
AV<br />
BB<br />
ug475_c3_109_052311<br />
Figure 3-78:<br />
FFG1761 Package—XC7VX485T I/O Banks<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 123<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-79<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42<br />
A<br />
39 38 38 38 38 38 38 37 37 37 37 37<br />
37 37 37 37<br />
35 35 35 35<br />
35 19 19<br />
A<br />
B<br />
39<br />
39 38 38 38<br />
38 37 37 37 37 37 37 37<br />
37 35 35 35<br />
35 35 35 35<br />
19 19<br />
B<br />
C<br />
39 39 39 39<br />
38 38 38 38<br />
37 37 37 37<br />
37 37 37 37<br />
35 35 35 35<br />
35 35 19 19<br />
C<br />
D<br />
39 39<br />
39 39 38 38<br />
38 38 37 37 37 37 37 37<br />
37 37 35 35<br />
35 35 35 35<br />
19 19 19<br />
D<br />
E<br />
39 39 39 39<br />
38 38 38 38<br />
37 37 37 37<br />
37 37 37 37<br />
35 35 35 35<br />
35 35 35 19<br />
19<br />
E<br />
F<br />
39 39 39<br />
39 38<br />
38 38 37 37<br />
37 37 37 37 37 37 37<br />
35 35 35 35 35<br />
35 19 19 19<br />
F<br />
G<br />
39 39 39<br />
39 38 38 38<br />
36 36 36 36 36 36 36 36<br />
35 35 35 35<br />
35 35 35 19 19 19 G<br />
H<br />
39 39 39 39<br />
38 38 38 36 36 36 36 36<br />
36 36 34 34<br />
35 34 34 35<br />
35 19 19 19<br />
H<br />
J<br />
39 39 39<br />
39 39 38 38 38 36 36 36<br />
36 36 36 36<br />
34 34 34 34<br />
34 35 35 35<br />
19 19 19<br />
J<br />
K<br />
39 39 39 39<br />
38 38 38 38<br />
36 36 36 36<br />
36 36 34 34<br />
34 34 34 34<br />
19 19 19 19<br />
19<br />
K<br />
L<br />
39 39<br />
39 39 39 38<br />
38 38 36 36 36 36 36 36<br />
34 34 34 34<br />
34 34 19 19<br />
19 19 19 19<br />
L<br />
M<br />
39 39 39 39<br />
39 38 38 38<br />
36 36 36 36<br />
36 36 34 34<br />
34 34 34 34<br />
19 19 19 19<br />
19 19 M<br />
N<br />
39 39 39 39<br />
38 38 38 36<br />
36 36 36 36<br />
34 34 34 34<br />
18 18 18 19<br />
19 19 19 19<br />
N<br />
P<br />
38 38<br />
38 36 36 36<br />
36 36<br />
34<br />
34 34 18 18<br />
18 18 18 18<br />
19 19 19<br />
P<br />
R<br />
34 34 34<br />
18 18 18 18<br />
18 18 18 19<br />
19<br />
R<br />
T<br />
34 34 34 18<br />
18 18 18 18<br />
18 18 18 18<br />
T<br />
U<br />
34 34<br />
34 18 18 18<br />
18 18 18 18<br />
18 18<br />
U<br />
V<br />
34 34 34<br />
18 18 18 18<br />
18 18 18 18<br />
V<br />
W<br />
34 34 18 18<br />
18 18 18 18<br />
17 18 18 W<br />
Y<br />
34 34<br />
16 16 16 16<br />
16 17 17 17<br />
17<br />
Y<br />
AA<br />
16 16 16 16<br />
16 16 16 16<br />
17 17 17 17 AA<br />
AB<br />
16<br />
16 16 16 16<br />
16 16 17 17<br />
17 17 AB<br />
AC<br />
16 16 16<br />
16 16 16 16<br />
17 17 17 17<br />
AC<br />
AD<br />
16 16 16 16<br />
16 16 16 17<br />
17 17 17 AD<br />
AE<br />
16 16<br />
16 16 16 16<br />
16 17 17 17<br />
17 AE<br />
AF<br />
14 14 16 16<br />
16 16 16 16<br />
17 17 17 17 AF<br />
AG<br />
14<br />
14 14 14 16<br />
16 17 17 17<br />
17 17 AG<br />
AH<br />
14 14 14 14<br />
14 14 14 16<br />
17 17 17 17<br />
AH<br />
AJ<br />
33 33 33 33<br />
14<br />
14 14 14 14<br />
14 14 14 17<br />
17 17 17 AJ<br />
AK<br />
33<br />
33 33<br />
14 14 14<br />
14 14 14 14<br />
14 17 17 17<br />
17 AK<br />
AL<br />
33 33 33<br />
33<br />
14 14 14 14<br />
14 14 14 14<br />
17 17 17 17 AL<br />
AM<br />
33 33 33 33<br />
14 14 14 14<br />
14 14 15 15<br />
15 15 AM<br />
AN<br />
33 33<br />
33 33<br />
13 13<br />
14 14 14 14<br />
15 15 15 15<br />
AN<br />
AP<br />
33 33 33<br />
13 13 13 13<br />
14 14 14 15<br />
15 15 15 AP<br />
AR<br />
33 33 33<br />
13<br />
13 13 13 13<br />
15 15 15 15<br />
15 AR<br />
AT<br />
33 33<br />
33<br />
13 13 13<br />
13 13 13 15<br />
15 15 15 15 AT<br />
AU<br />
33 33 33 33<br />
13 13 13 13<br />
13 15 15 15<br />
15 15 AU<br />
AV<br />
33<br />
33 33<br />
13 13<br />
13 13 13 13<br />
15 15 15 15<br />
AV<br />
AW<br />
33 33 33<br />
13 13 13 13<br />
13 13 15 15<br />
15 15 15 AW<br />
AY<br />
33 33 33 33<br />
13<br />
13 13 13 13<br />
15 15 15 15<br />
15 AY<br />
BA<br />
33 33<br />
33 33<br />
13 13 13<br />
13 13 13 15<br />
15 15 15 15 BA<br />
BB<br />
33 33 33 33<br />
13 13 13 13<br />
13 15 15 15<br />
15<br />
BB<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42<br />
Memory Groupings Pins<br />
# HP I/O<br />
# HR I/O<br />
# HP I/O − VCCAUX Group 0<br />
# HP I/O − VCCAUX Group 1<br />
# HP I/O − VCCAUX Group 2<br />
# HP I/O − VCCAUX Group 3<br />
# HP I/O − VCCAUX Group 4<br />
# HP I/O − VCCAUX Group 5<br />
# DQS pin<br />
# DCI pin<br />
# Memory Byte Group 0<br />
# Memory Byte Group 1<br />
# Memory Byte Group 2<br />
# Memory Byte Group 3<br />
# Bank Number<br />
ug475_c3_110_052311<br />
Figure 3-79:<br />
FFG1761 Package—XC7VX485T Memory Groupings<br />
www.BDTIC.com/XILINX<br />
124 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 125<br />
<strong>UG475</strong> (v1.4) October 17, 2011<br />
Virtex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-80<br />
Figure 3-80:<br />
FFG1761 Package—XC7VX485T Power <strong>and</strong> GND Placement<br />
11<br />
11<br />
11<br />
11<br />
11<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
11<br />
10<br />
10<br />
0<br />
0<br />
1<br />
1<br />
1<br />
2<br />
2<br />
2<br />
3<br />
3<br />
3<br />
4<br />
4<br />
4<br />
5<br />
5<br />
5<br />
14<br />
14<br />
14<br />
14<br />
14<br />
14<br />
14<br />
15<br />
15<br />
15<br />
15<br />
15<br />
15<br />
16<br />
16<br />
16<br />
16<br />
16<br />
16<br />
17<br />
17<br />
17<br />
17<br />
17<br />
17<br />
18<br />
18<br />
18<br />
18 18<br />
18<br />
19<br />
19<br />
19<br />
19<br />
19<br />
19<br />
19<br />
31<br />
31<br />
31<br />
31<br />
31<br />
31<br />
31<br />
32<br />
32<br />
32<br />
32<br />
32<br />
32<br />
33<br />
33<br />
33<br />
33<br />
33<br />
33<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
35<br />
35<br />
35<br />
35<br />
35<br />
35<br />
35<br />
36<br />
36<br />
36<br />
36<br />
36<br />
36<br />
36<br />
37<br />
37<br />
37<br />
37<br />
37<br />
37<br />
38<br />
38<br />
38<br />
38<br />
38<br />
38<br />
39<br />
39<br />
39<br />
39<br />
39<br />
39<br />
0<br />
0<br />
12<br />
12<br />
12<br />
12<br />
12<br />
12<br />
13<br />
13<br />
13<br />
13<br />
13<br />
13<br />
13<br />
1<br />
1<br />
2<br />
2<br />
3<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
6<br />
7<br />
7<br />
8<br />
8<br />
9<br />
9<br />
10<br />
10<br />
11<br />
11<br />
12<br />
12<br />
13<br />
13<br />
14<br />
14<br />
15<br />
15<br />
16<br />
16<br />
17<br />
17<br />
18<br />
18<br />
19<br />
19<br />
20<br />
20<br />
21<br />
21<br />
22<br />
22<br />
23<br />
23<br />
24<br />
24<br />
25<br />
25<br />
26<br />
26<br />
27<br />
27<br />
28<br />
28<br />
29<br />
29<br />
30<br />
30<br />
31<br />
31<br />
32<br />
32<br />
33<br />
33<br />
34<br />
34<br />
35<br />
35<br />
36<br />
36<br />
37<br />
37<br />
38<br />
38<br />
39<br />
39<br />
40<br />
40<br />
41<br />
41<br />
42<br />
42<br />
A<br />
A<br />
B<br />
B<br />
C<br />
C<br />
D<br />
D<br />
E<br />
E<br />
F<br />
F<br />
G<br />
G<br />
H<br />
H<br />
J<br />
J<br />
K<br />
K<br />
L<br />
L<br />
M<br />
M<br />
N<br />
N<br />
P<br />
P<br />
R<br />
R<br />
T<br />
T<br />
U<br />
U<br />
V<br />
V<br />
W<br />
W<br />
Y<br />
Y<br />
AA<br />
AA<br />
AB<br />
AB<br />
AC<br />
AC<br />
AD<br />
AD<br />
AE<br />
AE<br />
AF<br />
AF<br />
AG<br />
AG<br />
AH<br />
AH<br />
AJ<br />
AJ<br />
AK<br />
AK<br />
AL<br />
AL<br />
AM<br />
AM<br />
AN<br />
AN<br />
AP<br />
AP<br />
AR<br />
AR<br />
AT<br />
AT<br />
AU<br />
AU<br />
AV<br />
AV<br />
AW<br />
AW<br />
AY<br />
AY<br />
BA<br />
BA<br />
BB<br />
BB<br />
Power Pins<br />
# VCCO_#<br />
VCCINT<br />
VCCAUX<br />
# VCCAUX_IO_G#<br />
VCCBRAM<br />
VCCBATT_0<br />
VCCADC_0<br />
MGTVCCAUX<br />
# MGTVCCAUX_G# or MGTHVCCAUX_G#<br />
MGTAVCC<br />
# MGTAVCC_G# or MGTHAVCC_G#<br />
MGTAVTT<br />
# MGTAVTT_G# or MGTHAVTT_G#<br />
GND<br />
ug475_c3_111_052311<br />
www.BDTIC.com/XILINX
126 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011<br />
Chapter 3: Device Diagrams<br />
FFG1927 Package—XC7VX485T<br />
X-Ref Target - Figure 3-81<br />
Figure 3-81:<br />
FFG1927 Package—XC7VX485T <strong>Pinout</strong> Diagram<br />
User I/O Pins<br />
IO_LXXY_#<br />
s<br />
IO_XX_#<br />
Multi−Function Pins<br />
B<br />
ADV_B<br />
B<br />
FCS_B<br />
B<br />
FOE_B<br />
B<br />
MOSI<br />
B<br />
FWE_B<br />
B<br />
DOUT_CSO_B<br />
B<br />
CSI_B<br />
B<br />
PUDC_B<br />
U<br />
RDWR_B<br />
r<br />
RS0−RS1<br />
AD0P/AD0N−AD15P/AD15N<br />
EMCCLK<br />
VRN<br />
VRP<br />
VREF<br />
D00−D31<br />
A00−A28<br />
DQS<br />
MRCC<br />
SRCC<br />
Transceiver Pins<br />
E<br />
MGTAVCC_G#<br />
V<br />
MGTAVTT_G#<br />
V<br />
MGTVCCAUX_G#<br />
V<br />
MGTAVTTRCAL<br />
G<br />
MGTRREF<br />
MGTREFCLK1/0P<br />
MGTREFCLK1/0N<br />
MGTXRXP<br />
MGTXRXN<br />
MGTXTXP<br />
MGTXTXN<br />
E<br />
MGTHAVCC_G#<br />
V<br />
MGTHAVTT_G#<br />
MGTHRXP<br />
MGTHRXN<br />
MGTHTXP<br />
MGTHTXN<br />
Dedicated Pins<br />
C<br />
CCLK_0<br />
CFGBVS_0<br />
D<br />
DONE_0<br />
J<br />
DXP_0<br />
L<br />
DXN_0<br />
GNDADC_0<br />
Y<br />
INIT_B_0<br />
0 M0_0<br />
1 M1_0<br />
2 M2_0<br />
P<br />
PROGRAM_B_0<br />
K<br />
TCK_0<br />
I<br />
TDI_0<br />
O<br />
TDO_0<br />
M<br />
TMS_0<br />
VCCADC_0<br />
VCCBATT_0<br />
S<br />
VP_0<br />
S<br />
VN_0<br />
S<br />
VREFP_0<br />
S<br />
VREFN_0<br />
Other Pins<br />
GND<br />
VCCAUX_IO_G#<br />
VCCAUX<br />
VCCINT<br />
VCCO_#<br />
VCCBRAM<br />
n<br />
NC<br />
ug475_c3_112_090511<br />
L<br />
J<br />
S<br />
S<br />
S<br />
S<br />
C<br />
K<br />
M<br />
O<br />
I<br />
Y<br />
P<br />
D<br />
2<br />
0<br />
1<br />
B<br />
B<br />
B<br />
U<br />
B<br />
B<br />
B<br />
B<br />
B<br />
r<br />
r<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
V<br />
G<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
V<br />
G<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
1<br />
1<br />
2<br />
2<br />
3<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
6<br />
7<br />
7<br />
8<br />
8<br />
9<br />
9<br />
10<br />
10<br />
11<br />
11<br />
12<br />
12<br />
13<br />
13<br />
14<br />
14<br />
15<br />
15<br />
16<br />
16<br />
17<br />
17<br />
18<br />
18<br />
19<br />
19<br />
20<br />
20<br />
21<br />
21<br />
22<br />
22<br />
23<br />
23<br />
24<br />
24<br />
25<br />
25<br />
26<br />
26<br />
27<br />
27<br />
28<br />
28<br />
29<br />
29<br />
30<br />
30<br />
31<br />
31<br />
32<br />
32<br />
33<br />
33<br />
34<br />
34<br />
35<br />
35<br />
36<br />
36<br />
37<br />
37<br />
38<br />
38<br />
39<br />
39<br />
40<br />
40<br />
41<br />
41<br />
42<br />
42<br />
43<br />
43<br />
44<br />
44<br />
A<br />
A<br />
B<br />
B<br />
C<br />
C<br />
D<br />
D<br />
E<br />
E<br />
F<br />
F<br />
G<br />
G<br />
H<br />
H<br />
J<br />
J<br />
K<br />
K<br />
L<br />
L<br />
M<br />
M<br />
N<br />
N<br />
P<br />
P<br />
R<br />
R<br />
T<br />
T<br />
U<br />
U<br />
V<br />
V<br />
W<br />
W<br />
Y<br />
Y<br />
AA<br />
AA<br />
AB<br />
AB<br />
AC<br />
AC<br />
AD<br />
AD<br />
AE<br />
AE<br />
AF<br />
AF<br />
AG<br />
AG<br />
AH<br />
AH<br />
AJ<br />
AJ<br />
AK<br />
AK<br />
AL<br />
AL<br />
AM<br />
AM<br />
AN<br />
AN<br />
AP<br />
AP<br />
AR<br />
AR<br />
AT<br />
AT<br />
AU<br />
AU<br />
AV<br />
AV<br />
AW<br />
AW<br />
AY<br />
AY<br />
BA<br />
BA<br />
BB<br />
BB<br />
BC<br />
BC<br />
BD<br />
BD<br />
www.BDTIC.com/XILINX
Virtex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-82<br />
A<br />
B<br />
C 119 119<br />
D<br />
E 119 119<br />
F<br />
G 118 118<br />
H<br />
J 118 118<br />
K<br />
L 117 117<br />
M<br />
N 117 117<br />
P<br />
R 116 116<br />
T<br />
U 116 116<br />
V<br />
W 115 115<br />
Y<br />
AA 115 115<br />
AB<br />
AC 114 114<br />
AD<br />
AE 114 114<br />
AF<br />
AG 113 113<br />
AH<br />
117 117<br />
117 117<br />
116 116<br />
116 116<br />
115 115<br />
115 115<br />
114 114<br />
114 114<br />
113 113<br />
115 115<br />
115 115<br />
113 113<br />
113 113<br />
AJ 113 113 113 113<br />
AK<br />
AL<br />
AM<br />
AN<br />
AP<br />
AR<br />
AT<br />
AU<br />
AV<br />
AW<br />
AY<br />
BA<br />
BB<br />
BC<br />
BD<br />
1<br />
1<br />
2<br />
2<br />
3<br />
119 119<br />
119 119<br />
119 119<br />
118 118<br />
118 118<br />
119 119<br />
119 119<br />
114 114<br />
114 114 114 114<br />
114 114<br />
116 116<br />
116 116 116 116<br />
116 116<br />
117 117<br />
117 117 117 117<br />
117 117<br />
118 118<br />
118 118 118 118<br />
118 118<br />
119 119<br />
118 118<br />
117 117<br />
116 116<br />
115 115<br />
115 115<br />
114 114<br />
114 114<br />
113 113<br />
113 113<br />
113 113 113 113<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
6<br />
7<br />
7<br />
8<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44<br />
119 119<br />
119 119<br />
118 118<br />
117 117<br />
116 116<br />
115 115<br />
115 115<br />
115 115<br />
36 36 36 34<br />
36<br />
36<br />
36 36 36<br />
36 34 34 34<br />
36 36 34 34<br />
36 36 36 36 34<br />
36 34 34 34<br />
36 36 34 34<br />
36 36 36 34<br />
34<br />
36 36 34 34<br />
36 36<br />
36 36 36<br />
36 36 36 36<br />
36 36 36<br />
36 36 36 36<br />
36 36<br />
36 36 36<br />
36<br />
36 36 36<br />
38 38 38 39<br />
38 38<br />
38 38 38 38<br />
38<br />
38 38 38<br />
38 38 38 39<br />
36<br />
38 39 39 39<br />
38 38 39 39<br />
38 38 38 39<br />
38 38<br />
38 38 38 38<br />
38<br />
38 38 38<br />
38 38<br />
38 38 38<br />
34 34 34 35<br />
34 34 34 34<br />
34 34 34<br />
34 34 34 34<br />
34 34 34<br />
34 34 34 34<br />
36 34 34 34<br />
39 39 37 37<br />
39 39 39 37<br />
38 39 39 39<br />
38 38 39 39<br />
38 38 38 39<br />
38<br />
34 34 35 35<br />
34 34 35 35<br />
37 37 37 17<br />
39 37 37 37<br />
39 37 37 37<br />
39 39 37 37<br />
39 39 39 37<br />
38 39 39 39<br />
38 39 39 39<br />
38 38 39 39<br />
38 38<br />
39 39 39 39<br />
35 35 15 15 15 14 14 14<br />
35 35 35 15 15 15 14 14<br />
35 15 15 15<br />
35 35 35 15<br />
35 35 35 15<br />
35 35 15 15<br />
35 35 35 15<br />
17 17 17 19<br />
37 17 17 17<br />
37 37 17 17<br />
37 37 37 17<br />
37 37 37 37<br />
39 37 37 37<br />
39 39<br />
39 39 39 37<br />
39 39 39 39<br />
39<br />
15 15<br />
15 15 15 15<br />
15 15 15 14<br />
15 15 15 15<br />
35 15 15 15<br />
15 15 15 14<br />
15 15 15 14<br />
15 15 15 15<br />
35 15 15 15<br />
17 19 19 19<br />
17 17 19 19<br />
17 17 17 19<br />
37 17 17 17<br />
37 37 17 17<br />
37 37 37 17<br />
37 37 37<br />
37 37 37 37<br />
39 37 37 37<br />
37 37 37 17<br />
34 35 35 35<br />
34 35 35 35<br />
34 35 35 35<br />
34 34 34 35<br />
35 35 35<br />
17 17 19 19<br />
17 17 17 19<br />
17 17 17 17<br />
17 17 17<br />
37 37 17 17<br />
35 35 35 35<br />
35<br />
35 35 35 35<br />
35<br />
35 35<br />
35<br />
17 19 19 19<br />
17 17 19 19<br />
17 17 17 19<br />
17 17 17 17<br />
19 19 19 18<br />
17 19 19 19<br />
17 17 19 19<br />
19 19 18 18<br />
19 19 19 19<br />
19 19 18 18<br />
14 14 14 14<br />
15 14 14 14<br />
14 16 16 16<br />
14 14 16 16<br />
14 14 16 16<br />
14 14 14 16<br />
14 14 14 14<br />
14 14 14 16<br />
15 14 14 14 14 16 16 16<br />
14 14 14 14<br />
15 15 14 14 14 16 16 16 16<br />
14 14 14 14<br />
18 18 18 18<br />
16 16 16<br />
14 16 16 16<br />
14 16 16 16<br />
15 15 15 14 14 14 16 16 16 16<br />
18<br />
18 18<br />
19 18 18 18<br />
19 19 18 18<br />
19 19 19 18<br />
18 18 18<br />
18<br />
18 18 18 18<br />
18 18<br />
19 18 18 18<br />
19 19 19 19<br />
18 18 18<br />
18<br />
19 18 18 18<br />
18 18<br />
19 19 18 18<br />
19 19 19 18<br />
18 18 18<br />
18<br />
19 18 18 18<br />
16<br />
16 16<br />
16 16 16<br />
16<br />
219 219<br />
219 219<br />
16<br />
16 16 16 16<br />
16 16<br />
16 16 16<br />
16 16 16 16<br />
215 215<br />
215 215 215 215<br />
215 215<br />
214 214<br />
214 214 214 214<br />
215 215<br />
216 216<br />
216 216 216 216<br />
216 216<br />
217 217<br />
217 217 217 217<br />
217 217<br />
218 218<br />
218 218 218 218<br />
218 218<br />
219 219<br />
218 218<br />
217 217<br />
216 216<br />
215 215<br />
214 214<br />
214 214<br />
213 213<br />
213 213<br />
219 219<br />
219 219<br />
218 218<br />
217 217<br />
216 216<br />
215 215<br />
214 214<br />
213 213<br />
213 213<br />
219 219<br />
219 219<br />
219 219<br />
218 218<br />
218 218<br />
217 217<br />
217 217<br />
216 216<br />
216 216<br />
215 215<br />
215 215<br />
214 214<br />
214 214<br />
213 213<br />
213 213 AG<br />
213 213 213 213 AJ<br />
213 213 213 213<br />
219 219 C<br />
219 219 E<br />
218 218 G<br />
218 218 J<br />
217 217 L<br />
217 217 N<br />
216 216 R<br />
216 216 U<br />
215 215 W<br />
215 215 AA<br />
214 214 AC<br />
214 214 AE<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44<br />
A<br />
B<br />
D<br />
F<br />
H<br />
K<br />
M<br />
P<br />
T<br />
V<br />
Y<br />
AB<br />
AD<br />
AF<br />
AH<br />
AK<br />
AL<br />
AM<br />
AN<br />
AP<br />
AR<br />
AT<br />
AU<br />
AV<br />
AW<br />
AY<br />
BA<br />
BB<br />
BC<br />
BD<br />
ug475_c3_113_052311<br />
Figure 3-82:<br />
FFG1927 Package—XC7VX485T I/O Banks<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 127<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-83<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44<br />
A<br />
38 38 38 39<br />
39 39 37 37<br />
17 17 17 19<br />
19 19 18 18<br />
18<br />
A<br />
B<br />
38 38<br />
38 39 39 39<br />
37 37 37 17<br />
17 19 19 19<br />
18 18 18 18<br />
B<br />
C<br />
38 38 38 38<br />
39 39 39 37<br />
37 17 17 17<br />
19 19 19 18<br />
18 18<br />
C<br />
D<br />
38<br />
38 38 39 39<br />
39 37 37 37<br />
17 17 19 19<br />
19 18 18 18<br />
D<br />
E<br />
38 38 38<br />
39 39 39 39<br />
37 37 17 17<br />
19 19 19 19<br />
18 18 18<br />
E<br />
F<br />
38 38 38 39<br />
39 37 37 37<br />
17 17 17 19<br />
19 19 18 18<br />
18<br />
F<br />
G<br />
38 38<br />
38 39 39 39<br />
37 37 37 17<br />
17 17 19 19<br />
18 18 18 18<br />
G<br />
H<br />
38 38 38 38<br />
39 39 37 37<br />
37 17 17 17<br />
19 19 19 18<br />
18 18<br />
H<br />
J<br />
38<br />
38 38 39 39<br />
37 37 37 37<br />
17 17 17 19<br />
19 18 18 18<br />
J<br />
K<br />
38 38 38<br />
39 39 39 37<br />
37 37 17 17<br />
17 19 19 19<br />
18 18 18<br />
K<br />
L<br />
38 38 38 39<br />
39 37 37 37<br />
17 17 17 17<br />
19 19 18 18<br />
18<br />
L<br />
M<br />
38 38<br />
38 39 39 39<br />
37 37 37 17<br />
17 17 19 19<br />
19 18 18 18<br />
M<br />
N<br />
38 38 38 39<br />
39 39<br />
37 37 37<br />
17 17 17<br />
19 19 19 19<br />
18 18<br />
N<br />
P<br />
38<br />
38 39 39 39<br />
37 37 37 37<br />
17 17 17 19<br />
19 19 18 18<br />
P<br />
R<br />
38 38 38<br />
39 39 39 37<br />
37 37 17 17<br />
17 19 19 19<br />
18 18 18<br />
R<br />
T<br />
38 38 39 39<br />
39 37 37 37<br />
17 17 17 17<br />
19 19 19 18<br />
18<br />
T<br />
U<br />
38 38<br />
39 39 39 39<br />
37 37 37 17<br />
17 17 19 19<br />
19 18 18 18<br />
U<br />
V<br />
39<br />
V<br />
W<br />
W<br />
Y<br />
Y<br />
AA<br />
AA<br />
AB<br />
AB<br />
AC<br />
AC<br />
AD<br />
AD<br />
AE<br />
AE<br />
AF<br />
AF<br />
AG<br />
AG<br />
AH<br />
AH<br />
AJ<br />
36<br />
34<br />
35 35<br />
15 15<br />
14 16 16 16<br />
AJ<br />
AK<br />
36 36 36<br />
34 34 34 35<br />
35 35 15 15 15 14 14 14<br />
16 16 16<br />
AK<br />
AL<br />
36 36 34 34<br />
34 35 35 35<br />
15 15 15 15<br />
14 14 16 16<br />
16<br />
AL<br />
AM<br />
36 36<br />
34 34 34 34<br />
35 35 35 15 15 15 14 14<br />
14 16 16 16<br />
AM<br />
AN<br />
36 36 36 34<br />
34 34 35 35<br />
35 15 15 15<br />
14 14 14 14<br />
16 16<br />
AN<br />
AP<br />
36<br />
36 34 34 34<br />
35 35 35 35<br />
15 15 15 14<br />
14 14 16 16<br />
AP<br />
AR<br />
36 36 36<br />
34 34 34<br />
35<br />
35 35 35 15<br />
15 14 14 14<br />
16 16 16<br />
AR<br />
AT<br />
36 36 34 34<br />
34 35 35 35<br />
15 15 15 15<br />
14 14 14 16<br />
16<br />
AT<br />
AU<br />
36 36 36 36<br />
34 34 34 34<br />
35 35 35 15<br />
15 15 15 14<br />
14 16 16 16<br />
16<br />
AU<br />
AV<br />
36 36 36 36 34<br />
34 34 35 35<br />
35 15 15 15<br />
14 14 14 14<br />
16 16 16 16<br />
AV<br />
AW<br />
36 36 36<br />
36 34 34 34<br />
35 35 35 35<br />
15 15 15 14<br />
14 14 14 16<br />
16 16<br />
AW<br />
AY<br />
36 36 36 36<br />
34 34 34<br />
35<br />
35 35 15 15<br />
15 14 14 14 14 16 16 16<br />
AY<br />
BA<br />
36 36<br />
36 36 34 34<br />
34 35 35 35<br />
15 15 15 15<br />
14 14 14 14<br />
16 16 16<br />
BA<br />
BB<br />
36 36 36<br />
36<br />
34 34 34 34<br />
35 35 35 15<br />
15 15 14 14 14 16 16 16 16<br />
BB<br />
BC<br />
36<br />
36 36 36 34<br />
34 34 34 35<br />
35 15 15 15<br />
14 14 14 14<br />
16 16 16 16<br />
BC<br />
BD<br />
36 36 36<br />
36 34 34 34<br />
35 35 35<br />
35<br />
15 15 15 14 14 14 16 16 16 16<br />
BD<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44<br />
Memory Groupings Pins<br />
# HP I/O<br />
# HR I/O<br />
# HP I/O − VCCAUX Group 0<br />
# HP I/O − VCCAUX Group 1<br />
# HP I/O − VCCAUX Group 2<br />
# HP I/O − VCCAUX Group 3<br />
# HP I/O − VCCAUX Group 4<br />
# HP I/O − VCCAUX Group 5<br />
# DQS pin<br />
# DCI pin<br />
# Memory Byte Group 0<br />
# Memory Byte Group 1<br />
# Memory Byte Group 2<br />
# Memory Byte Group 3<br />
# Bank Number<br />
ug475_c3_114_052311<br />
Figure 3-83:<br />
FFG1927 Package—XC7VX485T Memory Groupings<br />
www.BDTIC.com/XILINX<br />
128 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 129<br />
<strong>UG475</strong> (v1.4) October 17, 2011<br />
Virtex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-84<br />
Figure 3-84:<br />
FFG1927 Package—XC7VX485T Power <strong>and</strong> GND Placement<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
20<br />
20<br />
20<br />
20<br />
20<br />
20<br />
20<br />
20<br />
20<br />
21<br />
21<br />
21<br />
21<br />
21<br />
21<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
10<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
11<br />
20<br />
20<br />
20<br />
20<br />
20<br />
20<br />
20<br />
20<br />
20<br />
20<br />
20<br />
20<br />
21<br />
21<br />
21<br />
21<br />
21<br />
21<br />
21<br />
21<br />
21<br />
21<br />
9<br />
9<br />
9<br />
9<br />
9<br />
9<br />
9<br />
9<br />
19<br />
19<br />
19<br />
19<br />
19<br />
19<br />
19<br />
19<br />
9<br />
9<br />
9<br />
9<br />
9<br />
9<br />
9<br />
9<br />
9<br />
9<br />
19<br />
19<br />
19<br />
19<br />
19<br />
19<br />
19<br />
19<br />
19<br />
19<br />
9 19<br />
10<br />
10<br />
11<br />
20<br />
20<br />
21<br />
3<br />
3<br />
3<br />
2<br />
2<br />
2<br />
1<br />
1<br />
1<br />
0<br />
0<br />
0<br />
14<br />
14<br />
14<br />
14<br />
14<br />
14<br />
15<br />
15<br />
15<br />
15<br />
15<br />
15<br />
16<br />
16<br />
16<br />
16<br />
16<br />
16<br />
17<br />
17<br />
17<br />
17<br />
17<br />
17<br />
18<br />
18<br />
18<br />
18<br />
18<br />
18<br />
19<br />
19<br />
19<br />
19<br />
19<br />
19<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
35<br />
35<br />
35<br />
35<br />
35<br />
35<br />
36<br />
36<br />
36<br />
36<br />
36<br />
36<br />
36<br />
37<br />
37<br />
37<br />
37<br />
37<br />
37<br />
37<br />
38<br />
38<br />
38<br />
38<br />
38<br />
38<br />
39<br />
39<br />
39<br />
39<br />
39<br />
39<br />
39<br />
0<br />
0<br />
1<br />
1<br />
2<br />
2<br />
3<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
6<br />
7<br />
7<br />
8<br />
8<br />
9<br />
9<br />
10<br />
10<br />
11<br />
11<br />
12<br />
12<br />
13<br />
13<br />
14<br />
14<br />
15<br />
15<br />
16<br />
16<br />
17<br />
17<br />
18<br />
18<br />
19<br />
19<br />
20<br />
20<br />
21<br />
21<br />
22<br />
22<br />
23<br />
23<br />
24<br />
24<br />
25<br />
25<br />
26<br />
26<br />
27<br />
27<br />
28<br />
28<br />
29<br />
29<br />
30<br />
30<br />
31<br />
31<br />
32<br />
32<br />
33<br />
33<br />
34<br />
34<br />
35<br />
35<br />
36<br />
36<br />
37<br />
37<br />
38<br />
38<br />
39<br />
39<br />
40<br />
40<br />
41<br />
41<br />
42<br />
42<br />
43<br />
43<br />
44<br />
44<br />
A<br />
A<br />
B<br />
B<br />
C<br />
C<br />
D<br />
D<br />
E<br />
E<br />
F<br />
F<br />
G<br />
G<br />
H<br />
H<br />
J<br />
J<br />
K<br />
K<br />
L<br />
L<br />
M<br />
M<br />
N<br />
N<br />
P<br />
P<br />
R<br />
R<br />
T<br />
T<br />
U<br />
U<br />
V<br />
V<br />
W<br />
W<br />
Y<br />
Y<br />
AA<br />
AA<br />
AB<br />
AB<br />
AC<br />
AC<br />
AD<br />
AD<br />
AE<br />
AE<br />
AF<br />
AF<br />
AG<br />
AG<br />
AH<br />
AH<br />
AJ<br />
AJ<br />
AK<br />
AK<br />
AL<br />
AL<br />
AM<br />
AM<br />
AN<br />
AN<br />
AP<br />
AP<br />
AR<br />
AR<br />
AT<br />
AT<br />
AU<br />
AU<br />
AV<br />
AV<br />
AW<br />
AW<br />
AY<br />
AY<br />
BA<br />
BA<br />
BB<br />
BB<br />
BC<br />
BC<br />
BD<br />
BD<br />
Power Pins<br />
# VCCO_#<br />
VCCINT<br />
VCCAUX<br />
# VCCAUX_IO_G#<br />
VCCBRAM<br />
VCCBATT_0<br />
VCCADC_0<br />
MGTVCCAUX<br />
# MGTVCCAUX_G# or MGTHVCCAUX_G#<br />
MGTAVCC<br />
# MGTAVCC_G# or MGTHAVCC_G#<br />
MGTAVTT<br />
# MGTAVTT_G# or MGTHAVTT_G#<br />
GND<br />
ug475_c3_115_052311<br />
www.BDTIC.com/XILINX
130 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011<br />
Chapter 3: Device Diagrams<br />
FFG1930 Package—XC7VX485T<br />
X-Ref Target - Figure 3-85<br />
Figure 3-85:<br />
FFG1930 Package—XC7VX485T <strong>Pinout</strong> Diagram<br />
ug475_c3_116_090511<br />
L<br />
J<br />
S<br />
S<br />
S<br />
S<br />
C<br />
K<br />
M<br />
O<br />
I<br />
Y<br />
P<br />
D<br />
2<br />
0<br />
1 n n n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n n n<br />
n<br />
n<br />
n<br />
n<br />
n n n<br />
n n n n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n n n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n n n<br />
n n n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n n n<br />
n<br />
B<br />
B<br />
B<br />
U B B<br />
B<br />
B<br />
B<br />
r<br />
r<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
n<br />
V<br />
G<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
E<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
V<br />
n<br />
n<br />
1<br />
1<br />
2<br />
2<br />
3<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
6<br />
7<br />
7<br />
8<br />
8<br />
9<br />
9<br />
10<br />
10<br />
11<br />
11<br />
12<br />
12<br />
13<br />
13<br />
14<br />
14<br />
15<br />
15<br />
16<br />
16<br />
17<br />
17<br />
18<br />
18<br />
19<br />
19<br />
20<br />
20<br />
21<br />
21<br />
22<br />
22<br />
23<br />
23<br />
24<br />
24<br />
25<br />
25<br />
26<br />
26<br />
27<br />
27<br />
28<br />
28<br />
29<br />
29<br />
30<br />
30<br />
31<br />
31<br />
32<br />
32<br />
33<br />
33<br />
34<br />
34<br />
35<br />
35<br />
36<br />
36<br />
37<br />
37<br />
38<br />
38<br />
39<br />
39<br />
40<br />
40<br />
41<br />
41<br />
42<br />
42<br />
43<br />
43<br />
44<br />
44<br />
A<br />
A<br />
B<br />
B<br />
C<br />
C<br />
D<br />
D<br />
E<br />
E<br />
F<br />
F<br />
G<br />
G<br />
H<br />
H<br />
J<br />
J<br />
K<br />
K<br />
L<br />
L<br />
M<br />
M<br />
N<br />
N<br />
P<br />
P<br />
R<br />
R<br />
T<br />
T<br />
U<br />
U<br />
V<br />
V<br />
W<br />
W<br />
Y<br />
Y<br />
AA<br />
AA<br />
AB<br />
AB<br />
AC<br />
AC<br />
AD<br />
AD<br />
AE<br />
AE<br />
AF<br />
AF<br />
AG<br />
AG<br />
AH<br />
AH<br />
AJ<br />
AJ<br />
AK<br />
AK<br />
AL<br />
AL<br />
AM<br />
AM<br />
AN<br />
AN<br />
AP<br />
AP<br />
AR<br />
AR<br />
AT<br />
AT<br />
AU<br />
AU<br />
AV<br />
AV<br />
AW<br />
AW<br />
AY<br />
AY<br />
BA<br />
BA<br />
BB<br />
BB<br />
BC<br />
BC<br />
BD<br />
BD<br />
User I/O Pins<br />
IO_LXXY_#<br />
s<br />
IO_XX_#<br />
Multi−Function Pins<br />
B<br />
ADV_B<br />
B<br />
FCS_B<br />
B<br />
FOE_B<br />
B<br />
MOSI<br />
B<br />
FWE_B<br />
B<br />
DOUT_CSO_B<br />
B<br />
CSI_B<br />
B<br />
PUDC_B<br />
U<br />
RDWR_B<br />
r<br />
RS0−RS1<br />
AD0P/AD0N−AD15P/AD15N<br />
EMCCLK<br />
VRN<br />
VRP<br />
VREF<br />
D00−D31<br />
A00−A28<br />
DQS<br />
MRCC<br />
SRCC<br />
Transceiver Pins<br />
E<br />
MGTAVCC_G#<br />
V<br />
MGTAVTT_G#<br />
V<br />
MGTVCCAUX_G#<br />
V<br />
MGTAVTTRCAL<br />
G<br />
MGTRREF<br />
MGTREFCLK1/0P<br />
MGTREFCLK1/0N<br />
MGTXRXP<br />
MGTXRXN<br />
MGTXTXP<br />
MGTXTXN<br />
E<br />
MGTHAVCC_G#<br />
V<br />
MGTHAVTT_G#<br />
MGTHRXP<br />
MGTHRXN<br />
MGTHTXP<br />
MGTHTXN<br />
Dedicated Pins<br />
C<br />
CCLK_0<br />
CFGBVS_0<br />
D<br />
DONE_0<br />
J<br />
DXP_0<br />
L<br />
DXN_0<br />
GNDADC_0<br />
Y<br />
INIT_B_0<br />
0 M0_0<br />
1 M1_0<br />
2 M2_0<br />
P<br />
PROGRAM_B_0<br />
K<br />
TCK_0<br />
I<br />
TDI_0<br />
O<br />
TDO_0<br />
M<br />
TMS_0<br />
VCCADC_0<br />
VCCBATT_0<br />
S<br />
VP_0<br />
S<br />
VN_0<br />
S<br />
VREFP_0<br />
S<br />
VREFN_0<br />
Other Pins<br />
GND<br />
VCCAUX_IO_G#<br />
VCCAUX<br />
VCCINT<br />
VCCO_#<br />
VCCBRAM<br />
n<br />
NC<br />
www.BDTIC.com/XILINX
Virtex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-86<br />
A<br />
B<br />
C<br />
D 36 36<br />
F 36<br />
36 36 36 36<br />
36 36 36 36 37 37<br />
36 36 36 36<br />
E 36 36 36 36<br />
G 36<br />
H<br />
1<br />
36 36 37 37<br />
36 36 36 36<br />
36 36 36 36<br />
36 36 36 36<br />
K 36 36 36 36<br />
L 36<br />
36 37 37 37<br />
36 36 36 37<br />
36 36 36 36<br />
118 118 118 118<br />
R 118 118<br />
W 117 117<br />
AR 114 114<br />
AW 113 113<br />
118 118<br />
118 118<br />
117 117<br />
AC 116 116 116 116<br />
AE 116 116 116 116<br />
116 116<br />
116 116<br />
AJ 115 115 115 115<br />
115 115<br />
115 115<br />
114 114<br />
113 113<br />
BA 113 113 113 113<br />
113 113<br />
37 37 37 37<br />
37 37 37 37<br />
36 37 37 37<br />
114 114<br />
37 37 38 38<br />
37 37 37 38<br />
37 37 37 37<br />
37 37<br />
37 37 37 37<br />
37 38 38 38<br />
37 37 38 38<br />
37 37 37 38<br />
37 37 37 37<br />
37<br />
114 114 114 114<br />
AU 114 114 114 114<br />
114 114<br />
117 117<br />
117 117 117 117<br />
AA 117 117 117 117<br />
117 117<br />
117 117<br />
118 118<br />
118 118 118 118<br />
AG 116 116 116 116<br />
AL 115 115 115 115<br />
AN 115 115 115 115<br />
1<br />
2<br />
J 36 36<br />
M<br />
N<br />
P<br />
T<br />
U<br />
V<br />
Y<br />
AB<br />
AD<br />
AF<br />
AH<br />
AK<br />
AM<br />
AP<br />
AT<br />
AV<br />
AY<br />
BB<br />
BC<br />
BD<br />
2<br />
3<br />
114 114<br />
113 113<br />
116 116<br />
115 115<br />
115 115<br />
115 115<br />
114 114<br />
113 113<br />
113 113<br />
113 113 113 113<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
6<br />
7<br />
118 118<br />
118 118<br />
118 118<br />
117 117<br />
116 116<br />
7<br />
8<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44<br />
37 38 38 38<br />
37 37 38 38<br />
37<br />
37 38 38<br />
38 38 39 39<br />
38 38 38 39<br />
38 39 39 39<br />
38 38 38 39<br />
38 38 38 38<br />
38 38 39 39<br />
39 39 39 35<br />
38 39 39 39<br />
38 38 39 39<br />
38 38 38 39<br />
38 38 38 38<br />
38 38 38 38<br />
39 39 39 39<br />
35 35 35 34<br />
35 35 35 34<br />
35 35 34 34<br />
35 35 35 34 34 34 33 33<br />
35 35 34 34<br />
14 14 14 14<br />
14 14<br />
14 14 14 14<br />
14<br />
14<br />
14 14<br />
14 14 14<br />
14 14 14<br />
14 14<br />
14<br />
14 14 14 14<br />
14 14 14<br />
14 14 14<br />
14 14 14<br />
14<br />
14<br />
14 14 14<br />
14 14<br />
14 14<br />
14 14 14<br />
14<br />
34 34 34 33<br />
39 39 39 35 35 34 34 34<br />
38 39 39 39<br />
38 38 38 39<br />
39 39 35 35 35 34 34 34<br />
39 39 35 35<br />
38 39 39 35<br />
39 39 35 35<br />
39 39 39 39<br />
35 35 35 35<br />
39 35 35 35<br />
39 39 35 35<br />
39 39 39 39<br />
39 35 35 35<br />
39 35 35 35<br />
35 35 35 34<br />
35 35 35 35<br />
35 34 34 34<br />
35 35 34 34<br />
35 34 34 34<br />
34 34 34 33 33 33<br />
34 34 33 33<br />
34 34 34 33<br />
14<br />
34 33 33 33<br />
34 34 33 33<br />
34 33 33 33<br />
34 33<br />
33 33 33<br />
34 34 33 33 33<br />
34 34 34 34<br />
34 34 34 34<br />
33 33 33 33<br />
33 33<br />
33 33 33<br />
33 33 33 33<br />
33 33 19 19<br />
33 33 33 19<br />
33 33 33 33<br />
33<br />
19 19 19 19<br />
33 19 19 19<br />
33 33 18 18<br />
18 18 18 18<br />
18 18 18 18<br />
15<br />
15<br />
15 15 15<br />
13<br />
19 19<br />
19 19 19 19<br />
19 19 19 19<br />
13 13 13<br />
13 13 13 15<br />
13 13 13 13<br />
13 13<br />
15 15 15 16<br />
15 15 15 15<br />
15 15<br />
19 18 18 18<br />
18 18 18 18<br />
17 17 17 17<br />
17<br />
17 17 17<br />
16 16 16 16<br />
16<br />
16 16 16<br />
15 15 15 15<br />
13 13 13<br />
19 19 19 19<br />
18 18 18 18<br />
18 18<br />
16 16 16 16<br />
16 16 16 16<br />
16 16<br />
19 19 19 19<br />
18 18 18 18<br />
17 17 17 17<br />
17 17 17 17<br />
15 15 15 15<br />
15 15 15 15<br />
13 13 13 13<br />
13 13 13 13<br />
13 13 13<br />
19 19 19 19<br />
19 19 19 19<br />
18 18 18 18<br />
18 18 18 18<br />
18 18 18 18<br />
17 17 17 17<br />
17 17 17 17<br />
17 17 17 17 17 17<br />
16 16 17 17<br />
16 16 16 16<br />
16 16 16 16<br />
15 15 15 15<br />
15 15 15 15<br />
13 13 13 13<br />
13 13 13 13<br />
19 19 19 19<br />
18 18 18 18<br />
16 16 16 16<br />
15 15 15 15<br />
15 15 15 15<br />
13 13 13 13 AR<br />
13 13 13 13<br />
13 13<br />
19 19 19 19 K<br />
18 18 18 18 R<br />
16 16 16 16 AE<br />
16 16 16 16<br />
19 19<br />
19 19 19 N<br />
17 17 17 V<br />
17 W<br />
17 17 17 17 Y<br />
17 17 17 17<br />
18 P<br />
18 18 T<br />
17 17 AA<br />
17 17 17 AC<br />
17 AD<br />
16 16 AF<br />
16 16 16 AH<br />
16 AJ<br />
15 16 16 16 AK<br />
15 15 AL<br />
15 15 15 AN<br />
15 AP<br />
13 13 AT<br />
13 13 13 AV<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44<br />
ug475_c3_117_052311<br />
A<br />
B<br />
C<br />
D<br />
E<br />
F<br />
G<br />
H<br />
J<br />
L<br />
M<br />
U<br />
AB<br />
AG<br />
AM<br />
AU<br />
AW<br />
AY<br />
BA<br />
BB<br />
BC<br />
BD<br />
Figure 3-86:<br />
FFG1930 Package—XC7VX485T I/O Banks<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 131<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
X-Ref Target - Figure 3-87<br />
A<br />
B<br />
C<br />
D 36 36<br />
F 36<br />
36 36 36 36<br />
36 36 36 36 37 37<br />
36 36 36 36<br />
E 36 36 36 36<br />
G 36<br />
H<br />
1<br />
36 36 37 37<br />
36 36 36 36<br />
36 36 36 36<br />
36 36 36 36<br />
K 36 36 36 36<br />
L 36<br />
1<br />
2<br />
J 36 36<br />
M<br />
N<br />
P<br />
R<br />
T<br />
U<br />
V<br />
W<br />
Y<br />
AA<br />
AB<br />
AC<br />
AD<br />
AE<br />
AF<br />
AG<br />
AH<br />
AJ<br />
AK<br />
AL<br />
AM<br />
AN<br />
AP<br />
AR<br />
AT<br />
AU<br />
AV<br />
AW<br />
AY<br />
BA<br />
BB<br />
BC<br />
BD<br />
2<br />
3<br />
36 37 37 37<br />
36 36 36 37<br />
36 36 36 36<br />
3<br />
4<br />
4<br />
5<br />
5<br />
6<br />
37 37 37 37<br />
37 37 37 37<br />
36 37 37 37<br />
6<br />
7<br />
37 37 38 38<br />
37 37 37 38<br />
37 37 37 37<br />
37 37<br />
37 37 37 37<br />
7<br />
8<br />
37 38 38 38<br />
37 37 38 38<br />
37 37 37 38<br />
37 37 37 37<br />
37<br />
8<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44<br />
37 38 38 38<br />
37 37 38 38<br />
37<br />
37 38 38<br />
38 38 39 39<br />
38 38 38 39<br />
38 39 39 39<br />
38 38 38 39<br />
38 38 38 38<br />
38 38 39 39<br />
39 39 39 35<br />
38 39 39 39<br />
38 38 39 39<br />
38 38 38 39<br />
38 38 38 38<br />
38 38 38 38<br />
39 39 39 39<br />
35 35 35 34<br />
35 35 35 34<br />
35 35 34 34<br />
35 35 35 34 34 34 33 33<br />
35 35 34 34<br />
14 14 14 14<br />
14 14<br />
14 14 14 14<br />
14<br />
14<br />
14 14<br />
14 14 14<br />
14 14 14<br />
14 14<br />
14<br />
14 14 14 14<br />
14 14 14<br />
14 14 14<br />
14 14 14<br />
14<br />
14<br />
14 14 14<br />
14 14<br />
14 14<br />
14 14 14<br />
14<br />
34 34 34 33<br />
39 39 39 35 35 34 34 34<br />
38 39 39 39<br />
38 38 38 39<br />
39 39 35 35 35 34 34 34<br />
39 39 35 35<br />
38 39 39 35<br />
39 39 35 35<br />
39 39 39 39<br />
35 35 35 35<br />
39 35 35 35<br />
39 39 35 35<br />
39 39 39 39<br />
39 35 35 35<br />
39 35 35 35<br />
35 35 35 34<br />
35 35 35 35<br />
35 34 34 34<br />
35 35 34 34<br />
35 34 34 34<br />
34 34 34 33 33 33<br />
34 34 33 33<br />
34 34 34 33<br />
14<br />
34 33 33 33<br />
34 34 33 33<br />
34 33 33 33<br />
34 33<br />
33 33 33<br />
34 34 33 33 33<br />
34 34 34 34<br />
34 34 34 34<br />
33 33 33 33<br />
33 33<br />
33 33 33<br />
33 33 33 33<br />
33 33 19 19<br />
33 33 33 19<br />
33 33 33 33<br />
33<br />
19 19 19 19<br />
33 19 19 19<br />
33 33 18 18<br />
18 18 18 18<br />
18 18 18 18<br />
15<br />
15<br />
15 15 15<br />
13<br />
19 19<br />
19 19 19 19<br />
19 19 19 19<br />
13 13 13<br />
13 13 13 15<br />
13 13 13 13<br />
13 13<br />
15 15 15 16<br />
15 15 15 15<br />
15 15<br />
19 18 18 18<br />
18 18 18 18<br />
17 17 17 17<br />
17<br />
17 17 17<br />
16 16 16 16<br />
16<br />
16 16 16<br />
15 15 15 15<br />
13 13 13<br />
19 19 19 19<br />
18 18 18 18<br />
18 18<br />
16 16 16 16<br />
16 16 16 16<br />
16 16<br />
19 19 19 19<br />
18 18 18 18<br />
17 17 17 17<br />
17 17 17 17<br />
15 15 15 15<br />
15 15 15 15<br />
13 13 13 13<br />
13 13 13 13<br />
13 13 13<br />
19 19 19 19<br />
19 19 19 19<br />
18 18 18 18<br />
18 18 18 18<br />
18 18 18 18<br />
17 17 17 17<br />
17 17 17 17<br />
17 17 17 17 17 17<br />
16 16 17 17<br />
16 16 16 16<br />
16 16 16 16<br />
15 15 15 15<br />
15 15 15 15<br />
13 13 13 13<br />
13 13 13 13<br />
19 19 19 19<br />
18 18 18 18<br />
16 16 16 16<br />
15 15 15 15<br />
15 15 15 15<br />
13 13 13 13 AR<br />
13 13 13 13<br />
13 13<br />
19 19 19 19 K<br />
18 18 18 18 R<br />
16 16 16 16 AE<br />
16 16 16 16<br />
19 19<br />
19 19 19 N<br />
17 17 17 V<br />
17 W<br />
17 17 17 17 Y<br />
17 17 17 17<br />
18 P<br />
18 18 T<br />
17 17 AA<br />
17 17 17 AC<br />
17 AD<br />
16 16 AF<br />
16 16 16 AH<br />
16 AJ<br />
15 16 16 16 AK<br />
15 15 AL<br />
15 15 15 AN<br />
15 AP<br />
13 13 AT<br />
13 13 13 AV<br />
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44<br />
Memory Groupings Pins<br />
A<br />
B<br />
C<br />
D<br />
E<br />
F<br />
G<br />
H<br />
J<br />
L<br />
M<br />
U<br />
AB<br />
AG<br />
AM<br />
AU<br />
AW<br />
AY<br />
BA<br />
BB<br />
BC<br />
BD<br />
# HP I/O<br />
# HR I/O<br />
# HP I/O − VCCAUX Group 0<br />
# HP I/O − VCCAUX Group 1<br />
# HP I/O − VCCAUX Group 2<br />
# HP I/O − VCCAUX Group 3<br />
# HP I/O − VCCAUX Group 4<br />
# HP I/O − VCCAUX Group 5<br />
# HP I/O − VCCAUX Group 6<br />
# HP I/O − VCCAUX Group 7<br />
# DQS pin<br />
# DCI pin<br />
# Memory Byte Group 0<br />
# Memory Byte Group 1<br />
# Memory Byte Group 2<br />
# Memory Byte Group 3<br />
# Bank Number<br />
ug475_c3_118_052311<br />
Figure 3-87:<br />
FFG1930 Package—XC7VX485T Memory Groupings<br />
www.BDTIC.com/XILINX<br />
132 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Virtex-7 <strong>FPGAs</strong> Device Diagrams<br />
X-Ref Target - Figure 3-88<br />
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44<br />
A<br />
37<br />
39<br />
33<br />
21<br />
A<br />
B<br />
36<br />
38<br />
34<br />
21<br />
B<br />
C 36<br />
37<br />
35<br />
21 21<br />
C<br />
D<br />
37<br />
39<br />
33<br />
21<br />
D<br />
E<br />
36<br />
38<br />
34<br />
20<br />
E<br />
F 36<br />
38<br />
35<br />
20<br />
21<br />
F<br />
G<br />
37<br />
39<br />
33<br />
20<br />
G<br />
H<br />
36<br />
39<br />
34<br />
20<br />
H<br />
J<br />
36<br />
38<br />
34<br />
20 20 J<br />
K<br />
37<br />
35<br />
33<br />
19<br />
K<br />
L<br />
37<br />
39<br />
33<br />
19<br />
L<br />
M<br />
38<br />
34<br />
19 19 M<br />
N<br />
37<br />
35<br />
19 19<br />
N<br />
P 11<br />
11<br />
35<br />
33<br />
18<br />
P<br />
R<br />
11<br />
11<br />
39<br />
34<br />
18<br />
R<br />
T<br />
38<br />
34<br />
18 18<br />
T<br />
U<br />
35<br />
3 33<br />
18<br />
U<br />
V 11<br />
11<br />
3<br />
18<br />
V<br />
W<br />
11<br />
11<br />
7<br />
2 3<br />
17 W<br />
Y<br />
6<br />
2<br />
17<br />
Y<br />
AA<br />
6<br />
2 1<br />
17<br />
AA<br />
AB 11<br />
11<br />
6<br />
1<br />
17 17 AB<br />
AC<br />
11<br />
11<br />
5<br />
1<br />
17<br />
AC<br />
AD<br />
5<br />
0<br />
16<br />
AD<br />
AE<br />
5<br />
0<br />
16<br />
AE<br />
AF 11<br />
11<br />
4 4<br />
0<br />
16 AF<br />
AG<br />
11<br />
11<br />
4<br />
16<br />
AG<br />
AH<br />
11<br />
31<br />
12<br />
16<br />
AH<br />
AJ<br />
10<br />
0 32<br />
14<br />
15<br />
16 AJ<br />
AK 10<br />
10<br />
0 30<br />
10<br />
15<br />
AK<br />
AL<br />
10<br />
10<br />
30<br />
12<br />
15<br />
AL<br />
AM<br />
31<br />
14<br />
15 15 AM<br />
AN<br />
32<br />
14<br />
10<br />
15<br />
AN<br />
AP 10<br />
10<br />
30<br />
12<br />
13<br />
AP<br />
AR<br />
10<br />
10<br />
31<br />
12<br />
13<br />
AR<br />
AT<br />
32<br />
14<br />
13 13 AT<br />
AU<br />
30<br />
10<br />
13<br />
AU<br />
AV 10<br />
10<br />
31<br />
12<br />
13<br />
AV<br />
AW<br />
10<br />
10<br />
32<br />
14<br />
10<br />
11 AW<br />
AY<br />
32<br />
30<br />
10<br />
11<br />
AY<br />
BA<br />
31<br />
12<br />
11<br />
BA<br />
BB 10<br />
10<br />
31<br />
14<br />
11 11 BB<br />
BC<br />
10<br />
10 32<br />
30<br />
10<br />
11<br />
BC<br />
BD<br />
30<br />
12<br />
11<br />
BD<br />
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44<br />
Power Pins<br />
# VCCO_#<br />
VCCINT<br />
VCCAUX<br />
# VCCAUX_IO_G#<br />
VCCBRAM<br />
VCCBATT_0<br />
VCCADC_0<br />
GNDADC_0<br />
MGTVCCAUX<br />
# MGTVCCAUX_G# or MGTHVCCAUX_G#<br />
MGTAVCC<br />
# MGTAVCC_G# or MGTHAVCC_G#<br />
MGTAVTT<br />
# MGTAVTT_G# or MGTHAVTT_G#<br />
GND<br />
ug475_c3_119_052311<br />
Figure 3-88:<br />
FFG1930 Package—XC7VX485T Power <strong>and</strong> GND Placement<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 133<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 3: Device Diagrams<br />
www.BDTIC.com/XILINX<br />
134 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 4<br />
Mechanical Drawings<br />
Summary<br />
This chapter provides mechanical drawings (package specifications) of the following<br />
7 series FPGA packages:<br />
• FB(G)484 Flip-Chip Bare-Die BGA (Kintex-7 <strong>FPGAs</strong>) (1.0 mm Pitch), page 136<br />
• FB(G)676 Flip-Chip Bare-Die BGA (Kintex-7 <strong>FPGAs</strong>) (1.0 mm Pitch), page 137<br />
• FB(G)900 Flip-Chip Bare-Die BGA (Kintex-7 <strong>FPGAs</strong>) (1.0 mm Pitch), page 138<br />
• FF(G)676 Flip-Chip BGA (Kintex-7 <strong>FPGAs</strong>) (1.0 mm Pitch), page 139<br />
• FF(G)900 Flip-Chip BGA (Kintex-7 <strong>FPGAs</strong>) (1.0 mm Pitch), page 140<br />
• FF(G)901 Flip-Chip BGA (Kintex-7 <strong>FPGAs</strong>) (1.0 mm Pitch), page 141<br />
• FF(G)1156 Flip-Chip BGA (Kintex-7 <strong>FPGAs</strong>) (1.0 mm Pitch), page 142<br />
• FF(G)1157 <strong>and</strong> FF(G)1158 Flip-Chip BGA (Virtex-7 <strong>FPGAs</strong>) (1.0 mm Pitch), page 143<br />
• FF(G)1761 Flip-Chip BGA (Virtex-7 <strong>FPGAs</strong>) (1.0 mm Pitch), page 144<br />
• FH(G)1761 Flip-Chip BGA (Virtex-7 <strong>FPGAs</strong>) (1.0 mm Pitch), page 145<br />
• FF(G)1926, FF(G)1927, FF(G)1928, <strong>and</strong> FF(G)1930 Flip-Chip BGA (Virtex-7 <strong>FPGAs</strong>)<br />
(1.0 mm Pitch), page 146<br />
• FL(G)1925, FL(G)1928, <strong>and</strong> FL(G)1930 Flip-Chip BGA (Virtex-7 <strong>FPGAs</strong>) (1.0 mm<br />
Pitch), page 147<br />
Note: This chapter is intentionally missing drawings.<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 135<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 4: Mechanical Drawings<br />
FB(G)484 Flip-Chip Bare-Die BGA (Kintex-7 <strong>FPGAs</strong>)<br />
(1.0 mm Pitch)<br />
X-Ref Target - Figure 4-1<br />
ug475_c4_01_031511<br />
Figure 4-1:<br />
FB(G)484 Flip-Chip Bare-Die BGA Package Specifications for Kintex-7 <strong>FPGAs</strong><br />
www.BDTIC.com/XILINX<br />
136 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
FB(G)676 Flip-Chip Bare-Die BGA (Kintex-7 <strong>FPGAs</strong>) (1.0 mm Pitch)<br />
FB(G)676 Flip-Chip Bare-Die BGA (Kintex-7 <strong>FPGAs</strong>)<br />
(1.0 mm Pitch)<br />
X-Ref Target - Figure 4-2<br />
ug475_c4_02_031511<br />
Figure 4-2:<br />
FB(G)676 Flip-Chip Bare-Die BGA Package Specifications for Kintex-7 <strong>FPGAs</strong><br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 137<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 4: Mechanical Drawings<br />
FB(G)900 Flip-Chip Bare-Die BGA (Kintex-7 <strong>FPGAs</strong>)<br />
(1.0 mm Pitch)<br />
X-Ref Target - Figure 4-3<br />
ug475_c4_03_031511<br />
Figure 4-3: FB(G)900 Flip-Chip Bare-Die BGA Package Specifications for Kintex-7 <strong>FPGAs</strong><br />
www.BDTIC.com/XILINX<br />
138 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
FF(G)676 Flip-Chip BGA (Kintex-7 <strong>FPGAs</strong>) (1.0 mm Pitch)<br />
FF(G)676 Flip-Chip BGA (Kintex-7 <strong>FPGAs</strong>)<br />
(1.0 mm Pitch)<br />
X-Ref Target - Figure 4-4<br />
ug475_c4_04_031511<br />
Figure 4-4:<br />
FF(G)676 Flip-Chip BGA Package Specifications for Kintex-7 <strong>FPGAs</strong><br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 139<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 4: Mechanical Drawings<br />
FF(G)900 Flip-Chip BGA (Kintex-7 <strong>FPGAs</strong>)<br />
(1.0 mm Pitch)<br />
X-Ref Target - Figure 4-5<br />
ug475_c4_05_031511<br />
Figure 4-5:<br />
FF(G)900 Flip-Chip BGA Package Specifications for Kintex-7 <strong>FPGAs</strong><br />
www.BDTIC.com/XILINX<br />
140 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
FF(G)901 Flip-Chip BGA (Kintex-7 <strong>FPGAs</strong>) (1.0 mm Pitch)<br />
FF(G)901 Flip-Chip BGA (Kintex-7 <strong>FPGAs</strong>)<br />
(1.0 mm Pitch)<br />
X-Ref Target - Figure 4-6<br />
ug475_c4_06_031511<br />
Figure 4-6:<br />
FF(G)901 Flip-Chip BGA Package Specifications for Kintex-7 <strong>FPGAs</strong><br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 141<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 4: Mechanical Drawings<br />
FF(G)1156 Flip-Chip BGA (Kintex-7 <strong>FPGAs</strong>)<br />
(1.0 mm Pitch)<br />
X-Ref Target - Figure 4-7<br />
ug475_c4_07_052311<br />
Figure 4-7:<br />
FF(G)1156 Flip-Chip BGA Package Specification for Kintex-7 <strong>FPGAs</strong><br />
www.BDTIC.com/XILINX<br />
142 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
FF(G)1157 <strong>and</strong> FF(G)1158 Flip-Chip BGA (Virtex-7 <strong>FPGAs</strong>) (1.0 mm Pitch)<br />
FF(G)1157 <strong>and</strong> FF(G)1158 Flip-Chip BGA (Virtex-7 <strong>FPGAs</strong>)<br />
(1.0 mm Pitch)<br />
X-Ref Target - Figure 4-8<br />
ug475_c4_08_052311<br />
Figure 4-8:<br />
FF(G)1157 <strong>and</strong> FF(G)1158 Flip-Chip BGA Package Specification for Virtex-7 <strong>FPGAs</strong><br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 143<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 4: Mechanical Drawings<br />
FF(G)1761 Flip-Chip BGA (Virtex-7 <strong>FPGAs</strong>)<br />
(1.0 mm Pitch)<br />
X-Ref Target - Figure 4-9<br />
ug475_c4_09_091411<br />
Figure 4-9:<br />
FF(G)1761 Flip-Chip BGA Package Specification for Virtex-7 <strong>FPGAs</strong><br />
www.BDTIC.com/XILINX<br />
144 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
FH(G)1761 Flip-Chip BGA (Virtex-7 <strong>FPGAs</strong>) (1.0 mm Pitch)<br />
FH(G)1761 Flip-Chip BGA (Virtex-7 <strong>FPGAs</strong>)<br />
(1.0 mm Pitch)<br />
X-Ref Target - Figure 4-10<br />
ug475_c4_10_100311<br />
Figure 4-10:<br />
FF(G)1761 Flip-Chip BGA Package Specification for Virtex-7 <strong>FPGAs</strong><br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 145<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 4: Mechanical Drawings<br />
FF(G)1926, FF(G)1927, FF(G)1928, <strong>and</strong> FF(G)1930 Flip-Chip BGA<br />
(Virtex-7 <strong>FPGAs</strong>) (1.0 mm Pitch)<br />
X-Ref Target - Figure 4-11<br />
ug475_c4_11_100311<br />
Figure 4-11:<br />
FF(G)1926, FF(G)1927, FF(G)1928, <strong>and</strong> FF(G)1930 Flip-Chip BGA Package Specification<br />
for Virtex-7 <strong>FPGAs</strong><br />
www.BDTIC.com/XILINX<br />
146 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
FL(G)1925, FL(G)1928, <strong>and</strong> FL(G)1930 Flip-Chip BGA (Virtex-7 <strong>FPGAs</strong>) (1.0 mm Pitch)<br />
FL(G)1925, FL(G)1928, <strong>and</strong> FL(G)1930 Flip-Chip BGA<br />
(Virtex-7 <strong>FPGAs</strong>) (1.0 mm Pitch)<br />
X-Ref Target - Figure 4-12<br />
ug475_c4_12_100311<br />
Figure 4-12:<br />
FL(G)1925, FL(G)1928, <strong>and</strong> FL(G)1930 Flip-Chip BGA Package Specification<br />
for Virtex-7 <strong>FPGAs</strong><br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 147<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 4: Mechanical Drawings<br />
www.BDTIC.com/XILINX<br />
148 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 5<br />
Thermal Specifications<br />
Summary<br />
Introduction<br />
This chapter provides thermal data associated with 7 series <strong>FPGAs</strong> packages. The<br />
following topics are discussed:<br />
• Introduction<br />
• Power Management Strategy<br />
• Some Thermal Management Options<br />
• Support for Compact Thermal Models (CTM)<br />
• References<br />
7 series <strong>FPGAs</strong> are offered exclusively in thermally efficient flip-chip BGA packages. These<br />
0.5 mm, 0.8 mm, <strong>and</strong> 1.0 mm flip-chip packages range in pin-count from the smaller<br />
10 x 10 mm CPG236 to the 45 x 45 mm FFG1930. The suite of packages is used to address<br />
the various power requirements of the 7 series devices. All 7 series devices are<br />
implemented in the 28 nm process technology.<br />
Similar to Virtex®-6 <strong>FPGAs</strong>, all 7 series devices feature the versatile SelectIO resources<br />
that support a variety of I/O st<strong>and</strong>ards. They also include analog-to-digital converters<br />
(XADC), DSPs, <strong>and</strong> other traditional features <strong>and</strong> blocks (such as block RAM) contained in<br />
earlier Virtex products.<br />
In line with Moore's law, the transistor count in this family of devices has been increased<br />
substantially. Though several innovative features at the silicon level have been deployed to<br />
minimize power dissipation, including leakage at the 28 nm node, these products have<br />
more densely packed transistors <strong>and</strong> embedded blocks with the capability to run faster<br />
than before. Thus, a fully configured 7 series FPGA design that exploits the fabric speed<br />
<strong>and</strong> incorporates several embedded circuits <strong>and</strong> systems can present power consumption<br />
challenges that must be managed.<br />
Unlike features in an ASIC or a microprocessor, the combination of FPGA features used in<br />
a user application are not known to the component supplier. Therefore, it remains a<br />
challenge for <strong>Xilinx</strong> to predict the power requirements of a given FPGA when it leaves the<br />
factory. Accurate estimates are obtained when the board design takes shape. For this<br />
purpose, <strong>Xilinx</strong> offers <strong>and</strong> supports a suite of integrated device power analysis tools to<br />
help users quickly <strong>and</strong> accurately estimate their design power requirements. 7 series<br />
devices are supported similarly to previous FPGA products. The uncertainty of design<br />
power requirements makes it difficult to apply canned thermal solutions to fit all users.<br />
Therefore, <strong>Xilinx</strong> devices do not come with preset thermal solutions. The user’s operating<br />
conditions dictate the appropriate solution.<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 149<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 5: Thermal Specifications<br />
Table 5-1 shows the thermal resistance data for 7 series devices (grouped in the packages<br />
offered). The data includes junction-to-ambient in still air, junction-to-case, <strong>and</strong><br />
junction-to-board data based on st<strong>and</strong>ard JEDEC four-layer measurements.<br />
• Thermal data is available on the <strong>Xilinx</strong> website at:<br />
http://www.xilinx.com/cgi-bin/thermal/thermal.pl.<br />
• Compact package thermal models for these products are available on the <strong>Xilinx</strong><br />
support download center (under the Device Model tab) at:<br />
http://www.xilinx.com/support/download/index.htm<br />
Table 5-1:<br />
Thermal Resistance Data—All Devices<br />
Package<br />
Package<br />
Body Size<br />
Devices<br />
JA<br />
(°C/W)<br />
JB<br />
(°C/W)<br />
JC<br />
(°C/W)<br />
JA (°C/W)<br />
@ 250 LFM<br />
JA (°C/W)<br />
@ 500 LFM<br />
JA (°C/W)<br />
@ 750 LFM<br />
Artix-7 <strong>FPGAs</strong><br />
CP(G)236 10 x 10<br />
CS(G)225 12 x 12<br />
XC7A8 41.0 23.4 8.89 35.2 33.3 32.0<br />
XC7A15 41.0 23.4 8.89 35.2 33.3 32.0<br />
XC7A30T 26.1 10.9 4.94 21.1 19.7 18.8<br />
XC7A50T 26.1 10.9 4.94 21.1 19.7 18.8<br />
XC7A8 29.6 16.1 7.41 24.6 23.2 22.4<br />
XC7A15 29.6 16.1 7.41 24.6 23.2 22.4<br />
CS(G)324 15 x 15<br />
XC7A30T 24.5 11.3 4.67 19.6 18.4 17.6<br />
XC7A50T 24.5 11.3 4.67 19.6 18.4 17.6<br />
XC7A100T 21.9 8.8 3.37 16.8 15.6 15.0<br />
XC7A8 31.2 21.1 11.08 26.5 25.0 24.2<br />
XC7A15 31.2 21.1 11.08 26.5 25.0 24.2<br />
FT(G)256 17 x 17<br />
XC7A30T 24.3 14.2 7.14 19.8 18.5 17.7<br />
XC7A50T 24.3 14.2 7.14 19.8 18.5 17.7<br />
XC7A100T 21.8 11.0 5.24 16.9 16.6 14.9<br />
FB(G)484 23 x 23<br />
XC7A200T 14.2 4.6 0.05 10.2 9.1 8.6<br />
XC7A350T 14.3 4.2 0.05 9.6 8.6 8.1<br />
XC7A30T 19.7 11.3 7.01 15.1 14.0 13.5<br />
FG(G)484 23 x 23<br />
XC7A50T 19.7 11.3 7.01 15.1 14.0 13.5<br />
XC7A100T 17.9 9.1 5.48 13.3 12.2 11.7<br />
FB(G)676 27 x 27<br />
XC7A200T 14.3 4.6 0.05 9.5 8.4 7.9<br />
XC7A350T 13.3 4.0 0.04 8.7 7.7 7.1<br />
FG(G)676 27 x 27 XC7A100T 16.8 8.5 5.2 12.3 11.3 10.8<br />
FF(G)1156 35 x 35<br />
XC7A200T 10.2 3.7 0.33 6.4 5.4 4.8<br />
XC7A350T 9.8 2.2 0.23 6.1 5.2 4.6<br />
www.BDTIC.com/XILINX<br />
150 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Introduction<br />
Table 5-1:<br />
Thermal Resistance Data—All Devices (Cont’d)<br />
Package<br />
Package<br />
Body Size<br />
Devices<br />
JA<br />
(°C/W)<br />
JB<br />
(°C/W)<br />
JC<br />
(°C/W)<br />
JA (°C/W)<br />
@ 250 LFM<br />
JA (°C/W)<br />
@ 500 LFM<br />
JA (°C/W)<br />
@ 750 LFM<br />
Kintex-7 <strong>FPGAs</strong><br />
FB(G)484 23 x 23<br />
XC7K70T 16.4 6.6 0.16 12.0 11.0 10.4<br />
XC7K160T 13.5 5.0 0.06 10.4 9.4 8.8<br />
XC7K70T 15.8 6.8 0.16 11.7 10.8 10.2<br />
FB(G)676 27 x 27<br />
XC7K160T 12.8 5.1 0.09 9.8 8.9 8.3<br />
XC7K325T 11.8 4.0 0.04 9.1 8.1 7.5<br />
XC7K410T 11.1 3.6 0.03 8.5 7.5 7.0<br />
FB(G)900 31 x 31<br />
XC7K325T 11.3 4.1 0.04 8.8 7.9 7.3<br />
XC7K410T 10.6 4.3 0.04 8.3 7.3 6.8<br />
XC7K160T 10.5 4.4 0.41 7.4 6.4 5.8<br />
FF(G)676 27 x 27<br />
XC7K325T 9.5 3.7 0.25 7.1 6.1 5.6<br />
XC7K410T 9.3 3.4 0.19 6.8 5.9 5.4<br />
FF(G)900 31 x 31<br />
XC7K325T 8.4 2.6 0.24 6.1 5.3 5.0<br />
XC7K410T 8.2 2.6 0.19 5.9 5.1 4.7<br />
XC7K355T 8.6 3.6 0.22 6.1 5.3 4.8<br />
FF(G)901 31 x 31<br />
XC7K420T 8.1 3.2 0.19 6.0 5.2 4.7<br />
XC7K480T 7.6 3.2 0.17 5.9 5.1 4.6<br />
FF(G)1156 35 x 35<br />
XC7K420T 7.3 3.2 0.19 5.8 4.9 4.4<br />
XC7K480T 7.0 3.1 0.17 5.6 4.8 4.3<br />
Virtex-7V <strong>FPGAs</strong><br />
FF(G)1157 35 x 35 XC7V585T 6.9 2.2 0.13 5.4 4.6 4.3<br />
FF(G)1761 42.5 x 42.5 XC7V585T 5.9 2.1 0.11 4.6 3.9 3.6<br />
FL(G)1761 42.5 x 42.5 XC7V1500T<br />
FH(G)1761 42.5 x 42.5 XC7V2000T<br />
FL(G)1925 45 x 45 XC7V2000T<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 151<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 5: Thermal Specifications<br />
Table 5-1:<br />
Thermal Resistance Data—All Devices (Cont’d)<br />
Package<br />
Package<br />
Body Size<br />
Devices<br />
JA<br />
(°C/W)<br />
JB<br />
(°C/W)<br />
JC<br />
(°C/W)<br />
JA (°C/W)<br />
@ 250 LFM<br />
JA (°C/W)<br />
@ 500 LFM<br />
JA (°C/W)<br />
@ 750 LFM<br />
Virtex-7VX <strong>FPGAs</strong><br />
XC7VX330T 7.4 2.3 0.18 5.6 4.8 4.4<br />
FF(G)1157 35 x 35<br />
XC7VX415T 7.0 2.1 0.14 5.4 4.7 4.3<br />
XC7VX485T 6.7 2.4 0.11 5.3 4.6 4.2<br />
XC7VX690T 6.1 2.0 0.04 4.8 4.2 3.8<br />
XC7VX415T 6.8 2.2 0.13 5.4 4.7 4.3<br />
FF(G)1158 35 x 35<br />
XC7VX485T 6.4 2.2 0.11 5.2 4.6 4.2<br />
XC7VX550T 6.5 2.1 0.09 5.2 4.5 4.2<br />
XC7VX690T 6.2 2.1 0.04 4.8 4.2 3.8<br />
XC7VX330T 6.4 2.3 0.19 4.8 4.1 3.7<br />
FF(G)1761 42.5 x 42.5<br />
XC7VX485T 5.8 2.0 0.13 4.5 3.9 3.5<br />
XC7VX690T 5.4 1.9 0.09 4.3 3.7 3.4<br />
FF(G)1926 45 x 45<br />
XC7VX690T 4.9 1.8 0.07 4 3.5 3.1<br />
XC7VX980T 4.8 1.7 0.04 3.8 3.2 2.9<br />
XC7VX415T 5.6 1.8 0.14 4.3 3.7 3.3<br />
FF(G)1927 45 x 45<br />
XC7VX485T 5.2 1.8 0.13 4.5 3.8 3.4<br />
XC7VX550T 5.4 1.8 0.09 4.2 3.6 3.3<br />
XC7VX690T 4.9 1.8 0.07 3.8 3.2 2.9<br />
FF(G)1928 45 x 45 XC7VX980T 4.8 1.7 0.04 4.0 3.4 3.1<br />
XC7VX485T 5.5 1.8 0.11 4.3 3.6 3.3<br />
FF(G)1930 45 x 45<br />
XC7VX690T 5.2 1.7 0.04 3.9 3.3 3.0<br />
XC7VX980T 5.0 1.7 0.04 3.8 3.2 2.9<br />
www.BDTIC.com/XILINX<br />
152 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Power Management Strategy<br />
Power Management Strategy<br />
<strong>Xilinx</strong> relies on a multi-prong approach with regards to the heat-dissipating potential of<br />
7 series devices:<br />
• Design <strong>and</strong> Silicon<br />
Significant power reduction in 7 series devices at the 28 nm node is achieved through<br />
innovative process <strong>and</strong> circuit design. For example, transistor static leakage current is<br />
minimized by more than 50 percent (comparable devices) by deploying multi-gate<br />
oxide transistors in the power-efficient 7 series architecture. Despite these<br />
improvements <strong>and</strong> a lower operating voltage, the base transistor counts are higher for<br />
these 7 series devices. They pack higher gate densities <strong>and</strong> the fabric is faster.<br />
Compared to previous generations, the power consumption is lower for the same<br />
design (same function <strong>and</strong> gate density) in a 7 series FPGA implementation.<br />
However, the increased resources <strong>and</strong> functionality associated with these higher gate<br />
density devices <strong>and</strong> faster switching fabric implies that more computation is possible<br />
in shorter time. Associated with this improved functionality is potential higher power<br />
dissipation that would have been worse without the silicon <strong>and</strong> device-based<br />
innovations.<br />
• <strong>Packaging</strong><br />
At the package component level, <strong>Xilinx</strong> has selected the more efficient flip-chip BGA<br />
packages, which present a low thermal path to the outside. This package incorporates<br />
a heat spreader with a thermal interface material (TIM), as shown in Figure 5-1.<br />
X-Ref Target - Figure 5-1<br />
Thermal Interface Material (TIM)<br />
Lid-Heat Spreader<br />
Die<br />
Substrate<br />
<strong>UG475</strong>_c05_01_082610<br />
Figure 5-1:<br />
Heat Spreader with Thermal Interface Material<br />
Materials with better thermal conductivity <strong>and</strong> consistent process applications deliver<br />
low thermal resistance up to the heat spreader. The junction-to-case thermal resistance<br />
(top of heat spreader) of all 7 series FPGA packages is typically less than 0.20°C/W.<br />
These packages deliver a low resistance platform for heat sink applications.<br />
The parallel effort to ensure optimized package electrical return paths has produced an<br />
added benefit of enhanced power <strong>and</strong> ground plane arrangement in the packages. The<br />
boost in copper density on the planes improves the overall thermal conductivity<br />
through the laminate. In addition, the extra dense <strong>and</strong> distributed via fields in the<br />
package increase the vertical thermal conductivity. These packages offer up to 20%<br />
lower JB compared to previous flip-chips packages.<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 153<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 5: Thermal Specifications<br />
• Heat Sinking Solutions at the System Level<br />
Depending on the system's physical as well as mechanical constraints, the expectation<br />
is that the thermal budget is maintained with custom or OEM heat sink solutions,<br />
providing the third prong in the thermal management strategy. At this point, <strong>Xilinx</strong><br />
has left the heat sink solution to the system-level designers who can tailor the design<br />
<strong>and</strong> solution to the constraints of their systems, being fully aware that the part has<br />
certain inherent capabilities for delivering the heat to the surface.<br />
Heat sink solutions do exist <strong>and</strong> can be effective on these low JB flip-chip platforms.<br />
Table 5-2 illustrates a finned heat sink solution matrix in Network environment (1U<br />
<strong>and</strong> 2U) arrangement for 35 mm packages <strong>and</strong> up for power ranging from 15W to 40W.<br />
The AAVID st<strong>and</strong>ard finned heat sink offerings are used to illustrate the coverage<br />
given thermal budgets of T = 35°C <strong>and</strong> T = 45°C scenarios. Other heat sink<br />
configurations can be explored similarly.<br />
Table 5-2:<br />
Package Power<br />
(W)<br />
Finned Heat Sink Solution Matrix for Large Flip-chip BGA in Network<br />
35 x 35 mm<br />
FF1156<br />
42.5 x 42.5 mm<br />
FF1761<br />
T=35°C T=45°C T=35°C T=45°C<br />
15W<br />
25W<br />
35W<br />
40W<br />
1U (5) Note 1 Note 1<br />
2U (6) Note 1 Note 1<br />
1U (5) Note 4 Note 2 Note 4 Note 2<br />
2U (6) Note 2 Note 1 Note 2 Note 1<br />
1U (5) Note 4 Note 3 Note 4 Note 3<br />
2U (6) Note 4 Note 2 Note 4 Note 2<br />
1U (5) – – Note 4 Note 3<br />
2U (6) – – Note 3 Note 2<br />
Notes:<br />
1. Solution available at 200 LFM, for example, AAVID finned part number 68520, 72390, 72415.<br />
2. Solution available at 400 LFM, for example, AAVID finned part number 68520, 69920.<br />
3. Solution available at 600 LFM, for example, AAVID finned part number 72390, 69920, 74590.<br />
4. No st<strong>and</strong>ard. AAVID finned solution below 600 LFM—custom finned might be required.<br />
5. For 1U Height—(max heat sink height = 26 mm)<br />
6. For 2U Height—(max heat sink height = 64 mm<br />
The 7 series FPGA packages can be grouped into medium- <strong>and</strong> high-performance<br />
packages based on their power h<strong>and</strong>ling capabilities. All 7 series FPGA packages can use<br />
thermal enhancements, ranging from simple airflow to schemes that can include passive as<br />
well as active heat sinks. This is particularly true for the bigger flip-chip BGA packages<br />
where system designers have the option to further enhance the packages with bigger <strong>and</strong><br />
more elaborate heat sinks to h<strong>and</strong>le excesses of 25W with arrangements that consider<br />
system –physical constraints as illustrated in Table 5-2.<br />
www.BDTIC.com/XILINX<br />
154 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Some Thermal Management Options<br />
Some Thermal Management Options<br />
The flip-chip thermal management chart in Figure 5-2 illustrates simple but incremental<br />
power management schemes that can be applied on a flip-chip BGA package.<br />
X-Ref Target - Figure 5-2<br />
Low End<br />
1–6W<br />
Bare Package with<br />
Moderate Air<br />
8–12°C/W<br />
Bare Package<br />
Package can be<br />
used with moderate<br />
airflow within a system<br />
Mid Range<br />
4–10W<br />
Passive H/S + Air<br />
5–10°C/W<br />
Packaged Used with<br />
Various Forms of<br />
Passive Heat Sinks<br />
Heat spreader techniques<br />
High End<br />
8–25W<br />
Active Heat Sink<br />
2–3°C/W or Better<br />
Package Used with<br />
Active Heat Sinks<br />
TEC <strong>and</strong> board level<br />
heat spreader techniques<br />
<strong>UG475</strong>_c5_02_082610<br />
Figure 5-2:<br />
Thermal Management Options for Flip-Chip BGA Packages<br />
• For moderate power dissipation (less than 6W), the use of passive heat sinks <strong>and</strong> heat<br />
spreaders attached with thermally conductive double-sided tapes or retainers (with<br />
TIM around 0.2°C/W) can offer quick thermal solutions in these packages.<br />
• The use of lightweight, finned, external, passive heat sinks can be effective for<br />
dissipating up to 10–25W in the bigger packages. The more efficient external heat<br />
sinks tend to be tall <strong>and</strong> heavy. To help protect component joints from heat sink<br />
induced stress cracks, the use of spring-loaded pins or clips that transfer the mounting<br />
stress to a circuit board is advisable whenever a bulky heat sink is considered.<br />
• As stated earlier, the flip-chip BGA packages offered for 7 series devices are thermally<br />
enhanced BGAs with the die facing down. These packages have an exposed metal<br />
heat sink at the top. These high-end thermal packages lend themselves to the<br />
application of efficient external heat sinks (passive or active) for further heat removal<br />
efficiency. Again, precautions must be taken to prevent component damage when a<br />
bulky heat sink is attached. The thermal interface resistance needs to be controlled to<br />
take full advantage of these packages.<br />
• An active heat sink might include a simple heat sink incorporating a mini fan or even<br />
a Peltier Thermoelectric Cooler (TEC) with a fan to carry away any dissipated heat.<br />
When considering the use of a TEC for heat management, consultation with experts in<br />
using the device is important because these devices can be reversed <strong>and</strong> cause<br />
damage to components. Also condensation can be an issue with these devices.<br />
• The printed circuit board on which the package is mounted can have a significant<br />
impact on thermal performance. As much as 60 to 80 percent of the dissipated heat<br />
can go through the BGA balls <strong>and</strong> thus to the board. A typical systems board is larger<br />
than the st<strong>and</strong>ard 4 x 4 in JEDEC thermal board. Components mounted on these<br />
boards with multiple copper layers <strong>and</strong> several internal vias show low effective<br />
junction-to-ambient thermal resistances.<br />
Table 5-3 shows this impact as an FF1156 flip-chip package's effective junction to<br />
ambient resistance is changed depending on the mounting board.<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 155<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 5: Thermal Specifications<br />
Table 5-3:<br />
Impact of Mounted Board Characteristics on JA (FF1156)<br />
<strong>Xilinx</strong> 35 x 35mm<br />
FF1156<br />
JA (°C/W) for Different Board Sizes<br />
4 x 4 in 10 x 10 in 20 x 20 in<br />
4 9.1 (1) 8.3 –<br />
Layer Count of<br />
Mounted Board<br />
8 8.0 5.5 4.9<br />
12 7.5 4.7 4.4<br />
16 7.2 4.5 4.2<br />
Notes:<br />
1. Base JEDEC Mount Conditions<br />
• Designs can be implemented to take advantage of the board's ability to spread heat.<br />
The effect of the board is dependent on its size <strong>and</strong> how it conducts heat. Board size,<br />
the level of copper traces, <strong>and</strong> the number of buried copper planes all lower the<br />
junction-to-ambient thermal resistance for a package mounted on the board. The cold<br />
ring junction-to-board thermal data for 7 series FPGA packages are given in Table 5-1.<br />
Users need to be aware that a direct heat path to the board from a component also<br />
exposes the component to the effect of other heat sources on the board, particularly if<br />
the board is not cooled effectively. An otherwise cooler component can be heated by<br />
other heat contributing components on the board.<br />
Support for Compact Thermal Models (CTM)<br />
24 – 4.3 4.0<br />
Table 5-1 provides the traditional thermal resistance data for 7 series devices. These<br />
resistances are measured using a prescribed JEDEC st<strong>and</strong>ard that might not necessarily<br />
reflect the user’s actual board conditions <strong>and</strong> environment. The quoted JA <strong>and</strong> JC<br />
numbers are environmentally dependent, <strong>and</strong> JEDEC has traditionally recommended that<br />
these be used with that awareness. For more accurate junction temperature prediction,<br />
these might not be enough, <strong>and</strong> a system-level thermal simulation might be required.<br />
Though <strong>Xilinx</strong> continues to support these figure of merit data, for 7 series <strong>FPGAs</strong>,<br />
boundary conditions independent compact thermal models (BCI-CTM) are also available<br />
to assist users in their thermal simulations.<br />
Two-resistor as well as eight to ten-resistor network models are offered for all 7 series<br />
devices. These compact models seek to capture the thermal behavior of the packages more<br />
accurately at predetermined critical points (junction, case, top, leads, <strong>and</strong> so on) with the<br />
reduced set of nodes as illustrated in Figure 5-3.<br />
Unlike a full 3D model, these are computationally efficient <strong>and</strong> work well in an integrated<br />
system simulation environment. Delphi CTM models are available on the <strong>Xilinx</strong> support<br />
download center (under the Device Model tab) at:<br />
http://www.xilinx.com/support/download/index.htm<br />
www.BDTIC.com/XILINX<br />
156 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
References<br />
X-Ref Target - Figure 5-3<br />
DELPHI BCI-CTM Topology for<br />
FCBGA<br />
TI<br />
TO<br />
Two Resistor Model<br />
R jc<br />
Junction<br />
SIDE<br />
Junction<br />
R jb<br />
BI<br />
Figure 5-3:<br />
BO<br />
Thermal Model Topologies<br />
<strong>UG475</strong>_c05_03_082610<br />
The CTM models are based on the DELPHI approach that JEDEC has proposed. Since the<br />
JEDEC neutral (XML) format proposal has not been adopted yet, the DELPHI approach is<br />
used to generate these files <strong>and</strong> the data saved in the NATIVE <strong>and</strong> proprietary file formats<br />
of the targeted CFD tools - rather than follow a neutral file format. The CTM libraries are<br />
available in Flotherm (PDML) format – good for V5.1 <strong>and</strong> above <strong>and</strong> Icepack (version 4.2<br />
<strong>and</strong> above) format.<br />
References<br />
The following websites contain additional information on heat management <strong>and</strong> contact<br />
information.<br />
• http://www.wakefield.com<br />
• http://www.aavidthermalloy.com<br />
• http://www.qats.com<br />
Refer to the following websites for interface material sources:<br />
• Power Devices - http://www.powerdevices.com<br />
• Bergquist Company - http://www.bergquistcompany.com<br />
• AOS Thermal Compound - http://www.aosco.com<br />
• Chometrics - http://www.chomerics.com<br />
• Kester - http://www.kester.com<br />
Refer to the following websites for CFD tools <strong>Xilinx</strong> supports with thermal models.<br />
• Flomerics - Flotherm & FloPCB - http://www.flomerics.com<br />
• Fluent - Icepak - http://www.icepak.com<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 157<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 5: Thermal Specifications<br />
www.BDTIC.com/XILINX<br />
158 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 6<br />
Package Marking<br />
All 7 series devices have package top-markings similar to the examples shown in<br />
Figure 6-1 <strong>and</strong> Figure 6-2 <strong>and</strong> explained in Table 6-1.<br />
X-Ref Target - Figure 6-1<br />
Device Type<br />
Package<br />
Speed Grade<br />
XC7K325T TM<br />
FF900xxxXXXX<br />
DDxxxxxxxA<br />
1C ES<br />
Date Code<br />
Lot Code<br />
Engineering Sample<br />
Operating Range<br />
ug475_c6_01_031511<br />
Figure 6-1:<br />
Kintex-7 Device Package Marking<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 159<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Chapter 6: Package Marking<br />
X-Ref Target - Figure 6-2<br />
Device Type<br />
Package<br />
Speed Grade<br />
XC7VX485T TM<br />
FFG1761xxxXXXX<br />
DDxxxxxxxA<br />
1C ES<br />
Date Code<br />
Lot Code<br />
Engineering Sample<br />
Operating Range<br />
ug475_c6_02_081011<br />
Table 6-1:<br />
Item<br />
Figure 6-2:<br />
<strong>Xilinx</strong> Device Marking Definition—Example<br />
Virtex-7 Device Package Marking<br />
Definition<br />
<strong>Xilinx</strong> Logo<br />
Family Br<strong>and</strong><br />
Logo<br />
1st Line<br />
2nd Line<br />
3rd Line<br />
<strong>Xilinx</strong> logo, <strong>Xilinx</strong> name with trademark, <strong>and</strong> trademark-registered status.<br />
Device family name with trademark <strong>and</strong> trademark-registered status. This line is optional <strong>and</strong> could<br />
appear blank.<br />
Device type.<br />
Package code, circuit design revision, the location code for the wafer fab, the geometry code, <strong>and</strong> date<br />
code.<br />
A G in the third letter of a package code indicates a Pb-free RoHS compliant package. For more details<br />
on <strong>Xilinx</strong> Pb-Free <strong>and</strong> RoHS Compliant Products, see: http://www.xilinx.com/pbfree.<br />
Ten alphanumeric characters for Assembly, Lot, <strong>and</strong> Step information. The last digit is usually an A or<br />
an M if a stepping version does not exist.<br />
Device speed grade <strong>and</strong> temperature range. When not marked on the package, the product is<br />
considered to operate at the commercial (C) temperature range. For more information on the ordering<br />
codes, see DS180: 7 <strong>Series</strong> <strong>FPGAs</strong> Overview.<br />
Other variations for the 4th line:<br />
4th Line<br />
L2E The L2E indicates a -2LE device. The -2L devices operate at either of two voltages, 0.9V<br />
<strong>and</strong> 1.0V. The E is for the extended temperature operating range. For more information,<br />
see the specific device’s data sheet at:<br />
http://www.xilinx.com/support/documentation/7_series.htm#156339.<br />
1C xxxx<br />
1C ES<br />
The xxxx indicates the SCD for the device. An SCD is a special ordering code that is not<br />
always marked in the device top mark.<br />
The ES indicates an Engineering Sample.<br />
www.BDTIC.com/XILINX<br />
160 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011
Appendix A<br />
Recommended PCB Design Rules for<br />
BGA Packages<br />
<strong>Xilinx</strong> provides the diameter of a l<strong>and</strong> pad on the component side. This information is<br />
required prior to the start of the board layout so the board pads can be designed to match<br />
the component-side l<strong>and</strong> geometry. The typical values of these l<strong>and</strong> pads are described in<br />
Figure A-1 <strong>and</strong> summarized in Table A-1. For <strong>Xilinx</strong>® BGA packages, Non-Solder Mask<br />
Defined (NSMD) pads on the board are suggested to allow a clearance between the l<strong>and</strong><br />
metal (diameter L) <strong>and</strong> the solder mask opening (diameter M) as shown in Figure A-1. The<br />
space between the NSMD pad <strong>and</strong> the solder mask as well as the actual signal trace widths<br />
depend on the capability of the PCB vendor. The cost of the PCB is higher when the line<br />
width <strong>and</strong> spaces are smaller.<br />
X-Ref Target - Figure A-1<br />
VL<br />
W<br />
VH<br />
D<br />
L<br />
M<br />
Mask Opening outside of L<strong>and</strong><br />
e<br />
<strong>UG475</strong>_aA_01_082610<br />
Figure A-1:<br />
Suggested Board Layout of Soldered Pads for BGA Packages<br />
www.BDTIC.com/XILINX<br />
7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong> www.xilinx.com 161<br />
<strong>UG475</strong> (v1.4) October 17, 2011
Appendix A: Recommended PCB Design Rules for BGA Packages<br />
Table A-1:<br />
Recommended PCB Design Rules for All FF(G) Packages<br />
Design Rule<br />
FF(G) Packages<br />
(Dimensions in mm)<br />
Component L<strong>and</strong> Pad Diameter (SMD) (1) 0.53<br />
Solder L<strong>and</strong> (L) Diameter 0.45<br />
Opening in Solder Mask (M) Diameter 0.55<br />
Solder (Ball) L<strong>and</strong> Pitch (e) 1.00<br />
Line Width Between Via <strong>and</strong> L<strong>and</strong> (w) 0.13<br />
Distance Between Via <strong>and</strong> L<strong>and</strong> (D) 0.70<br />
Via L<strong>and</strong> (VL) Diameter 0.61<br />
Through Hole (VH) Diameter 0.300<br />
Notes:<br />
1. Component l<strong>and</strong> pad diameter refers to the pad opening on the component side (solder<br />
mask defined).<br />
www.BDTIC.com/XILINX<br />
162 www.xilinx.com 7 <strong>Series</strong> <strong>FPGAs</strong> <strong>Packaging</strong><br />
<strong>UG475</strong> (v1.4) October 17, 2011