TMS320C5515 Evaluation Module (EVM) - Spectrum Digital Support
TMS320C5515 Evaluation Module (EVM) - Spectrum Digital Support
TMS320C5515 Evaluation Module (EVM) - Spectrum Digital Support
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1<br />
2<br />
3<br />
4<br />
5<br />
<strong>Spectrum</strong> <strong>Digital</strong>, Inc<br />
D RN5 RPACK8-22<br />
U13C<br />
D<br />
7,9<br />
7,8,9<br />
8,9<br />
7,9<br />
RN7 RPACK8-22<br />
CPU_A5 D1<br />
CPU_SDRAS R151 0<br />
SDRAS<br />
A2<br />
CPU_A2<br />
CPU_A4<br />
EM_A[5]<br />
SDRASn<br />
A6<br />
CPU_SDCAS<br />
SDCAS<br />
SDRAS 7<br />
C 7,9 A2<br />
8 9<br />
C1<br />
R152 22<br />
C<br />
A5<br />
CPU_A5<br />
CPU_A3<br />
EM_A[4]<br />
SDCASn<br />
B4<br />
SDCAS 7<br />
7,9 A5<br />
7 10<br />
D2<br />
A3<br />
CPU_A3<br />
CPU_A2<br />
EM_A[3]<br />
7,9 A3<br />
6 11<br />
E1<br />
CPU_SDCLK R159 22 SDCLK<br />
A4<br />
CPU_A4<br />
CPU_A1<br />
EM_A[2]<br />
EM_SDCLK M3<br />
SDCLK 7<br />
7,9 A4<br />
5 12<br />
C2<br />
7,9 A0<br />
A0<br />
CPU_A0<br />
CPU_A0<br />
EM_A[1]<br />
4 13<br />
B2<br />
CPU_SDCKE<br />
SDCKE<br />
A1<br />
CPU_A1<br />
CPU_BA1<br />
EM_A[0]<br />
SDCKE N2<br />
R158 22<br />
SDCKE 7<br />
7,9 A1<br />
3 14<br />
B1<br />
7,9 BA0<br />
BA0<br />
2 15<br />
CPU_BA0<br />
CPU_BA0<br />
EM_BA[1]<br />
A1<br />
CPU_SDCE0 R150 22 SD_CEXn<br />
BA1<br />
CPU_BA1<br />
EM_BA[0]<br />
SD_CE0n<br />
B3<br />
SD_CEXn 7<br />
7,9 BA1<br />
1 16<br />
R283 NO-POP<br />
SD_CE1n<br />
A4<br />
CPU_EM_CS2n R153 22 EM_CS2n<br />
EM_CS2n<br />
C5<br />
CPU_EM_CS3n<br />
EM_CS2n 9<br />
R17 R15<br />
EM_CS3n<br />
M4<br />
CPU_EM_CS4n R154 22 EM_CS4n<br />
10K 10K<br />
EM_CS4n<br />
C3<br />
CPU_EM_CS5n<br />
EM_CS4n 8<br />
DVDDEMIF EM_CS5n<br />
A3<br />
B B<br />
A SPECTRUM DIGITAL INCORPORATED<br />
A<br />
9<br />
9<br />
9<br />
9<br />
9<br />
9<br />
9<br />
9<br />
8<br />
8 9<br />
D15<br />
A15<br />
CPU_A15<br />
CPU_A20<br />
EM_D[15]<br />
J4<br />
D15 7,9<br />
A15<br />
7 10<br />
J3<br />
D14<br />
A14<br />
CPU_A14<br />
CPU_A19<br />
EM_A[20]/GP[26]<br />
EM_D[14]<br />
K3<br />
D14 7,9<br />
A14<br />
6 11<br />
G4<br />
D13<br />
A10<br />
CPU_A10<br />
CPU_A18<br />
EM_A[19]/GP[25]<br />
EM_D[13]<br />
K4<br />
D13 7,9<br />
A10<br />
5 12<br />
G2<br />
D12<br />
D12 7,9<br />
A13<br />
CPU_A13<br />
CPU_A17<br />
EM_A[18]/GP[24]<br />
EM_D[12]<br />
L3<br />
A13<br />
4 13<br />
F2<br />
D11<br />
D11 7,9<br />
A11<br />
A11<br />
CPU_A11<br />
CPU_A16<br />
EM_A[17]/GP[23]<br />
EM_D[11]<br />
C4<br />
3 14<br />
E2<br />
D10<br />
D10 7,9<br />
A12<br />
A12<br />
CPU_A12<br />
CPU_A15<br />
EM_A[16]/GP[22]<br />
EM_D[10]<br />
D3<br />
2 15<br />
N1<br />
D9<br />
D9 7,9<br />
A9<br />
A9<br />
CPU_A9<br />
CPU_A14<br />
EM_A[15]/GP[21]<br />
EM_D[9]<br />
F4<br />
1 16<br />
M1<br />
D8<br />
EM_A[14]<br />
EM_D[8]<br />
E3<br />
D8 7,9<br />
7,9<br />
9<br />
7,9<br />
7,9<br />
RN6 RPACK8-22<br />
A8<br />
A8<br />
8 9<br />
CPU_A8<br />
CPU_A13 L1<br />
D7<br />
A20<br />
CPU_A20<br />
CPU_A12<br />
EM_A[13]<br />
EM_D[7]<br />
H3<br />
D7 7,8,9<br />
A20<br />
7 10<br />
K1<br />
D6<br />
A7<br />
CPU_A7<br />
CPU_A11<br />
EM_A[12]/(CLE)<br />
EM_D[6]<br />
K5<br />
D6 7,8,9<br />
A7<br />
6 11<br />
K2<br />
D5<br />
A19<br />
CPU_A19<br />
CPU_A10<br />
EM_A[11]/(ALE)<br />
EM_D[5]<br />
M2<br />
D5 7,8,9<br />
A19<br />
5 12<br />
L2<br />
D4<br />
D4 7,8,9<br />
A18<br />
A18<br />
CPU_A18<br />
CPU_A9<br />
EM_A[10]<br />
EM_D[4]<br />
L4<br />
4 13<br />
J2<br />
D3<br />
D3 7,8,9<br />
A17<br />
A17<br />
3<br />
CPU_A17<br />
CPU_A8<br />
EM_A[9]<br />
EM_D[3]<br />
D4<br />
14<br />
J1<br />
D2<br />
D2 7,8,9<br />
A6<br />
A6<br />
2 15<br />
CPU_A6<br />
CPU_A7<br />
EM_A[8]<br />
EM_D[2]<br />
F3<br />
H2<br />
D1<br />
D1 7,8,9<br />
A16<br />
A16<br />
1 16<br />
CPU_A16<br />
CPU_A6<br />
EM_A[7]<br />
EM_D[1]<br />
E5<br />
F1<br />
D0<br />
EM_A[6]<br />
EM_D[0]<br />
G3<br />
D0 7,8,9<br />
CPU_DQM1 R119 22 DQM1<br />
DQM1 7<br />
EM_DQM1<br />
P1<br />
CPU_DQM0 R118 22 DQM0<br />
EM_DQM0<br />
B5<br />
DQM0 7<br />
CPU_RnW<br />
EM_WAIT2<br />
EM_R/Wn<br />
B6<br />
EM_WAIT2<br />
D5<br />
EM_WAIT3<br />
EM_WAIT2<br />
K6<br />
CPU_WE<br />
R156 22 WE<br />
EM_WAIT4<br />
EM_WAIT3<br />
EM_WEn<br />
H1<br />
WE 7,8,9<br />
EM_WAIT4<br />
G1<br />
EM_WAIT5<br />
EM_WAIT4<br />
H4<br />
CPU_OE<br />
OE<br />
EM_WAIT5<br />
EM_OEn<br />
E4<br />
R155 22<br />
OE 8,9<br />
<strong>TMS320C5515</strong><br />
Title:<br />
<strong>TMS320C5515</strong> EVALUATION MODULE<br />
Page Contents:<br />
<strong>TMS320C5515</strong> EMIF<br />
Revision:<br />
Size: B<br />
DWG NO 512702-0001<br />
A<br />
Date:<br />
Sheet o f Monday, February 01, 2010 6 20<br />
A-7
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