TMS320C5515 Evaluation Module (EVM) - Spectrum Digital Support

TMS320C5515 Evaluation 

Module (EVM) 

Technical 

Reference 

2010 DSP Development Systems

TMS320C5515 Evaluation 

Module (EVM) 

Technical Reference 

512705-0001 Rev. A 

February 2010 

SPECTRUM DIGITAL, INC. 

12502 Exchange Drive, Suite 440 Stafford, TX. 77477 

Tel: 281.494.4505 Fax: 281.494.5310 

sales@spectrumdigital.com www.spectrumdigital.com

IMPORTANT NOTICE 

Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any 

product or service without notice. Customers are advised to obtain the latest version of relevant 

information to verify that the data being relied on is current before placing orders. 

Spectrum Digital, Inc. warrants performance of its products and related software to current 

specifications in accordance with Spectrum Digital’s standard warranty. Testing and other quality 

control techniques are utilized to the extent deemed necessary to support this warranty. 

Please be aware that the products described herein are not intended for use in life-support 

appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for 

the product described herein to be used in other than a development environment. 

Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, 

software performance, or infringement of patents or services described herein. Nor does Spectrum 

Digital warrant or represent any license, either express or implied, is granted under any patent right, 

copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any 

combination, machine, or process in which such Digital Signal Processing development products or 

services might be or are used. 

WARNING 

This equipment is intended for use in a laboratory test environment only. It generates, uses, and can 

radiate radio frequency energy and has not been tested for compliance with the limits of computing 

devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable 

protection against radio frequency interference. Operation of this equipment in other environments 

may cause interference with radio communications, in which case the user at his own expense will be 

required to take whatever measures necessary to correct this interference. 

WARNING 

To minimize risk of electric shock hazard, use only the following 

power supply for the EVM module with Medical Development 

Applications: SL Power AULT Model MW173KB0503F01. 

Copyright © 2010 Spectrum Digital, Inc.

Contents 

1 Introduction to the TMS320C5515 Evaluation Module . . . . . . . . . . . . . . . . . . . . . . . 1-1 

Provides you with a description of the TMS320C5515 EVM, key features, and block diagram. 

1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 

1.2 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 

1.3 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 

1.4 C5515 GPIO Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 

1.5 C5515 EVM Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 

1.6 C5515 I 2 C Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 

2 Operation and Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 

Describes the operation and physical layout of the TMS320C5515 EVM and its connectors. 

2.1 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 

2.2 Connector Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 

2.2.1 J1, RS-232 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 

2.2.2 J2, Embedded USB Emulation Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 

2.2.3 J3, I 2 C Probe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 

2.2.4 J4, Headphone Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 

2.2.5 J5, HDR4 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 

2.2.6 J6, I 2 C Probe Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 

2.2.7 J7, Stereo Out Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 

2.2.8 J8, External JTAG Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 

2.2.9 J9, Stereo In 1 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 

2.2.10 J10, Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 

2.2.11 J11, USB Type B Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 

2.2.12 J12, Stereo In 2 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 



2.2.15 J15, MMC/SD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 

2.2.16 J16, +5 Volt In Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 

2.2.17 J17, Embedded Emulation Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 

2.2.18 J18, Battery Holder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 

2.2.19 J19, Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 

2.2.20 M1, Left Microphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 

2.2.21 M2, Right Microphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 

2.2.22 Blue Tooth Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 

2.2.22.1 P1, Blue Tooth Board Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 

2.2.22.2 P2, Blue Tooth Board Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 

2.3 System LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.4 C5515 EVM Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 

2.4.1 SW1, RESET Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 

2.4.2 SW2, WAKEUP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 

2.4.3 SW4, LDO Option DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 

2.4.4 SW5, On/Off Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 

2.4.5 SW6-SW15, Function Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 

2.5 Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 

2.5.1 C5515 EVM Option Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 

2.5.1.1 JP2, nRESET Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 

2.5.1.2 JP3, UART_EN Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 

2.5.1.3 JP5, WAKEUP Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 

2.5.1.4 JP6, LDO_EN Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 

2.5.1.5 JP9, CLK_SEL Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 

2.5.1.6 JP12, MIC_BIAS Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 

2.5.1.7 JP39, VIN Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 

2.5.2 C5515 EVM Power Domain Probe Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 

2.6 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 

A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 

Contains the schematics for the TMS320C5515 EVM 

B Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 

Contains the mechanical information about the TMS320C5515 EVM

About This Manual 

Notational Conventions 

This document describes the board level operations of the TMS320C5515 

Evaluation Module (EVM). The EVM is based on the Texas Instruments 

TMS320C5515 Digital Signal Processor. 

The TMS320C5515 EVM is a table top card to allow engineers and software 

developers to evaluate certain characteristics of the TMS320C5515 DSP to 

determine if the processor meets the designers application requirements. Evaluators 

can create software to execute on board or expand the system in a variety of ways. 

The TMS320C5515 EVM can be used to develop TMS320C5504 applications since 

the TMS320C5504 processor is a subset of the TMS320C5515. 

This document uses the following conventions. 

The TMS320C5515 will sometimes be referred to as the C55XX. 

The TMS320C5515 EVM will sometimes be referred to as the EVM. 

Program listings, program examples, and interactive displays are shown is a special 

italic typeface. Here is a sample program listing. 

equations 

!rd = !strobe&rw; 

Information About Cautions 

This book may contain cautions. 

This is an example of a caution statement. 

A caution statement describes a situation that could potentially damage your software, 

or hardware, or other equipment. The information in a caution is provided for your 

protection. Please read each caution carefully. 

Related Documents 

Texas Instruments TMS320C55XX DSP CPU Reference Guide 

Texas Instruments TMS320C55XX DSP Peripherals Reference Guide

Table 1: Hardware History 

Revision 

A 

B 

History 

Prototype Release 

Production Release 

Table 2: Manual History 

Revision 

A 

Production Release 

History

Chapter 1 

Introduction to the 

TMS320C5515 EVM 

Chapter One provides a description of the TMS320C5515 EVM 

along with the key features and a block diagram of the circuit board. 

Topic 

Page 

1.1 Key Features 1-2 

1.2 Development Tools 1-3 

1.3 Power Supply 1-3 

1.4 C5515 GPIO Terminal Functions 1-4 

1.5 C5515 EVM Memory Map 1-7 

1.6 C5515 I 2 C Addressing 1-8 

1-1

Spectrum Digital, Inc 

1.1 Key Features 

The C5515 EVM is a standalone development platform that enables users to 

evaluate and develop applications for the TI TMS320C5515 Digital Signal Processor 

(DSP). The EVM also serves as a hardware reference design for the TMS320C5515 

DSP. Schematics, logic equations and application notes are available to ease 

hardware development and reduce time to market. 

The EVM comes with a full complement of on-board devices that suit a wide 

variety of application environments. Key features include: 

• A Texas Instruments TMS320C5515 DSP operating up to 100 Mhz. 

• 128 Mbytes of Mobile SDRAM 

• 16 Megabytes of NOR Flash 

• 64 Megabytes of NAND Flash 

• 128 x 128 bit mapped color LCD display 

Figure 1-1, TMS320C5515 EVM 

1-2 TMS320C5515 EVM Technical Reference


• TPS65023 Power Management IC for individual C5515 power rail control 

• TLV320AIC3204 stereo codec with line in, line out, headphone, mic in, on board 

microphones 

• MMC / SD Media Card Connector 

• User USB 2.0 port via C5515 

• I 2 C EEPROM (256Kbits) and SPI EEPROM (256Kbits) 

• Expansion connectors for Blue Tooth interface 

• RS-232 Interface 

• External JTAG emulation interface 

• Embedded JTAG controller 

• 10 User push button switches 

• INA219 power measurement devices 

• Optional battery power 

1.2 Development Tools 

The EVM is designed to work with TI’s Code Composer Studio (CCS) Integrated 

Development Environment (IDE). Code Composer Studio communicates with the EVM 

board through the external emulator header, or on board emulation. An EVM specific 

version of Code Composer Studio ships with the EVM. 

1.3 Power Supply 

The EVM operates from a +5V external power supply or battery. 

WARNING 

To minimize risk of electric shock hazard, use only the following 

power supply for the EVM module with Medical Development 

Applications: SL Power AULT Model MW173KB0503F01. 

1-3


1.4 C5515 GPIO Terminal Functions 

The C5515 has multiple GIO signals that can be used for system level tasks. The GIO 

signals are connected to various connectors on the EVM. Refer to the discussion of the 

connectors later in this document for details. The next table describes how the GIO 

lines are used on the EVM. 



Table 1: C5515 GPIO Terminal Functions 

C5515 Pin # 

C5515 Default 

Multiplexed 

Function 

GPIO Pin Routed To 

M8 XF XF LED D2, TP4 

L10 MMC0_CLK GP[0] MMC0_CLK = SH16, J15-5, MMC/SD connector 

GP[0] = SH18, ADS_GPIO0, J13-12 

M11 MMC0_CMD GP[1] MMC0_CMD = SH16, J15-2, MMC/SD connector 

GP[1] = SH18, ADS_GPIO1, J13-8 

L9 MMC0_DATA0 GP[2] MMC0_DATA0 = SH16, J15-7, MMC/SD connector 

GP[2] = SH18, ADS_GPIO2, J13-22 

M10 MMC0_DATA1 GP[3] MMC0_DATA1 = SH16, J15-8, MMC/SD connector 

GP[3] = SH18, ADS_GPIO3, J13-21 

L12 MMC0_DATA2 GP[4] 


M13 MMC1_CLK GP[6] 

L14 MMC1_CMD GP[7] 

M14 MMC1_DATA0 GP[8] 

M12 MMC1_DATA1 GP[9] 

K14 MMC1_DATA2 GP[10] 

MMC0_DATA2 = SH16, J15-9, MMC/SD connector 

GP[4] = SH5, GPIO4, P1-10 

GP[4] = SH18, ADS_GPIO4, J13-1 

MMC0_DATA3 = SH16, J15-1, MMC/SD connector 

GP[5] = SH5, GPIO, P1-12 

GP[5] = SH18, ADS_GPIO5, TP14 

MMC1_CLK, SH5, P1-15, Blue Tooth Board Interface 

GP[6] = SH18, I2S1_CLK, J13-5 

GP[6] = SH5, I2S1_CLK_CC, P2-17 

GP[6] = SH16, MMC0_WP, J15-WP, TP19 

MMC1_CMD = SH5, P1-17, Blue Tooth Board Interface 

GP[7] =I2S1_FS, SH18, J13-9 

GP[7] = I2S1_FS_CC, SH5, P2-11 

GP[7] = MMC0_INS, SH16, J15-Card Detect, TP22 

MMC1_DATA0 = SH5, P1-2, Blue Tooth Board Interface 

GP[8] = I2S1_DX, SH18, J13-19 

GP[8] = I2S1_DX_CC, SH5, P2-8 


GP[9] = I2S1_RX, SH18, J13-14 

GP[9] = I2S1_RX_CC, SH5, P2-10 

MMC1_DATA2, SH5, P1-6, Blue Tooth Board Interface 

GP[10] = AIC_RST, SH19, U12-31 

GP[10] = ADS_GPIO10, SH18, J13-6 



GP[11] = GPIO, SH18, J13-11 

GP[11] = GPIO11_LCD_PWR, SH20, J19-?? 

P6 LCD_DATA0 SPI_RX LCD_DATA0 = SH20, J19-14 

Input LCD_DATA0 = SPI_ALT_RX , SH5, P1-20 

N6 LCD_DATA1 SPI_TX LCD_DATA1 = SH20, J19-13 

LCD_DATA1 = SPI_ALT_D, SH5, P1-18 

P7 LCD_DATA2 GP[12] LCD_DATA2 = SH20, J19-12 

LCD_DATA2 = GPIO12, SH5, P2-13 

N7 LCD_DATA3 GP[13] LCD_DATA3 = SH20, J19-11 

LCD_DATA3 = GPIO13, SH5, P2-20 


LCD_DATA4 = GPIO14_CC, SH5, P2-15 




N10 LCD_DATA8 GP[18] 

LCD_DATA8 = I2S2_CLK, SH19, U12-2 

LCD_DATA8 = SPI_CLK, SH17, U9-6 

LCD_DATA8 = SPI_CLK, SH18, J13-3 

LCD_DATA8 = I2S2_CLK, SH19, U12-2 

1-5


Table 1: C5515 GPIO Terminal Functions 

C5515 Pin # 

C5515 Default 

Multiplexed 

Function 

GPIO Pin Routed To 

P11 LCD_DATA9 GP[19] 

N11 LCD_DATA10 GP[20] 

LCD_DATA9 = I2S2_FS, SH19, U12-3 

LCD_DATA9 = SPI_CS0, SH17, U9-1 

LCD_DATA9 = SPI_CS0, SH18, J13-7 

LCD_DATA9 = I2S2_FS, SH19, U12-3 

LCD_DATA10 = I2S2_RX, SG 19, U12-5 

LCD_DATA10 = SPI_RX, SH17, U9-2 

LCD_DATA10 = SPI_RX, SH18, J13-13 

LCD_DATA10 = I2S2_RX, SH19, U12-5 

P12 LCD_DATA11 GP[27] 

LCD_DATA11 = I2S2_DX, SH19, U12-4 

LCD_DATA11 = SPI_DX, SH17, U9-5 

LCD_DATA11 = SPI_DX, SH18, J13-11 

LCD_DATA11 = I2S2_DX, SH19, U12-4 

N12 LCD_DATA12 GP[28] LCD_DATA12 = UART_RTS, SH5, P1-3 

LCD_DATA12 = UART_RTX, SH17, U5-12 

P13 LCD_DATA13 GP[29] LCD_DATA13 = UART_CTS, SH5, P2-18 

LCD_DATA12 = UART_CTS, SH 17, U5-10 

N13 LCD_DATA14 GP[30] LCD_DATA14 = UART_RX, SH5, P1-7 

LCD_DATA14 = UART_RX, SH17, U5-15 

P14 LCD_DATA15 GP[31] LCD_DATA15 = UART_TX, SH5, P1-9 

LCD_DATA15 = UART_TX, SH17, U5-13 

N3 LCD_EN_RDB SPIO_CLK LCD_EN_RDB = LCD_RE, SH20, J19-15 

LCD_EN_RDB = LCD_RE = SPI_ALT_CLK, SH5, P1-16 

P4 LCD_CS0_E0 SPI_CS0 LCD_CS0_E0 = LCD_BIAS_OE, SH20, J19-19 

N4 LCD_CS1_E1 SPI_CS1 LCD_CS1_E1 = LCD_MCLK = SPI_ALT_CS1, SH5, P1-14 

P5 LCD_RW_WRB SPI_CS2 LCD_RW_WRB = LCD_nWE, SH20, J19-16 

N5 LCD_RS SPI_CS3 LCD_RS = LCD_ALE, SH20, J19-20 



1.5 C5515 EVM Memory Map 

The C5515 EVM supports on chip DARAM, off chip SDRAM, off chip NOR flash, and 

off chip NAND Flash. The addressing for each of these memory blocks is shown in the 

figure below. 

CPU Byte 

Address 

000000h 

0000C0h 

010000h 

MEMORY BLOCKS 

(MMR Reserved) 

Internal DARAM 

Internal DARAM 

050000h 

800000h 

C00000h 

E00000h 

F00000h 

FE0000h 

ROM 

(if MPNMC=0) 

Mobile SDRAM 

External-CS0 Space 

NOR Flash 


Not Used 


NAND Flash 


Not Used 



(if MPNMC=1) 

FFFFFFh 

Figure 1-2, EVM C5515 Memory Map 

1-7


1.6 C5515 I 2 C Addressing 

The C5515 EVM has multiple I 2 C devices for different purposes. The table below 

shows the addresses of these devices on the I2C bus. 

Table 2: C5515 GIO Schedule 

EVM I 2 C Device I 2 C Address Function 

TLV320AIC3204 0x18 Audio CODEC 

INA219 0x40 CPU core power measurement, 

VDDC, U3 

INA219 0x42 CPU DVDD EMIF power measurement, 

DC_VDD_IO2 U7 

INA219 0x43 CPU USB LDO power measurement, 

USB_VDD_IN, U21 

INA219 0x44 CPU DVDD IO power measurement, 

DC_VDD_IO1, U20 

INA219 0x45 CPU 3V3 power measurement, 

3.3V, U27 


1.8V, U23 


5V, U24 

TPS62023 0x48 PMIC - Not Used 

CAT24WC256X 0x50 I 2 C Interface EEPROM 


Chapter 2 

Physical Description 

This chapter describes the physical layout of the TMS320C5515 EVM 

and its connectors. 

Topic 

Page 

2.1 Board Layout 2-3 

2.2 Connector Index 2-5 

2.2.1 J1, RS-232 Connector 2-6 

2.2.2 J2, Embedded USB Emulation Connector 2-7 

2.2.3 J3, I 2 C Probe 2-7 

2.2.4 J4, Headphone Connector 2-8 

2.2.5 J5, HDR4 Connector 2-8 

2.2.6 J6, I 2 C Probe 2-9 

2.2.7 J7, Stereo Out Connector 2-9 

2.2.8 J8, External JTAG Header 2-10 

2.2.9 J9, Stereo In 1 Connector 2-10 

2.2.10 J10, Daughter Card Interface 2-11 

2.2.11 J11, USB Type B Connector 2-11 

2.2.12 J12, Stereo In 2 Connector 2-12 



2.2.15 J15, MMC/SD Connector 2-14 

2.2.16 J16, +5 Volt In Connector 2-15 

2.2.17 J18, Battery Holder 2-15 

2.2.18 J19, Display Interface 2-16 

2.2.19 M1, Left Microphone 2-16 

2.2.20 M2, Right Microphone 2-16 

2.2.21 Blue Tooth Board Interface 2-17 

2.2.21.1 P1, Blue Tooth Board Interface Connector 2-17 

2.2.21.2 P2, Blue Tooth Board Interface Connector 2-18 

2-1


Topic 

Page 

2.3 System LEDs 2-18 

2.4 C5515 EVM Switches 2-19 

2.4.1 SW1, RESET Switch 2-19 

2.4.2 SW2, WAKEUP Switch 2-19 

2.4.3 SW4, LDO Option DIP Switches 2-20 

2.4.4 SW5, On/Off Switch 2-20 

2.4.5 SW6-SW15, Function Switches 2-21 

2.5 Jumpers 2-22 

2.5.1 C5515 EVM Option Jumpers 2-23 

2.5.1.1 JP2, nRESET Source Select 2-25 

2.5.1.2 JP3, UART_EN Select 2-25 

2.5.1.3 JP5, WAKEUP Source Select 2-26 

2.5.1.4 JP6, LDO_EN Source Select 2-26 

2.5.1.5 JP9, CLK_SEL Source Select 2-27 

2.5.1.6 JP12, MIC_BIAS Source Select 2-27 

2.5.1.7 JP39, VIN Source Select 2-28 

2.5.2 C5515 EVM Power Domain Probe Points 2-29 

2.6 Test Points 2-31 



2.1 Board Layout 

The C5515 EVM is a 6.35 x 5.75 inch (161 x 146 mm.) ten (10) layer board which 

is powered by an external +5 volt only power supply. Figure 2-1 shows the layout of the 

top side of the C5515 EVM. 

J1 

DS1 

P1 

J10 

P2 

J3 

D2 

SW1 

SW2 

M1 

J2 

J5 

J4 

J6 

J8 

J7 

J13 

J11 

J9 

J14 

J12 

J15 

SW4 

M2 

SW5 

SW8 

J16 

SW12 

SW9 

SW6 

SW10 

SW13 

SW14 

SW11 

SW15 

SW7 

D8 

Figure 2-1, TMS320C5515 EVM (Top) 

2-3


Figure 2-2 shows the layout of the bottom side of the C5515 EVM. 

J18 

Figure 2-2, TMS320C5515 EVM (Bottom) 

J19 



2.2 Connector Index 

The TMS320C5515 EVM has twenty-three (23) connectors which provide the user 

access to the various signals on the EVM. 

Table 1: New TMS320C5515 EVM Connectors 

Connector / 

Schematic 

Page 

# Pins Function 

Board 

Side 

J1 / 17 9 RS-232 Top 

J2 / 25 5 Embedded USB Emulation Port Top 

J3 / 15 3 I 2 C Probe Top 

J4 / 19 2 Headphones Out Top 

J5 / 19 4 HDR4 Connector Top 

J6 / 2 3 I 2 C Probe Headers Top 

J7 / 19 2 Stereo Out Top 

J8 / 4 14 JTAG Header Top 

J9 / 19 2 Stereo In 1 Top 

J10 / 18 10 Daughter Card Interface Top 

J11 / 3 4 USB Type B Connector Top 

J12 / 19 2 Stereo In 2 Top 



J15 / 16 18 MMC/SD Card Top 

J16 / 13 2 +5 Volt In Top 

J17 / 23 10 Factory use only Bottom 

J18 / 13 2 Battery Holder Bottom 

J19 / 20 30 Display Interface Bottom 

M1 / 19 2 Left Microphone Top 

M2 / 19 2 Right Microphone Top 

P1 / 5 20 Blue Tooth Board Interface Top 

P2 / 5 20 blue tooth Board Interface Top 

2-5


2.2.1 J1, RS-232 Connector 

The C5515 EVM has an RS-232 connector, J1, which brings out the transmit and 

receive of the processor. This EVM uses the MAX3222 RS-232 line driver. The pin 

positions for the J1 connector as viewed from the edge of the printed circuit board are 

shown below. 

1 2 3 4 5 

6 7 8 9 

Figure 2-3, J1, DB9 Male Connector 

The pin numbers and their corresponding signals are shown in the table below. This 

corresponds to a DB-9 connector interface used on personal computers. 

Table 2: J1, RS-232 UART Pinout 

Pin # 

Signal Name 

1 No Connect 

2 RXD 

3 TXD 

4 No Connect 

5 No Connect 

6 No Connect 

7 RTS 

8 CTS 

9 GND 

10 GND_SHIELD 

11 GND_SHIELD 



2.2.2 J2, Embedded USB Emulation Connector 

Connector J2 provides a Mini-B Universal Serial Bus (USB) Interface to the embedded 

JTAG emulation logic on the EVM. This allows for code development and debug 

without the use of an external emulator. This USB connector is for embedded emulation 

support only. 

2.2.3 J3, I 2 C Probe Headers 

Connector J3 brings out the I 2 C signals from the C5515 processor. The signals are 

shown in the table below. 

Table 3: J3, I 2 C Probe Headers 

Pin # 

Signal Name 

1 I2C_SDA 

2 I2C_SCL 

3 GND 

Shown below is a top view of the J3 connector. 

J3 

GND 

SCL 

SDA 

1 

Figure 2-4, Top View of the J3 Connector 

2-7


2.2.4 J4, Headphone Connector 

Connector J4 is a headphone/speaker jack. It can drive standard headphones or a 

high impedance speaker directly. These outputs connect to HEADPHONE LOUT 

and HEADPHONE_ROUT of the TLV320AIC3204. The standard 3.5 mm jack is 

shown in the figure below. 

Ground 

Right Headphone 

Left Headphone 

Figure 2-5, Headphone Connector 

2.2.5 J5, HDR4 Connector 

The HDR4 connector brings out 4 signals from the TLV320AIC3204. These signals are 


Table 4: J5, HDR4 Connector 

Pin # 

Signal Name 

1 AIC_SCLK 

2 AIC_MISO 

3 AIC_SPI_SEL 

4 AIC_MOSI 


AIC_MOSI 

AIC_MISO 

J5 

AIC_SPI_SEL 

AIC_SCLK 

1 




2.2.6 J6, I 2 C Probe 

Connector J6 brings out the I 2 C signals from the C5515 processor. The signals are 


Table 5: J6, I 2 C Probe Headers 

Pin # 

Signal Name 

1 I2C_SDA 

2 I2C_SCL 

3 GND 


J6 

GND 

SCL 

1 

SDA 


2.2.7 J7, Stereo Out Connector 

The audio line out, J7, is a stereo output. These outputs connect to AIC3254_LOUT 

and AIC3254_ROUT of the TLV320AIC3204.The output connector is a 3.5 mm stereo 

jack. The signals on the mating plug are shown in the figure below. 

Ground 

Right Line Out 

Left Line Out 

Figure 2-8, Stereo Out Connector 

2-9


2.2.8 J8, External JTAG Header 

The TMS320C5515 EVM is supplied with a 14 pin header interface, J8. This is the 

standard interface used by JTAG emulators to interface to Texas Instruments 

processors. The pinout for the connector is shown in the figure below. 

TMS 

TDI 

Vcc 

TDO 

RTCK 

TCK 

EMU0 

1 2 

3 4 

5 6 

7 8 

9 10 

11 12 

13 14 

TRST- 

GND 

no pin (key) 

GND * 

GND 

GND 

EMU1 

Header Dimensions 

Pin-to-Pin spacing, 0.100 in. (X,Y) 

Pin width, 0.025-in. square post 

Pin length, 0.235-in. nominal 

* Embed/External EMU Select 

Figure 2-9, JTAG INTERFACE 

2.2.9 J9, Stereo In 1 Connector 

The J9 connector in is a stereo input. The input connector is a 3.5 mm stereo jack. 

These inputs connect to AIC_LINE2L and AIC_LINE2R of the TLV320AIC3204. The 

signals on the mating plug are shown in the figure below. 

Ground 

Right Line In 

Left Line In 

Figure 2-10, Stereo In 1 Jack 



2.2.10 J10, Daughter Card Interface 

The TMS320C5515 EVM has 3 daughter card interfaces, J10, J13, and J14. The 

Medical Development Kit (MDK) daughter cards from Texas Instruments use these 

interfaces. For more information about these cards refer to the following web sites: 

http://focus.ti.com/docs/toolsw/folders/print/tmdxmdkek1258.html 

http://focus.ti.com/docs/toolsw/folders/print/tmdxmdkds3254.html 

http://focus.ti.com/docs/toolsw/folders/print/tmdxmdkpo8328.html 

Connector J10 is a 2 x 5 double row male header (.1 in. centers) used to interface to 

plug on daughter cards. The signals on this connector are shown in the table below. 

Table 6: J10, Daughter Card Interface 

Pin # Signal Name Pin # Signal Name 

2 NC 1 NC 

4 NC 3 NC 

6 NC 5 GND 

8 NC 7 V1.8 

10 V5 9 V3.3 

2.2.11 J11, USB Type B Connector 

The J11 connector is a USB Type B connector. This connector interfaces directly to the 

C5515 processor. The signals on this connector are shown in the table below. 

Table 7: J11, USB Type B Connector 

Pin # USB Signal C5515 Signal, Pin 

1 VBUS USB VBUS, J12 

2 D- USB_DM, J14 

3 D+ USB_DP, H14 

4 GND 

5 GND 

5 GND 

2-11


2.2.12 J12, Stereo In 2 Connector 

The J12 connector in is a stereo input. The input connector is a 3.5 mm stereo jack. 

These inputs connect to AIC_LINE3L and AIC_LINE3R of the TLV320AIC3204. The 

signals on the mating plug are shown in the figure below. 

Ground 

Right Line In 

Left Line In 

Figure 2-11, Stereo In 2 Jack 






1 ADS_GPIO4 2 GPIO11 

3 SPI_CLK 4 GND 

5 GPIO6 / I2S1_CLK 6 ADS_GPIO10 

7 SPI_CS0 8 ADS_GPIO1 

9 GPIO7 / I2S1_FS 10 GND 

11 SPI_DX 12 ADS_GPIO0 

13 SPI_RX 14 GPIO9 / I2S1_RX 

15 INT1 16 I2C_SCL 

17 XF 18 GND 

19 GPIO8 / I2S1_DX 20 I2C_SDA 

21 ADS_GPIO3 22 ADS_GPIO2 








2 GPAIN0 1 No connect 




10 NC 9 GND 

12 NC 11 GND 

14 NC 13 GND 

16 NC 15 NC 

18 NC 17 GND 

20 NC 19 GND 

2-13


2.2.15 J15, MMC/SD Connector 

Connector J15 is used to provide a MMC/SD interface to the C5515 processor. The 

signals on this connector are shown in the table below. 

Table 10: J15, MMC/SD Connector 

Pin # 

Signal Name 

1 MMC0_DATA3 

2 MMC0_CMD 

3 GND 

4 VDD_IO1 

5 MMC0_CLK 

6 GND 

7 MMC0_DATA0 

8 MMC0_DATA1 

9 MMC0_DATA2 

10 WP 

11 COM / GND 

12 CARD_DETECT 

13 No Connect 

14 No Connect 

15 No Connect 

16 No Connect 

17 No Connect 

18 No Connect 



2.2.16 J16, +5 Volt In Connector 

Power (+5 volts) is brought onto the TMS320C5515 EVM via the J16 connector. The 

connector has an outside diameter of 5.5 mm. and an inside diameter of 2.5 mm. The 

diagram of J7 is shown below. 

J16 

+5V 

Ground 

PC Board 

Front View 

Figure 2-12, J16, TMS320C5515 EVM Power Connector 

2.2.17 J18, Battery Holder 

Connector J18 is a battery holder on the bottom side of the board. This battery holder 

will accommodate two (2) “AA” size batteries. The ground and positive voltage from the 

battery go to the voltage regulator U26, TPS61030-ADJ. Jumper JP39 is used to select 

the voltage input source (power jack or the battery holder). 

2-15


2.2.18 J19, Display Interface 

Connector J19 provides an interface to a display module. This connector is located on 

the bottom side of the board. The signals on this connector are shown in the table 

below. 

Table 11: J19, Display Interface 


1 GND 16 LCD_nWE / R/Wn 

2 V13 17 GND / BS0 

3 VCOMH 18 VDD_IO1 / BS1 

4 VDD_IO1 / VDDIO 19 LCD_BIAS_OE / CEn 

5 VSL 20 LCD_ALE / D/Cn 

6 NC 21 nRESET / RESETn 

7 LCD_DATA7 / D7 22 IREF 

8 LCD_DATA6 / D6 23 GPIO1 

9 LCD_DATA5 / D5 24 GPIO0 

10 LCD_DATA4 / D4 25 NC-25 

11 LCD_DATA3 / D3 26 VDD 

12 LCD_DATA2 / D2 27 VDD_IO1 / VCI 

13 LCD_DATA1 / D1 28 GND / VSS 

14 LCD_DATA0 / D0 29 NC-29 

15 LCD_RE / E/RDn 30 GND / NC-30 

2.2.19 M1, Left Microphone 

The M1 microphone (left channel) connects to the AIC_MIC1L input of the 

TLV320AIC3204. 

2.2.20 M2, Right Microphone 

The M2 microphone (right channel) connects to the AIC_MIC1R input of the 

TLV320AIC3204. 



2.2.21 Blue Tooth Board Interface Connectors 

Connectors P1 and P2 make up the Blue Tooth Board Interface. Both connectors are 

2 x 10 double row headers and are specifically spaced to interface directly to Texas 

Instruments Blue Tooth modules. 

2.2.21.1 P1, Blue Tooth Board Interface Connector 

Connector P1 is a 2 x 10 double row used to interface to plug on daughter cards. The 


Table 12: P1, Blue Tooth Board Interface 


1 GND 2 MMC1_DATA0 

3 UART_RTS 4 MMC1_DATA1 

5 RTC_CLKOUT 6 MMC1_DATA2 

7 UART_RX 8 MMC1_DATA3 

9 UART_TX 10 GPIO4 

11 I2C_SDA 12 GPIO5 

13 I2C_SCL 14 SPI_ALT_CS1 

15 MMC1_CLK 16 SPI_ALT_CLK 

17 MMC1_CMD 18 SPI_ALT_DX 

19 GND 20 SPI_ALT_RX 

2-17


2.2.21.2 P2, Blue Tooth Board Interface Connector 

Connector P2 is a 2 x 10 double row used to interface to plug on daughter cards. The 


Table 13: P2, Blue Tooth Board Interface 


1 NC 2 GND 

3 NC 4 NC 

5 NC 6 NC 

7 V3.3 8 I2S1_DX_CC 

9 V3.3 10 I2S1_RX_CC 

11 I2S1_FS_CC 12 NC 

13 GPIO12 14 NC 

15 GPIO14_CC 16 NC 

17 I2S1_CLK_CC 18 UART_CTS 

19 GPIO14_CC 20 GPIO13 

2.3 System LEDs 

TheTMS320C5515 EVM has three light emitting diodes (LEDs). These LEDs indicate 

various conditions on the EVM. These function of each LED is shown in the table 

below. 

Table 14: System LEDs 

Reference 

Designator 

Color 

Function 

Schematic 

Page 

D2 Green Connected to the XF bit on the C5515 processor 2 

D8 Red Indicates +5 volts is applied at the J7 connector 13 

DS1 Green Emulator busy N/A 



2.4 C5515 EVM Switches 

The C5515 EVM has 14 switches. A list of the switches is shown in the table below: 

Table 15: TMS320C5515 EVM Switches 

Switch 

Silkscreen 

Nomenclature/ 

Function 

Schematic 

Page 

Board 

Side 

SW1 RESET 14 Top 

SW2 WAKEUP 2 Top 

SW4 2 Position DIP 14 Top 

SW5 Power On/Off 13 Top 

SW6 MENU 18 Top 

SW7 UP 18 Top 

SW8 MODE 18 Top 

SW9 SHIFT 18 Top 

SW10 REWIND (RWD) 18 Top 

SW11 PLAY 18 Top 

SW12 FORWARD (FWD) 18 Top 

SW13 STOP 18 Top 

SW14 DOWN (DN) 18 Top 

SW15 REC 18 Top 

2.4.1 SW1, RESET Switch 

This switch asserts the nRESET signal to all major components on the C5515 EVM 

board. 

2.4.2 SW2, WAKEUP Switch 

“Wakeup” is an active high external input signal used to wake up the core from the 

power off state. It can be configured as an active low open drain output signal. A 

pull up / pull-down jumper (JP5) is provided to accommodate both active high and 

active low states. 

2-19


2.4.3 SW4, LDO Option DIP Switches 

SW4 is a 4 position DIP used to select LDO options. The table below shows the 

functions of the 4 positions. When switch is in the “ON” position a logic “0” is applied to 

the signal. When the switch is in the “OFF” position a logic “1” is applied to the signal. 

2 

1 

SW4 

VDD_IO1_SEL 

ON 

V_CORE_SEL 

Tied to DEFLDO2 on TPS65023 

Tied to DEFCDCD1 on TPS65023 

Figure 2-13, SW4 Switch 

Table 16: LDO Option DIP Switches 

Switch 

Position 

Signal 

State 

Signal 

Function 

Default 

Setting 

1 - ON * 

1 - OFF 

Low 

High 

V_CORE_SEL = 1.3V 

V_CORE_SEL = 1.05V 

For proper device operation, this 

switch must be in the ON position 

2 - ON * Low VDD_IO1_SEL = 3.3V For proper device operation, this 

2 - OFF High VDD_IO1_SEL = 1.8V 

switch must be in the ON position 

ON/Low 

ON/Low 

* default position 

2.4.4 SW5, Power On/Off Switch 

The On/Off switch provides +5 volts to the logic on the board. In the “OFF” position this 

switch interrupts the power from the power supply as well as the battery holder. 



2.4.5 SW6 - SW15, Function Switches 

Switches SW6-SW15 are push button momentary switches which are read by the 

processor. These switches can take on any function defined by user software. The silk 

screen nomenclature is provided for user convenience and are shown in the table 

below. 

Table 17: Function Switches 

Switch # 

SW6 

SW7 

SW8 

SW9 

SW10 

SW11 

SW12 

SW13 

SW14 

SW15 

Silk Screen Name 

MENU 

UP 

MODE 

SHIFT 

REWIND (RWD) 

PLAY 

FORWARD (FWD) 

STOP 

DOWN (DN) 

REC 

2-21


2.5 Jumpers 

The C5515 EVM has twenty-nine (29) jumpers locations. These jumpers can be 

divided into 3 classes; factory installed options, user options, and power domain probe 

points. The following sections describe the jumpers in these classes. The position of 

these jumpers on the top side of the EVM board are shown in the figures below. 

JP3 

JP38 

JP15 

JP11 

JP9 

JP37 

JP1 

JP4 

JP2 

JP5 

JP7 

JP8 

JP40 

JP17 

JP14 

JP12 

JP19 

JP20 

JP23 

JP25 

JP13 

JP18 

JP16 

JP6 

JP22 

JP21 

JP24 

JP39 

JP26 

Figure 2-14, TMS320C5515 EVM Jumpers (Top) 



2.5.1 C5515 EVM Option Jumpers 

The C5515 EVM’s option jumpers fall into two categories; user selectable, and factory 

installed. The table below shows lists the user option jumpers and their function. 

Table 18: C5515 EVM User Option Jumpers 

Jumper #/ 

Schematic 

Page 

Nomenclature 

# of 

Positions 

Setting 

Function 

JP2 / 12 nRESET Select 3 

JP3 / 17 UART_EN 2 

JP5 / 2 WK_PU_PD_SEL 3 

JP6 / 10 LDO_EN 2 

JP9 / 3 CLK_SEL 2 

JP12 / 10 MIC_BIAS 3 

JP39 / 13 VIN Select 3 

1 - 2 * Use RESET from TPS65023 

2 - 3 Use RESET from SW1 

Shorted * UART transceiver enabled 

Open UART transceiver disabled 

1 - 2 WAKEUP pin uses pull up 

2 - 3 * WAKEUP pin uses pull down 

Shorted * Enable internal DSP LDO 

Open 

Disable internal DSP LDO 

Shorted CLK_SEL tied to VDD_IO1 

Open * 

CLK_SEL tied to GND 

1 - 2 Use 3.3V 

2 - 3 * Use AIC output 

1 - 2 Power is from battery 

2 - 3 * Power is from external 5v supply 

* Factory default 

2-23


The factory installed jumpers are pre-configured with a zero (0) ohm resistor at the 

factory and are not meant to be changed by users. These jumpers are not populated 

with a jumper header. The table below lists the factory installed option jumpers and 

their function. 

Table 19: C5515 EVM Factory Installed Power Domain Configuration 

Jumper #/ 

Schematic 

Page 

Nomenclature 

# of 

Positions 

Setting 

Function 

JP1 / 11 CPU VDDC Select 3 

JP4 / 3 RTC 3 

JP11 / 10 LDOI Select 3 

JP15 / 11 USB_VDD_IN Select 3 

JP16 / 10 VDDA_ANA Select 3 

JP18 / 10 VDDA_PLL Select 3 

1 - 2 *+ Internal DSP-LDO used 

2 - 3 DSP will use external 1.3 volt 

1 - 2 * CVDDRTC tied to V1.3 

2 - 3 Do Not Use 

1 - 2 * LDO_IN tied to V1.8 

2 - 3 LDO_IN tied to V3.3 

1 - 2 *z DSP will use internal USB LDO 

2 - 3 DSP will use external 1.3V 

1 - 2 * Internal Analog-LDO used 


1 - 2 * Internal Analog-LDO used 


* Default 

+ JP6 must be installed 

Z USB LDO must be enabled in software 



2.5.1.1 JP2, nRESET Source Select 

Jumper JP2 is a three position jumper that allows the user to the select the source of 

the nRESET signal to the C5515 processor. This jumper is pre-configured at the 

factory with a jumper in the 2-3 position (*).The table below shows the positions and 


Table 20: JP2, nRESET Source Select 

Jumper 

Position 

Function 

1-2 * PWR_RSTn is the source of the nRESET signal to the C5515 Processor 

2-3 SW1 is the source of the nRESET signal to the C5515 Processor 

Shown below is a top view of the JP2. 

1 1 

JP2 

JP2 

1-2 Position 2-3 Position 

Figure 2-15, Top View of the Jumper JP2 

2.5.1.2 JP3, UART_EN Select 

Jumper JP3 is a two position populated jumper that enables/disables the UART driver 

on the EVM. This jumper is pre-configured at the factory with a jumper in place (*). The 

table below shows the positions and their function. 

Table 21: JP3, UART Enable Jumper 

Jumper 

Position 

Open 

Shorted * 

Function 

EN_L pulled to GND thereby disabling the MAX3222 line driver 

EN_L pulled to +3.3 thereby enabling the MAX3222 line driver 


JP22 

UART_EN 

JP22 

UART_EN 

Factory 

Configuration 

Open Shorted 


2-25


2.5.1.3 JP5, WAKEUP Source Select 

Jumper JP5 is a three position jumper that allows the user to the select the a pull up or 

pull down WAKEUP signal to the C5515 processor (U13-E8). This jumper is 

pre-configured at the factory with a jumper in the 2-3 position (*). The 1-2 position 

allows the switch, SW2, to wake up the processor. The table below shows the positions 

and their function. 

Table 22: JP5, WAKEUP Source Select 

Jumper 

Position 

Function 

1-2 Depressing switch SW2 wakes up the C5515 Processor (uses pull up) 

2-3 * WAKEUP pin uses Pull Down 


2.5.1.4 JP6, LDO_EN Source Select 

JP5 

1 

WK_PU_PD 

JP5 

1 

WK_PU_PD 



Jumper JP6 is a two position jumper located on the top side of the circuit board that 

selects the level of the LDO_EN signal. When the jumper is shorted, LDO_EN is pulled 

to GND enabling on-chip LDO’s. If the jumper is open, LDO_EN is pulled high disabling 

on-chip LDO’s. This jumper must be installed. The table below shows the positions and 


Table 23: JP6, LDO_EN Select 

Jumper 

Position 

Open 

Shorted * 

Function 

LDO_EN, is pulled high, LDO’s enabled 

LDO_EN is low, the internal LDO is enabled 

* Default 


Open 

JP6 

JP6 

Shorted 

1 1 




2.5.1.5 JP9, CLK_SEL Source Select 

Jumper JP9 is a two position jumper that determines if the DSP uses an external or 

internal oscillator. The shorted state allows an external oscillator to be used when an 

oscillator is populated in the 8 pin OSC1 socket. An open jumper means the DSP will 

use an internal oscillator. The jumper is pre-configured at the factory in the open state. 

The table below shows the positions and their function. 

Table 24: JP9, CLK_SEL Select 

Jumper 

Position 

Open * 

Shorted 

Function 

Use internal oscillator for DSP clock 

Use external oscillator for DSP clock 

* Default 


Factory 

Configuration 

JP9 CLK_SEL 

1 

JP9 CLK_SEL 

1 

Open Shorted 


2.5.1.6 JP12, MIC_BIAS Source Select 

Jumper JP12 is a three position populated jumper that selects the source of the 

microphone bias used for AIC MIC1L and AIC MIC1R on the TLV320AIC3204. The 

table below shows the positions and their function. 

Table 25: JP12, Microphone Bias Select 

Jumper 

Position 

Function 

1-2 When R209 is installed bias is 3.3 volts 

2-3 * Bias from TLV320AIC3204 MICBIAS pin 

* Default 


1 

1 

JP12 

MIC_BIAS 

JP12 

MIC_BIAS 



2-27


2.5.1.7 JP39, VIN Source Select 

Jumper JP39 is a three position populated jumper located on the top side of the circuit 

board that selects the source of the incoming +5 volts. The table below shows the 

positions and their function. 

Table 26: JP39, VIN Source Select 

Jumper 

Position 

Function 

1 - 2 Battery is selected as source for +5 volts input 

2 - 3 * External power supply is selected as source for +5 volts input, J16 

* default 

Shown below is a top view of the JP39 with silkscreen markings. 

JP39 

VIN_SEL 

EXT 

BAT 

1-2 BAT 

2-3 5V 

JP39 

VIN_SEL 

EXT 

BAT 

1-2 BAT 

2-3 5V 

Factory 

Setting 





2.5.2 C5515 EVM Power Domain Probe Points 

The C5515 EVM has pre-designed probe points in the circuitry which could be used to 

observe power domains. Several of the power domains have INA219 power monitors 

and these domains have a 1 ohm resistor shunted on the EVM. The probe points with 

power monitors are shown in the table below. 

Table 27: C5515 EVM Power Probe Points With Power Monitors 

Jumper #/ 

Schematic 

Page 

Signal 

# of Positions 

1 Ohm Shunt 

Resistor 

Installed at 

factory 

JP8 / 11 TPS65023_VCC_1V8 2 Monitor 

JP17 / 11 C5515 VDD_IO1 2 Monitor 

JP20 / 15 V1.8 2 Monitor 

JP22 / 13 VIN_EVM 2 Monitor 

JP23 / 15 VDD_IO2 2 Monitor - 0 

JP25 / 15 V3.3 2 Monitor 

JP37 / 11 VDDC 2 Monitor 

JP38 / 11 USB_VDD_IN 2 Monitor 

Shown below is a diagram of a typical Power Domain Probe Point with a one (1) ohm 

resistor. 

One (1) ohm 

resistor 

Figure 2-22, Diagram of a typical jumper 

2-29


The remaining pre-configured power probe points are shunted with zero (0) ohm 

resistors as shown below. 

Table 28: C5515 EVM Power Probe Points With 0 Ohm Resistors 

Jumper #/ 

Schematic 

Page 

Signal 

# of Positions 

0 Ohm Shunt 

Resistor 

Installed at 

factory 

JP7 / 19 AIC HPVDD 2 Yes 

JP13 / 2 C5515 VDDIO4 2 Yes 

JP14 / 19 AIC IOVDD 2 Yes 

JP19 / 10 USB_VDDA3P3 2 Yes 

JP21 / 15 V1.3 2 Yes 

JP24 / 15 VDD_IO1 2 Yes 

JP26 / 15 CPU_VCC_CORE 2 Yes 

JP40 / 19 AIC AVDD 2 Yes 

Shown below is a diagram of a typical Power Domain Probe Point with a zero (0) ohm 

resistor. 

Zero (0) ohm 

resistor 

Figure 2-23, Diagram of a typical jumper 



2.6 Test Points 

The C5515 EVM has forty-one (41) test points. The position of these test points 

on the top side of the C5515 EVM are shown in the figures below. 

TP1 

TP21 

TP17 

TP4 

TP2 

TP3 

TP5 

TP6 

TP10 

TP11 

TP7 

TP9 

TP14 

TP15 

TP16 

TP19 

TP22 

TP20 

TP25 

TP26 

TP27 

TP8 

TP12 

TP18 

TP24 

TP23 

TP28 

TP29 

TP30 

TP31 

TP32 

TP33 

TP34 

Figure 2-24, TMS320C5515 EVM Test Points (Top) 

2-31


Figure below shows the location of test points on the bottom side of the C5515 EVM. 

TP41 TP40 

TP39 

TP38 

TP36 

TP35 

TP37 

Figure 2-25, TMS320C5515 EVM Test Points (Bottom) 


The table below shows the signals present on each user test point. 

Table 29: C5515 EVM User Test Points 

Test 

Point # 

Signal 

Schematic 

Page # 

TP1 GND 11 

TP2 nRESET 12 

TP3 WAKUP 2 

TP4 XF 2 

TP5 AIC_GPIO 19 

TP6 INT1 2 

TP7 INT0 2 

TP8 RTC_CLKOUT 2 

TP9 CLKOUT 3 

TP12 GND 15 

TP13 USB_3.3V 27 

TP14 GPIO5 18 

TP15 GND 19 

TP16 VBUS 3 

TP17 TPS65023_VCC_3V3 15 

TP18 V_PWR_MON 15 

TP19 MMC0.WP 16 

TP20 INTn 14 

TP21 LOWBATn 14 

TP22 MMC0.INS 16 

TP23 VPWR_IN 13 

TP24 GND 17 

TP25 PWRFAILn 14 

TP26 PWRFAIL_SNS 14 

TP27 LOWBAT_SNS 14 

TP28 VBATOUT 13 

TP29 GND 18 

TP30 GND 13 

TP31 +5V Input 13 

TP32 Battery + 13 

TP33 Battery - 13 

TP34 GND 3 


2-33


The table below shows the signals present on each test point used exclusively by the 

factory. 

Table 30: C5515 EVM Factory Test Points 

Test 

Point # 

Signal 

Schematic 

Page # 

TP10 USB_1.6V 27 

TP11 USB_3.3V 27 

TP35 GPIO_1 24 

TP36 GPIO_0 24 

TP37 CLKOUT 23 

TP38 ODEMU1n 24 

TP39 ODEMU0n 24 

TP40 TCKR 24 

TP41 USB_2.5V 27 


Appendix A 

Schematics 

This appendix contains the schematics for the TMS320C5515 EVM. 

Board components with designators over 200 (e.g. DS210, R211) are 

part of Spectrum Digital’s embedded JTAG emulator and are not 

included in these schematics. 

A-1

1 

2 

4 

5 

5 

6 

7 

8 

9 

A 

A 

4 

4 

3 

3 

A 

2 

2 

1 

1 


REV DESCRIPTION 

DATE APPROVED 

10/15/2009 RRP 

Initial schematic for layout 

B Update TPS65023 Enable Logic 12/15/2009 RRP 

NOTES, UNLESS OTHERWISE SPECIFIED: 

1. RESISTANCE VALUES IN OHMS. 

2. CAPACTITANCE VALUES IN MICROFARADS. 

3. REFERENCE DESIGNATORS USED: 

4. ALL 0.1 uF AND 0.01uF CAPACITORS ARE DECOUPLING CAPS UNLESS 

OTHERWISE NOTED. THEY ARE SHOWN ON THE PAGE WITH THE INTEGRATED 

D CIRCUITS THEY SHOULD BE PLACED NEAR. 

D 

Schematic Contents 

C C 

01 - TITLE PAGE 

02 - TMS320C5515 GPIO / MMC / SPI / I2C 

03 - TMS320C5515 CLOCKS / JTAG / USB 

04 - EMULATION - JTAG 

05 - CC Board Interface 

06 - TMS320C5515 EMIF 

07 - Mobile DRAM Interface 

08 - NAND Flash Interface 

09 - NOR Flash Interface 

10 - TMS320C5515 Power 

11 - CPU Decoupling Caps 

12 - RESET 

13 - Power Input 

14 - TPS65023 Power Management 

15 - POWER Router 

16- MMC / SD 

17 - UART / EEPROMs 

18 - SAR Resistor Network 

19 - CODEC 

20 - COLOR LCD INTERFACE 

A-2 TMS320C5515 EVM Technical Reference 

B B 

REVISION STATUS OF SHEETS 

REV 

DWN 

DATE 

SHEET 

R.R.P. 10/15/2009 

A CHK 

DATE 

SPECTRUM DIGITAL INCORPORATED 

A 

REV 

T.W.K. 10/15/2009 

ENGR 

DATE 

SHEET 

R.R.P. 10/15/2009 

Title: 

TMS320C5515 EVALUATION MODULE 

ENGR-MGR 

DATE 

REV A B A B A A A A A 

R.R.P. 10/15/2009 

Page Contents: TITLE SHEET 

QA 

DATE 

SHEET 11 12 13 14 15 16 17 18 19 20 

C.M.D. 10/15/2009 

Revision: 

MFG 

DATE 

Size: B 

DWG NO 512702-0001 

B 

REV B A A A A A A A A 

NEXT ASSY 

USED ON 

R.R.P. 10/15/2009 

RLSE 

DATE 

Date: Monday, February 01, 2010 Sheet 1 o f 20 

SHEET 

3 5 

10 APPLICATION 

R.R.P. 10/15/2009

1 

2 

3 

4 

5 

5 

1 

2 

3 

4 

5 


VDD_IO1 

GPAIN3 

GP[0] R43 0 

18 GPAIN3 

ADS_GPIO0 18 

JP13 NO-POP 

GPAIN2 

U13A 

GP[1] R34 0 

VDDIO4 

18 GPAIN2 

ADS_GPIO1 18 

2 1 

GPAIN1 

GP[2] R31 0 

18 GPAIN1 

ADS_GPIO2 18 

GPAIN0 

GP[3] R28 0 

PWR JP 

18 GPAIN0 

ADS_GPIO3 18 

R193 0 

R204 0 

GPIO4 5 

GP[0] 

MMC0_CLK 16 

C50 

MMC0_CLK/I2S0_CLK/GP[0] 

L10 

GP[1] 

GP[4] R47 0 

MMC0_CMD 16 

ADS_GPIO4 18 

1uF C135 

MMC0_CMD/I2S0_FS/GP[1] 

M11 

GP[2] 

MMC0_DATA0 16 

0.1uF 

MMC0_D0/I2S0_DX/GP[2] 

L9 

GP[3] 

GP[5] R51 0 

MMC0_D1/I2S0_RX/GP[3] 

M10 

MMC0_DATA1 16 

ADS_GPIO5 18 

C11 

GP[4] 

D GPAIN3 ADC 

MMC0_D2/GP[4] 

L12 

MMC0_DATA2 16 

GP[5] 

D 

R120 

B11 

DVDDIO 

MMC0_D3/GP[5] 

L11 

R215 0 

MMC0_DATA3 16 

GPIO5 5 

JP5 

GPAIN2 

A11 

10K 

GPAIN1 

D10 

GPAIN0 

SW2 

GP[6] 

GP[6] R196 0 

1 

VDDA_ANA 

MMC1_CLK/I2S1_CLK/GP[6] 

M13 

MMC1_CLK 5 

I2S1_CLK 18 

GP[7] 

R287 0 

2 

1 3 

MMC1_CMD/I2S1_FS/GP[7] 

L14 

MMC1_CMD 5 

MMC0.WP 16 

GP[8] 

GP[7] R46 0 

3 

2 4 

MMC1_DATA0 5 

I2S1_FS 18 

C93 

MMC1_D0/I2S1_DX/GP[8] 

M14 

Wakeup 

GP[9] 

R288 0 

MMC1_DATA1 5 

MMC0.INS 16 

0.1uF 

MMC1_D1/I2S1_RX/GP[9] 

M12 

WAKEUP_PU-PD_SEL R112 

GP[10] 

GP[8] R202 0 

MMC1_D2/GP[10] 

K14 

MMC1_DATA2 5 

I2S1_DX 18 

GP[11] 

GP[9] 

TP3 

F8 

DVDDIO 

MMC1_DATA3 5 

I2S1_RX 18 

TP8 

MMC1_D3/GP[1]1 

L13 

R191 0 

10K 

DVDDRTC 

WAKEUP 

RTC_CLKOUT RTC_CLKOUT D8 

GP[6] R39 0 

RTC_CLKOUT 

I2S1_CLK_CC 5 

LCD_DATA0 

GP[7] R205 0 

RTC_CLKOUT 

LCD_D[0]/SPI_RX P6 

LCD_DATA0 20 

I2S1_FS_CC 5 

LCD_DATA1 

GP[8] 

LCD_DATA1 20 

I2S1_DX_CC 5 

WAKEUP 

LCD_D[1]/SPI_TX N6 

R42 0 

E8 

LCD_DATA2 

GP[9] 

LCD_D[2]/GP[12] 

P7 

R36 0 

WAKEUP 

LCD_DATA2 20 

I2S1_RX_CC 5 

LCD_DATA3 

LCD_D[3]/GP[13] 

N7 

LCD_DATA3 20 

LCD_DATA4 

LCD_D[4]/GP[14] 

N8 

LCD_DATA4 20 

DVDDRTC 

LCD_DATA5 

LCD_D[5]/GP[I5] 

P9 

LCD_DATA5 20 

LCD_DATA6 

R208 0 AIC_RST 

TP7 TP6 

LCD_DATA6 20 

AIC_RST 19 

VDD_IO1 

LCD_D[6]/GP[16] 

N9 

LCD_DATA7 

LCD_D[7]/GP[17] 

P10 

INT0 INT1 

LCD_DATA7 20 

GP[10] R50 0 ADS_GPIO10 

ADS_GPIO10 18 

R20 100K 

R14 100K 

GP[11] R37 0 GPIO11 

GPIO11 18 

LCD_DATA8 

LCD_D[8]/I2S2_CLK/GP[18]/SPI_CLK N10 

LCD_DATA8 19 

LCD_DATA9 

C 18 INT1 

E7 

INT1n 

LCD_D[9]/I2S2_FS/GP[19]/ SPI_CS0 

P11 

LCD_DATA9 19 

C 

LCD_DATA10 

13 INT0 

C6 

INT0n 

LCD_D[10]/I2S2_RX/GP[20]/SPI_RX N11 

LCD_DATA10 19 

LCD_DATA11 

GPIO11_LCD_PWR 

12,19,20 nRESET 

D6 

RESETn 

LCD_D[11]/I2S2_DX/GP[27]/SPI_TX P12 

R195 0 

LCD_DATA11 19 

GPIO11_LCD_PWR 20 

M8 

LCD_DATA12 

XF 

LCD_D[12]/UART_RTS/GP[28]/I2S3_CLK 

DVDDIO 

N12 

LCD_DATA13 

LCD_D[13]/UART_CTS/GP[29]/I2S3_FS P13 

LCD_DATA14 

LCD_RE 

LCD_D[14]/UART_RX/GP[30]/I2S3_RX N13 

R13 0 

SPI_ALT_CLK 5 

R124 1K D2 

LCD_DATA15 

TP4 

XF 

LCD_D[15]/UART_DX/GP[31]/I2S3_DX P14 

C13 

LCD_MCLK R12 0 

XF 

RSV5_(GND) 

SPI_ALT_CS1 5 

C14 

LCD_RE 

RSV4_(GND) 

LCD_EN_RDB/SPI0_CLK N3 

LCD_RE 20 

LCD_BIAS_OE 

LCD_DATA0 

LCD_CS0_E0/SPI_CS0 

P4 

R16 0 

LCD_BIAS_OE 20 

SPI_ALT_RX 5 

LCD_MCLK 

18 XF 

LCD_CS1_E1/SPI_CS1 

N4 

LCD_nWE 

LCD_DATA1 

LCD_RW_WRB/SPI_CS2 

P5 

R18 0 

LCD_nWE 20 

SPI_ALT_DX 5 

I2C 

LCD_ALE 

LCD_ALE 20 

VDD_IO1 

LCD_RS/SPI_CS3 

N5 

B8 

LCD_DATA2 R22 0 GPIO12 

SDA 

GPIO12 5 

B7 

SCL 

DVDDIO 

DVDDIO 

LCD_DATA3 R25 0 GPIO13 

GPIO13 5 

R19 R26 

LCD_DATA4 R289 0 GPIO14_CC 

GPIO14_CC 5 

10K 10K 

TMS320C5515 

LCD_DATA8 

I2S2_CLK 19 

LCD_DATA9 

I2S2_FS 19 

LCD_DATA10 

I2S2_RX 19 

B LCD_DATA11 

I2S2_DX 19 B 

I2C_SDA 

I2C_SCL 

LCD_DATA8 R24 0 SPI_CLK 

SPI_CLK 17,18 

LCD_DATA9 R29 0 SPI_CS0 

SPI_CS0 17,18 

LCD_DATA10 R27 0 SPI_RX 

SPI_RX 17,18 

J6 

LCD_DATA11 R32 0 SPI_DX 

5,14,15,17,18,19 I2C_SDA 

1 

SPI_DX 17,18 

5,14,15,17,18,19 I2C_SCL 

2 I2C Probe Point Headers 

LCD_DATA12 R30 0 UART_RTS 

3 

UART_RTS 5,17 

HEADER 3 

LCD_DATA13 R35 0 UART_CTS 

UART_CTS 5,17 

LCD_DATA14 R33 0 UART_RX 

UART_RX 5,17 

LCD_DATA15 R40 0 UART_TX 

UART_TX 5,17 

A SPECTRUM DIGITAL INCORPORATED 

A 

Title: 


Page Contents: 

GPIO,MMC-SD,SPI,I2C,I2S 

Revision: 

Size: B 

DWG NO 512702-0001 

A 

Date: 

Sheet o f Monday, February 01, 2010 2 20 

A-3

1 

2 

3 

4 

5 

1 

2 

3 

4 

5 


CPU_3V3_USB 

FB6 

1 2 

BLM21PG221SN1D 

AGND 

TP16 

U13D 

VBUS 

D D 

USB_VBUS J12 

USB_DM J14 

USB_DP H14 

USB_R1 

USB_R1 

G9 

JP4 

TP9 

R117 

NC-CLKOUT 

A7 

Place as 

V3.3 

CLKOUT 

CLKOUT 

close as 

CLKIN 

1 

A8 

R116 0 

possible 

JP9 POP 

CLKIN 

2 

to Y2 

R189 

VDD_IO1 

3 

2 1 

C7 

VDDC 

CLK_SEL 

C99 

C R113 NO-POP 

C 

CLK_SEL 

DVDDIO 

1uF 

OSC_V 

R157 

NO-POP 

R55 

R217 

10K 

NO-POP NO-POP 

CVDDRTC C8 

M9 

C161 

TRSTN 

R210 

C162 0.01uF 

L8 

R179 

C31 33pF 

1uF 

OSC1 

47K 

TMS 

RTCXO A9 

8 

VCC_8 OE_8 

1 

L7 

TDI 

7 

NC-7 NC-2 

2 

3 

6 

32.768KHz 

NC-6 NC-3 

3 

M7 

2 

R199 33 

5 

Y1 

OUT GND 4 

TDO 

M6 

Oscillator Socket 

R23 

TCK 

C39 33pF 

RTCXI 

B9 

L6 

EMU0 

V3.3 

B R174 

B 

R168 

VDD_IO1 

GND 

U11 

100 

10K 

1 

PLACE CLOSE TO TCK PIN 

VCCA VCCB 6 

5 

C130 

DIR 

3 

A 

B 4 

2 

15pF 

GND 

DIR=H : A to B 

DIR=L : B to A 

TARGET_EMU1 4 

TARGET_EMU0 4 

TARGET_TCK 4 

TARGET_TDO 4 

TARGET_TDI 4 

TARGET_TMS 4 

TARGET_TRSTn 4 


A 

Title: 


0 

AUDIO_MCLK 19 


CLOCK,JTAG,USB 

Revision: 

Size: B 

DWG NO 512702-0001 

A 

Date: 

Sheet o f Wednesday, February 03, 2010 3 20 

0 

0 

0 

C57 

C152 

USBVDD_OSC 

USB_VSSREF 

G10 

R207 

M5 

10K 

EMU1 

R54 

0 

1 4 

VSS_RTC C9 

DVDDIO CVDDRTC 


0 

C169 

0 

10uF 

0.1uF 

1000pF 

C47 

R56 

33pF 

Y2 

12.000MHz 

C48 

R57 

33pF 

G12 

USB_XI 

USBVDD_OSC 

R49 

G13 

NO-POP 

USB_MXI 

USB_XO 

G14 

USB_MXO 

F11 

USB_VSSOSC 

USB_VBUS 

J11 

S1 

6 

1 

USB_DM 

VBUS 

2 

USB_DP 

D- 

3 

D+ 

4 

GND 

S2 

5 

D3 

C58 C177 R236 USB-B connector 

R201 6.2V 

10uF 0.1uF 

100K 

V1.3 

10K 1% 

TP34 

SN74AVC1T45 

A-4 TMS320C5515 EVM Technical Reference

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


VDD_IO1 

VDD_IO1 

R176 

R185 

R200 

NO-POP NO-POP 1K 

R48 

R175 10K 

TARGET_TRSTn 

USBSEL - HIGH, SELECT EMBEDDED EMULATION 

TARGET_TRSTn 3 

J8 

10K 

2 

TARGET_TMS 

D D 

USBSEL - LOW, SELECT EXTERNAL XDS EMULATION 

nTRST TMS 1 

TARGET_TDI 

TARGET_TMS 3 

4 

4 TDI 

3 

TARGET_TDI 3 

6 

6 Key Vcc 

5 

8 

TARGET_TDO 

8 TDO 7 

TARGET_TDO 3 

10 

TARGET_TCK 

10 RTCK 9 

TARGET_TCK 3 

C45 

12 

R211 

12 TCK 11 

14 

TARGET_EMU0 

100nF 

EMU1 EMU0 

13 

TARGET_EMU0 3 

R220 

JTAG 

R222 

3V3_EMU 

100K 

100K 

R216 

REMOVE IF USING BOARD ON QUICKTURN 

TARGET_EMU1 

TARGET_EMU1 3 

10K 

VDD_IO1 

EMBED_EMU_SELn 3V3_EMU 

C174 

Q3 

0.1 uF 

G 

BSS138 

U22 

C175 

1 

VCCA VCCB 16 

0.1 uF 

D 

C C 

4 

R232 33 

1A1 

1B1 

13 

5 

R230 33 

1A2 

1B2 

12 

S 

6 

2B1 

11 R228 33 

2A1 

7 

R225 33 

2A2 

2B2 

10 

3V3_EMU 

R233 10K 

2 

1DIR 

15 

DIR AND OEn ARE ON A POWER DOMAIN 

1OEn 

EMBED_EMU_XRSp 12 

3 

EMBED_EMU_SELn 

2DIR GND.1 

8 

14 

OEn DIR FUNCTION 

2OEn GND.2 

9 

L L B->A 

L H BA 

L H B

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


NOTE: DIMENSIONS AND LOCATIONS OF THESE CONNECTORS MUST MEET SPECIFICATION FOR INTERFACE MODULES 

D D 

P1 

P2 

1 

2 

1 

2 

MMC1_DATA0 2 

3 

4 

2,17 UART_RTS 

3 

4 

MMC1_DATA1 2 

5 

6 

RTC_CLKOUT 

5 

6 

MMC1_DATA2 2 

V3.3 

7 

8 

I2S1_DX_CC 2 

2,17 UART_RX 

7 

8 

MMC1_DATA3 2 9 

10 

I2S1_RX_CC 2 

GPIO4 

C 2,17 UART_TX 

9 

10 

GPIO4 2 

I2S1_FS_CC 

11 

12 

C 

GPIO5 

2,14,15,17,18,19 I2C_SDA 

11 

12 

GPIO5 2 

GPIO12 

13 

14 

2,14,15,17,18,19 I2C_SCL 

13 

14 

SPI_ALT_CS1 2 

GPIO14_CC 

15 

16 

MMC1_CLK 

15 

16 

SPI_ALT_CLK 2 

I2S1_CLK_CC 

17 

18 

UART_CTS 2,17 

MMC1_CMD 

17 

18 

SPI_ALT_DX 2 

19 

20 

GPIO13 2 

19 

20 

SPI_ALT_RX 2 

HEADER 10X2 

HEADER 10X2 

B B 


A 

Title: 



CC BOARD INTERFACE 

Revision: 

Size: B 

DWG NO 512702-0001 

A 

Date: 


2 

2 

2 

2 

2 

2 

2 


1 

2 

3 

4 

5 

1 

2 

3 

4 

5 


D RN5 RPACK8-22 

U13C 

D 

7,9 

7,8,9 

8,9 

7,9 

RN7 RPACK8-22 

CPU_A5 D1 

CPU_SDRAS R151 0 

SDRAS 

A2 

CPU_A2 

CPU_A4 

EM_A[5] 

SDRASn 

A6 

CPU_SDCAS 

SDCAS 

SDRAS 7 

C 7,9 A2 

8 9 

C1 

R152 22 

C 

A5 

CPU_A5 

CPU_A3 

EM_A[4] 

SDCASn 

B4 

SDCAS 7 

7,9 A5 

7 10 

D2 

A3 

CPU_A3 

CPU_A2 

EM_A[3] 

7,9 A3 

6 11 

E1 

CPU_SDCLK R159 22 SDCLK 

A4 

CPU_A4 

CPU_A1 

EM_A[2] 

EM_SDCLK M3 

SDCLK 7 

7,9 A4 

5 12 

C2 

7,9 A0 

A0 

CPU_A0 

CPU_A0 

EM_A[1] 

4 13 

B2 

CPU_SDCKE 

SDCKE 

A1 

CPU_A1 

CPU_BA1 

EM_A[0] 

SDCKE N2 

R158 22 

SDCKE 7 

7,9 A1 

3 14 

B1 

7,9 BA0 

BA0 

2 15 

CPU_BA0 

CPU_BA0 

EM_BA[1] 

A1 

CPU_SDCE0 R150 22 SD_CEXn 

BA1 

CPU_BA1 

EM_BA[0] 

SD_CE0n 

B3 

SD_CEXn 7 

7,9 BA1 

1 16 

R283 NO-POP 

SD_CE1n 

A4 

CPU_EM_CS2n R153 22 EM_CS2n 

EM_CS2n 

C5 

CPU_EM_CS3n 

EM_CS2n 9 

R17 R15 

EM_CS3n 

M4 

CPU_EM_CS4n R154 22 EM_CS4n 

10K 10K 

EM_CS4n 

C3 

CPU_EM_CS5n 

EM_CS4n 8 

DVDDEMIF EM_CS5n 

A3 

B B 


A 

9 

9 

9 

9 

9 

9 

9 

9 

8 

8 9 

D15 

A15 

CPU_A15 

CPU_A20 

EM_D[15] 

J4 

D15 7,9 

A15 

7 10 

J3 

D14 

A14 

CPU_A14 

CPU_A19 

EM_A[20]/GP[26] 

EM_D[14] 

K3 

D14 7,9 

A14 

6 11 

G4 

D13 

A10 

CPU_A10 

CPU_A18 

EM_A[19]/GP[25] 

EM_D[13] 

K4 

D13 7,9 

A10 

5 12 

G2 

D12 

D12 7,9 

A13 

CPU_A13 

CPU_A17 

EM_A[18]/GP[24] 

EM_D[12] 

L3 

A13 

4 13 

F2 

D11 

D11 7,9 

A11 

A11 

CPU_A11 

CPU_A16 

EM_A[17]/GP[23] 

EM_D[11] 

C4 

3 14 

E2 

D10 

D10 7,9 

A12 

A12 

CPU_A12 

CPU_A15 

EM_A[16]/GP[22] 

EM_D[10] 

D3 

2 15 

N1 

D9 

D9 7,9 

A9 

A9 

CPU_A9 

CPU_A14 

EM_A[15]/GP[21] 

EM_D[9] 

F4 

1 16 

M1 

D8 

EM_A[14] 

EM_D[8] 

E3 

D8 7,9 

7,9 

9 

7,9 

7,9 

RN6 RPACK8-22 

A8 

A8 

8 9 

CPU_A8 

CPU_A13 L1 

D7 

A20 

CPU_A20 

CPU_A12 

EM_A[13] 

EM_D[7] 

H3 

D7 7,8,9 

A20 

7 10 

K1 

D6 

A7 

CPU_A7 

CPU_A11 

EM_A[12]/(CLE) 

EM_D[6] 

K5 

D6 7,8,9 

A7 

6 11 

K2 

D5 

A19 

CPU_A19 

CPU_A10 

EM_A[11]/(ALE) 

EM_D[5] 

M2 

D5 7,8,9 

A19 

5 12 

L2 

D4 

D4 7,8,9 

A18 

A18 

CPU_A18 

CPU_A9 

EM_A[10] 

EM_D[4] 

L4 

4 13 

J2 

D3 

D3 7,8,9 

A17 

A17 

3 

CPU_A17 

CPU_A8 

EM_A[9] 

EM_D[3] 

D4 

14 

J1 

D2 

D2 7,8,9 

A6 

A6 

2 15 

CPU_A6 

CPU_A7 

EM_A[8] 

EM_D[2] 

F3 

H2 

D1 

D1 7,8,9 

A16 

A16 

1 16 

CPU_A16 

CPU_A6 

EM_A[7] 

EM_D[1] 

E5 

F1 

D0 

EM_A[6] 

EM_D[0] 

G3 

D0 7,8,9 

CPU_DQM1 R119 22 DQM1 

DQM1 7 

EM_DQM1 

P1 

CPU_DQM0 R118 22 DQM0 

EM_DQM0 

B5 

DQM0 7 

CPU_RnW 

EM_WAIT2 

EM_R/Wn 

B6 

EM_WAIT2 

D5 

EM_WAIT3 

EM_WAIT2 

K6 

CPU_WE 

R156 22 WE 

EM_WAIT4 

EM_WAIT3 

EM_WEn 

H1 

WE 7,8,9 

EM_WAIT4 

G1 

EM_WAIT5 

EM_WAIT4 

H4 

CPU_OE 

OE 

EM_WAIT5 

EM_OEn 

E4 

R155 22 

OE 8,9 


Title: 



TMS320C5515 EMIF 

Revision: 

Size: B 

DWG NO 512702-0001 

A 

Date: 


A-7

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


D U4 

D 

RN2 RPACK8-10 

6,9 A0 

A0 

H7 

SDRAM_D0 

SDRAM_D0 

D0 

A1 

A0 

DQ0 

A8 

1 16 

D0 6,8,9 

6,9 A1 

H8 

SDRAM_D1 

SDRAM_D1 

D1 

A2 

A1 

DQ1 

B9 

2 15 

D1 6,8,9 

6,9 A2 

J8 

SDRAM_D2 

SDRAM_D2 

D2 

A3 

A2 

DQ2 

B8 

3 14 

D2 6,8,9 

6,9 A3 

J7 

SDRAM_D3 

SDRAM_D3 

D3 

A4 

A3 

DQ3 

C9 

4 13 

D3 6,8,9 

6,9 A4 

J3 

SDRAM_D4 

SDRAM_D4 

D4 

A5 

A4 

DQ4 

C8 

5 12 

D4 6,8,9 

6,9 A5 

J2 

SDRAM_D5 

SDRAM_D5 

D5 

A6 

A5 

DQ5 

D9 

6 11 

D5 6,8,9 

6,9 A6 

H3 

SDRAM_D6 

SDRAM_D6 

D6 

A7 

A6 

DQ6 

D8 

7 10 

D6 6,8,9 

6,9 A7 

H2 

SDRAM_D7 

SDRAM_D7 

D7 

6,9 A8 

A8 

A7 

DQ7 

E9 

8 9 

D7 6,8,9 

H1 

6,9 A9 

A9 

A8 

G3 

RN1 RPACK8-10 

6,9 A10 

A10 

A9 

H9 

SDRAM_D8 

SDRAM_D8 

D8 

D8 6,9 

6,8,9 A11 

A11 

A10 

DQ8 

E1 

1 16 

G2 

SDRAM_D9 

SDRAM_D9 2 

D9 

A11 

DQ9 

D2 

15 

D9 6,9 

SDRAM_D10 

SDRAM_D10 3 14 D10 

D10 6,9 

6,9 BA0 

BA0 

DQ10 

D1 

G7 

SDRAM_D11 

SDRAM_D11 4 13 D11 

D11 6,9 

6,9 BA1 

BA1 

BA0 

DQ11 

C2 

G8 

SDRAM_D12 

SDRAM_D12 5 12 D12 

BA1 

DQ12 

C1 

D12 6,9 

SDRAM_D13 

SDRAM_D13 6 11 D13 

D13 6,9 

SDCLK 

DQ13 

B2 

SDRAM_D14 

SDRAM_D14 

D14 

SDCLK 

F2 

CLK 

DQ14 

B1 

7 10 

D14 6,9 

SDRAM_D15 

SDRAM_D15 8 9 D15 

D15 6,9 

SDCAS 

DQ15 

A2 

SDCAS 

F7 

SDCKE 

CAS 

SDCKE 

F3 

DQM1 

CKE 

DQM1 

F1 

DQM0 

DQMH 

C DQM0 

E8 

C 

SDRAS 

DQML 

SDRAS 

F8 

WE 

RAS 

VDD_IO2 

6,8,9 WE 

F9 

SD_CEXn 

WE 

SD_CEXn 

G9 

CS 

NC1 

E2 

A9 

VCC1 

NC2 

G1 

E7 

+C87 

VCC2 

C90 C89 C98 C94 C88 C101 C97 

J9 

4.7uF 

VCC3 

A7 

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 

VCCQ1 

B3 

VCCQ2 

C7 

VCCQ3 

D3 

VCCQ4 

A3 

VSSQ1 VSS1 

A1 

B7 

VSSQ2 VSS2 

E3 

C3 

VSSQ3 VSS3 

J1 

D7 

VSSQ4 

MT48H4M16LF 

B B 


A 

Title: 



MOBILE SDRAM 

Revision: 

Size: B 

DWG NO 512702-0001 

A 

Date: 


6 

6 

6 

6 

6 

6 

6 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


D D 

VDD_IO2 

C78 

10uF 

C82 C86 

U2A 

U2B 

0.1uF 0.1uF 

R104 

10K 

D7 

I/O7 

G6 

D7 6,7,9 

1 

D6 

N.C.1 

33.N.C. 

E2 

A3 

Vss.1 

I/O6 

H5 

D6 6,7,9 

2 

D5 

N.C.2 

32.N.C. 

E1 

EM_WAIT4 

A6 

R/B 

I/O5 

G5 

D5 6,7,9 

3 

D4 

N.C.3 

31.N.C. 

D6 

6,9 OE 

B2 

RE 

I/O4 

H4 

D4 6,7,9 

4 

N.C.4 

30.N.C. 

D5 

EM_CS4n 

A4 

CE 

5 

N.C.5 

29.N.C. 

D4 

6 

N.C.6 

28.N.C. 

D3 

R107 

7 

VDD_IO2 

F6 

10K 

Vcc 

VccQ G4 

N.C.7 

27.N.C. 

D2 

8 

N.C.8 

26.N.C. 

D1 

C H1 

Vss.2 

Vss.3 

H6 

9 

N.C.9 

25.N.C. 

C6 

C 

10 

N.C.10 

24.N.C. 

C5 

11 

6,9 A12 

A12 CLE 

N.C.11 

23.N.C. 

C4 

B3 

6,7,9 A11 

A11 ALE 

CLE 

A2 

D3 

ALE 

I/O3 

H3 

D3 6,7,9 

D2 

6,7,9 WE 

A5 

WE 

I/O2 

H2 

D2 6,7,9 

A1 

D1 

WP 

I/O1 

G2 

D1 6,7,9 

D0 

I/O0 

F2 

D0 6,7,9 

K9F1208R0C-JIB0 

K9F1208R0C-JIB0 

NAND 

B B 


A 

Title: 



NAND FLASH 

Revision: 

Size: B 

DWG NO 512702-0001 

A 

Date: 


6 

6 

+ 

12 

13 

14 

15 

B1 

B4 

B5 

B6 

C1 

C2 

C3 

N.C.12 

N.C.13 

N.C.14 

N.C.15 

N.C.16 

N.C.17 

N.C.18 

N.C.19 

N.C.20 

N.C.21 

N.C.22 

43.N.C. 

42.N.C. 

41.N.C. 

40.N.C. 

39.N.C. 

38.N.C. 

37.N.C. 

36.N.C. 

35.N.C. 

34.N.C. 

G3 

G1 

F5 

F4 

F3 

F1 

E6 

E5 

E4 

E3 

A-9

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


U1 

D D 

BA1 

D0 

6,7 BA1 

A1 

A0 

A1 

D0 

F2 

D0 6,7,8 

D1 

6,7 A0 

B1 

A1 

A2 

D1 

E2 

D1 6,7,8 

D2 

6,7 A1 

C1 

A2 

A3 

D2 

G3 

D2 6,7,8 

D3 

6,7 A2 

D1 

A3 

A4 

D3 

E4 

D3 6,7,8 

D4 

6,7 A3 

D2 

A4 

A5 

D4 

E5 

D4 6,7,8 

D5 

6,7 A4 

A2 

D5 6,7,8 

A5 

A6 

D5 

G5 

D6 

VDD_IO2 

6,7 A5 

C2 

D6 6,7,8 

A6 

A7 

D6 

G6 

D7 

6,7 A6 

A3 

D7 6,7,8 

A7 

A8 

D7 

H7 

D8 

6,7 A7 

B3 

D8 6,7 

A8 

A9 

D8 

E1 

D9 

6,7 A8 

C3 

D9 6,7 

A9 

A10 

D9 

E3 

D10 

6,7 A9 

D3 

D10 6,7 

A10 

A11 

D10 

F3 

D11 

6,7 A10 

C4 

D11 6,7 

A11 

A12 

D11 

F4 

R101 

D12 

6,7,8 A11 

A5 

D12 6,7 

A12 

A13 

D12 

F5 

D13 

6,8 A12 

B5 

D13 6,7 

A13 

A14 

D13 

H5 

NO-POP 

D14 

A13 

C5 

D14 6,7 

A14 

A15 

D14 

G7 

D15 

A14 

D7 

D15 6,7 

A15 

A16 

D15 

E7 

A15 

D8 

A16 

A17 

A16 

A7 

A17 

A18 

WAIT 

F7 

R103 NO-POP 

EM_WAIT2 6 

A17 

B7 

A18 

A19 

A18 

C7 

A19 

A20 

A19 

C8 

A20 

A21 

C A20 

A8 

C 

BA0 

A22 

VDD_IO2 

6,7 BA0 

G1 

A23 

VPP A4 

H8 

NC/A24 

B6 

NC/A25 

VCC.1 

H3 

VCC.2 

A6 

R105 

EM_CS2n 

VCCQ.1 

D5 

10K 

EM_CS2n 

B4 

CE 

VCCQ.2 

G4 

C76 C77 C81 C84 

6,8 OE 

F8 

OE 

VCCQ.3 

D6 

.1uF .1uF .1uF .1uF 

6,7,8 WE 

G8 

WE 

1V8_SYS_RESETz 

VSS.1 

B2 

12 1V8_SYS_RESETz 

D4 

RSTn 

VSS.2 

H4 

VDD_IO2 

FLASH_WPn 

VSS.3 

H2 

C6 

WPn 

VSS.4 

H6 

R106 

E6 

CLK 

RFU.1 

F1 

RFU.2 

H1 

F6 

ADV 

RFU.3 

G2 

RFU.4 

B8 

RFU.5 

E8 

PC28F128P30T85 

B B 


A 

Title: 



NOR FLASH 

Revision: 

Size: B 

DWG NO 512702-0001 

A 

Date: 


0 

6 

6 

6 

6 

6 

6 

6 

6 

6 


1 

2 

3 

4 

5 

0 

0 

1 

2 

3 

4 

5 


VDD_SAR 

R223 

FB3 

JP18 

1 2 

2 NO-POP 

BLM21AG151SN1D 

B 

V3.3 

JP19 

CPU_3V3_USB FB8 

C134 

R282 

NO-POP 

0.01uF 

NO-POP 

2 1 

1 2 

D V1.3 


D 

PWR JP 

C55 C151 C171 

U13B 

R231 0 

10uF 0.1uF 1000pF 

PLL 

V1.8 

VDDA_PLL 

C10 

R194 

LDO_IN 

JP11 

VSSA_PLL 

D9 

H12 

LDO_IN 

2 NO-POP 

USB_VDD_IN 

USB_VDDA3P3 

B DSP LDOI SEL 

LDO_IN 

DSP_LDO_OUT 

C155 

LDOI.2 

F14 

R182 

FB10 

H11 

DSP_LDO1.3 DSP_LDO_OUT 

0.1uF NO-POP 

USB_VSSA3P3 

DSP_LDOO E10 

V3.3 

1 2 

RSV6 


RSV6 

D13 

C53 

C139 C173 

H10 

LDO_EN 

USB_VDDA1P3 

DSP_LDO_EN D12 

VDDC 

1uF 

0.1uF 0.01uF 

0 

3 

C 

A 1 

CVDD.1 

F6 

H9 

AGND 

USB_VSSA1P3 

CVDD.2 

H8 

FB9 

CVDD.3 

J6 

AGND 

CVDD.4 

K10 

CVDD.5 

L5 

1 2 

J13 


USB_VDD1P3 

RSV1(CVDD) 

J11 

C RSV2(CVDD) 

J10 

R181 0 

C 

C54 

C150 C172 

10uF 

0.1uF 1000pF 

H13 

LDO_IN 

CPU_3V3_USB 

USB_VSS1P3 

DVDDIO.1 

F7 

FB7 

DVDDIO.2 

K7 

DC_VDD_IO1 

AGND 

AGND 

DVDDIO.3 

K12 

DVDDIO.4 

N14 

R234 0 

1 2 

G8 


USB_VDDPLL 

DVDDIO.5 

P3 

DC_VDD_IO1 

DVDDIO.6 

P8 

C56 

C137 C170 

R67 

10uF 

0.1uF 1000pF 

G11 

DVDDEMIF.1 

A2 

100K 

USB_VSSPLL 

DVDDEMIF.2 

A5 

DC_VDD_IO2 

LDO_IN AGND 

AGND 

DVDDEMIF.3 

E6 

DVDDEMIF.4 

F5 

POR_BGRST LDO_EN PM_CTL 

RSV6 

LDO_IN 

DVDDEMIF.5 

G5 

F13 

LDOI.3 

DVDDEMIF.6 

H5 

SAR LDOI SEL 

USB_LDO_OUT 

DVDDEMIF.7 

H7 

C154 

DVDDEMIF.8 

J5 

DC_VDD_IO2 

USB_LDO_OUT 

DVDDEMIF.9 

P2 

F12 

R285 

JP6 R286 

R284 

0.1uF 

USB_LDOO 

JUMPER 2 0 

0 

LDO_IN 

VSS.1 

A13 

B LDO_IN 

VSS.2 

A14 

B12 

B 

LDOI.1 

VSS.3 

D7 

SAR_LDO12 

VSS.4 

D11 

C147 

SAR_LDO12 

VSS.5 

E9 

0.1uF 

A12 

ANA_LDO 

VSS.6 

E11 

POR_BGRST 

VSS.7 

E12 

C12 

PM_CTL 

(RSV0)POR_BGRST 

VSS.8 

E13 

D14 

DSP_LDO_EN: 

VDD_SAR 

(RSV3)PM_CTL 

VSS.9 

E14 

If high, the DSP_LDOO is tri-stated 

VSS.10 

F9 

If low, the DSP_LDOO is 1.3V or 1.05V 

DC_VDD_SAR 

VSS.11 

F10 

depending on DSP_LDO_V 

A10 

VDDA_ANA 

VSS.12 

G6 

VSS.13 

G7 

VSS.14 

H6 

VSS.15 

J7 

C51 

C142 

B13 

BG_CAP 

VSS.16 

J8 

1uF 

VSS.17 

J9 

0.1uF 

VSS.18 

K8 

C158 

VSS.19 

K9 

B10 

0.1uF 

VSSA_ANA.1 

VSS.20 

K11 

B14 

SAR_LDO12 

VSSA_ANA.2 

VSS.21 

K13 

R66 

100K 

SAR_LDO12 


AGND 

R226 

FB5 

FB2 


A 

1 2 

1 2 

JP16 



NO-POP 

Title: 


PWR JP B 2 

R218 

AGND 

PLL 

Page Contents: TMS320C5515 POWER 

V1.3 

NO-POP 

Revision: 

Size: B 

DWG NO 512702-0001 

A 

Date: 


0 

3 

C 

A 1 

1 

A 

B 2 

R64 

R65 

100K 

100K 

3 

C 

A 1 

A-11

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


VDDC 

DC_VDD_IO2 

DC_VDD_IO2 

VDDC 

C22 

C106 C105 C109 C110 C113 C124 C118 C119 C129 

C120 C125 C122 C127 C148 C144 C132 C133 C116 C111 

10uF 

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 

1uF 0.01uF 1uF 0.01uF 1uF 0.01uF 1uF 0.01uF 1uF 0.01uF 

D JP8 NO-POP 

D 

DC_VDD_IO2 1 2 

TPS65023_VCC_1V8 

CPU_VCC_CORE 

R146 1 1% 

I 

JP37 NO-POP 

1 2 

R102 

VDDC 

NO-POP 

R1 1 1% 

2 

DSP_LDO_OUT 

DSP_LDO_OUT 

I 

U7 

INA219IDCN 

V_PWR_MON 

1 

2 

U3 

INA219IDCN 

V_PWR_MON 

GND 

C C 

I2C_SCL_PWR 

I2C_SDA_PWR 

3 

8 

7 

5 

6 

4 

A1 

A0 

SCL 

SDA 

VS 

3 

GND 

8 

A1 

7 

A0 

5 

SCL 

6 

SDA 

4 

VS 

R108 

B 

JP1 

NO-POP 

C102 

0.1uF 

I2C_SCL_PWR 

I2C_SDA_PWR 

C83 

0.1uF 

DC_VDD_IO1 

C46 

DC_VDD_IO1 

C153 

C157 

C160 

C140 

C141 

C159 

10uF 

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 

V1.3 

I 

USB_VDD_IN 

JP38 NO-POP 

DC_VDD_IO1 

VDD_IO1 

R219 

JP17 NO-POP 

1 2 

NO-POP 

1 2 

JP15 

R59 1 1% 

2 

B 

NO-POP 

R224 1 1% 

B R227 

USB_LDO_OUT 

B 

I 

USB_LDO_OUT 

2 

1 

U21 

INA219IDCN 

V_PWR_MON 

V_PWR_MON 

3 

8 

7 

5 

6 

4 

1 

A 

C 3 

U20 

INA219IDCN 

C166 

0.1uF 

V_PWR_MON 

C165 

0.1uF 

I2C_SCL_PWR 

I2C_SCL_PWR 

13,15 I2C_SCL_PWR 

I2C_SDA_PWR 

I2C_SDA_PWR 

13,15 I2C_SDA_PWR 

A TP1 


A 

GND 

Title: 



CPU DECOUPLING CAPS 

Revision: 

Size: B 

DWG NO 512702-0001 

A 

Date: 


0 

0 

3 

GND 

8 

A1 

7 

A0 

5 

SCL 

6 

SDA 

4 

VS 

VIN- 

VIN+ 

VIN- 

2 

VIN+ 

1 

GND 

A1 

A0 VIN- 

SCL 

SDA 

VIN+ 

VS 

VIN- 

VIN+ 

2 

1 

1 

A 

C 3 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


VDD_IO1 

D D 

R109 

100K 

14 

PWR_RSTn 

TP2 

nRESET 

VDD_IO1 

JP2 

1 

2 

nRESET 2,19,20 

3 

HEADER 3 

R100 

VDD_IO2 

C 100K 

C 

VDD_IO1 

14 

PB_RESET 

C75 

C79 

C80 

.1uF 

.1uF 

100nF 

U29 

1 

VCCA VCCB 6 

5 

DIR 

3 

1V8_SYS_RESETz 

A 

B 4 

1V8_SYS_RESETz 9 

2 

GND 

SN74AVC1T45 

VDD_IO1 

B B 

R203 

10K 

R183 33 

D 

EMBED_EMU_XRSp 

G 

Q4 

BSS138 

S 

R198 

10K 


A 

Title: 



RESET 

Revision: 

Size: B 

DWG NO 512702-0001 

B 

Date: 


A-13

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


1 2 

1 2 

V5 

TP23 

SW5A 

J16 

F1 FUSE_3A 

R95 

VPWR_IN 

Power Jack 

VIN_EVM 

1201M2S3AQE2 

D7 470 

C73 

+ 

D8 

JP22 POP 

D D 

220uF 

2 1 

R239 1 1% 

TP30 TP31 

GND 2 

Max Input: 5VDC, 4 A. 

Use only recommended power supplies. 

JP39 

HEADER 3 

V_PWR_MON 

I2C_SCL_PWR 11,15 

C I2C_SDA_PWR 11,15 

C 

TP28 

V_PWR_MON 

18 

Battery_Measurement 

TP32 

Battery Holder 

L9 6.8uH 20% 

1 

SW5B 

SW1 

VOUT15 

15 

2 

SW2 

VOUT14 

14 

VOUT13 

13 

R256 

+ 

1 4 5 

C184 C67 

B B 

C72 R92 

1M 1% 

2.2uF 220uF 

1201M2S3AQE2 

10uF 

475K 1% 

FB 12 

7 

R261 

LBI 

NC 16 

R93 

8 

R255 

180K 1% 

R91 

SYNC 

11 

182K 1% 

GND 

3 

1M 1% 

TP33 

PGND3 

J18 

4 

B- 

PGND4 

LBO 10 

5 

PGND5 

INT0 


A 

Title: 



POWER IN 

Revision: 

Size: B 

DWG NO 512702-0001 

A 

Date: 


2 

1 

2 

3 

3 

U24 

INA219IDCN 

C59 

0.1uF 

B+ 

R254 

0 

+ 

6 

4 

6 

5 

7 

8 

3 

VS 

SDA 

SCL 

A0 

A1 

GND 

VIN+ 

VIN- 

1 

2 

LEDRED 

9 

U26 TPS61030-ADJ 

EN 

6 

VBAT 

17 

PWR_PAD 

SMCJ06A 

VBATOUT 

R88 

C190 

0.1uF 

0 

0 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 



+ C66 

10uF 



R247 0 

D L6 2.2uH 

D 

C185 

0.1uF 

R79 

NO-POP 


TP26 

TP-60 

TP27 

TP-60 

TP25 

TP-60 

R245 

1K 

+ C181 

22uF 

VRTC 

R84 

100K 

VRTC 

U25 

R70 R69 

R71 

4.7K 4.7K 

10K 


C C 

R258 

1 TP20 

+ C189 

22.1K 

TP-60 

22uF 

+ C68 

10uF 

1 

R77 NO-POP 

DEFDCDC3 

SDAT 

29 

I2C_SDA 2,5,15,17,18,19 

2 

R76 NO-POP 

VDCDC3 

SCLK 30 

I2C_SCL 2,5,15,17,18,19 

3 

L7 2.2uH 

PGND3 

INTn 

28 

4 

L3 

RESPWRONn 

27 

PWR_RSTn 12 

5 

VINCDDC3 

TRESPWRON 26 

6 



L8 2.2uH 

VINDCDC1 

DCDC1_EN 25 

7 

TPS65023_VCC_CORE 

L1 

DCDC2_EN 24 

8 

C60 

PGND1 

DCDC3_EN 23 

9 

0.001uF 

C69 

VDCDC1 

LDO_EN 22 

10 

DEFCDCD1 

LOWBATn 

21 

R74 R73 R72 

10uF 

C188 

R85 

2K 

47K 

10K 

22uF 

100K 1% 

VIN_EVM VIN_EVM 

TP21 

TP-60 

TPS65023 

TPS65023_LDO_1V3 

B B 

V_CORE_SEL 

R82 

R83 

OFF = 1.05V 

10K 

NO-POP 

ON = 1.30V default 

R259 

C63 C62 C61 

R257 

+ C64 

NO-POP 0.1uF 0.1uF 

243K 1% 130K 1% 

22uF 


R81 

VRTC 

+ C182 

NO-POP 

2.2uF 

DIP_SWITCH_2 

C65 

C183 

R78 

VOUT = VDEFDCDC * (( R85 + R257eq)/R257eq ) 

R80 

10uF 

NO-POP 

VDEFDCDC = 0.6 

DEFLDO2 DEFLDO1 VLDO1 VLDO2 

2.2uF 

0 0 1.3 V 3.3 V 

R250 

0 1 2.8 V 3.3 V 

0 

1 0 1.3 V 1.8 V 

1 1 1.8 V 3.3 V 


A 

R3 33 

Title: 



POWER MANAGEMENT 

Revision: 

Size: B 

DWG NO 512702-0001 

B 

PB_RESET 12 

Date: 


+ 

+ 

. 

0 

+ 

+ 

11 

12 

13 

14 

15 

16 

17 

18 

19 

20 

HOT_RESETn 

DEFLDO1 

DEFLDO2 

VSYSIN 

VBACKUP 

VRTC 

AGND2 

VLDO2 

VINLDO 

VLDO1 

PWR_PAD 41 

AGND1 

40 

LOWBAT_SNS 39 

PWRFAIL_SNS 38 

VCC 37 

VINDCDC2 

36 

L2 

35 

PGND2 

34 

VDCDC2 

33 

DEFDCDC2 

32 

PWRFAILn 

31 

VDD_IO1_SEL 

OFF = 1.8V 

TPS65023_LDO_VLDO2 

ON = 3.3V default 

R252 

R251 


R75 

SW4 

NO-POP 10K 


10K 

ON 

1 4 

2 3 

3 

4 

SW1 

RESET 

1 

2 

1 

2 

A-15

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


VDD_IO1 Power Supply 

0 


0 

NO-POP 

1 

JP25 

2 

V3.3 

VDD_IO1 JP21 

V1.3 

NO-POP 

TPS65023_LDO_1V3 2 1 

0 

JP24 NO-POPPOP 

2 1 

TPS65023_LDO_VLDO2 

R265 

1 1% 

R241 0 

R237 0 

D D 

2 

1 

VIN+ 

U27 

INA219IDCN 

GND 

SDA 

SCL 

V_PWR_MON 

A0 

A1 

VS 

3 

7 

8 

6 

5 

4 

V_PWR_MON 

C191 

0.1uF 

I2C_SCL_PWR 

I2C_SDA_PWR 

JP26 

JP23 

NO-POP 

C TPS65023_VCC_1V8 

C 

NO-POP 

2 1 

2 1 

VDD_IO2 TPS65023_VCC_CORE 

CPU_VCC_CORE 

R264 

R238 

VDD_IO2 Power Supply 

V_PWR_MON V_PWR_MON 

NO-POP 

1 

JP20 

R145 

2.2K 

R137 

2.2K 

2 

V1.8 

R235 

1 1% 

I2C_SCL_PWR 


I2C_SCL_PWR 

11,13 

I2C_SDA_PWR 

I2C_SDA_PWR 

11,13 

2 

1 

B B 

U23 

J3 

INA219IDCN 

R147 0 

2,5,14,17,18,19 I2C_SDA 

1 

R133 0 

2 

V_PWR_MON 

2,5,14,17,18,19 I2C_SCL 

3 Power Monitor I2C Probe Point Headers 

VIN- 

VIN- 

VIN+ 

HEADER 3 

GND 

A0 

A1 

SDA 

SCL 

VS 

3 

7 

8 

6 

5 

4 


TP17 

Test Point_1 

TP18 

Test Point_1 

V_PWR_MON 

C179 

0.1uF 

V_PWR_MON 

R68 

I2C_SCL_PWR 

I2C_SDA_PWR 

TP12 

+ C178 

33uF 

GND 


A 


POWER ROUTER 

Title: 


Revision: 

DWG NO 512702-0001 

A 

20 

Sheet o f Monday, February 01, 2010 15 Size: B 

Date:

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


D D 

VDD_IO1 

VDD_IO1 

R290 

10K 

MMC0.WP 2 

J15 

MMC0_DATA2 

9 

DAT2 

WP WP 

TP19 

MMC0_DATA3 

1 

DAT3 

COM CO 

MMC0.WP 

MMC0_CMD 

2 

CMD CARD_DETECT 

CD 

TP22 

MMC0.INS 

3 

VSS1 

C 4 

VDD 

C 

MMC0_CLK 

5 

CLK 

6 

R293 

VSS2 

MMC0_DATA0 

7 

DAT0 

MMC0.INS 2 

MMC0_DATA1 

8 

1K 

DAT1 

R291 

VDD_IO1 

10K 

MMC/SD_CARD 

B B 


A 

Title: 



MMC/SD SOCKETS 

Revision: 

Size: B 

DWG NO 512702-0001 

A 

Date: 


2 

2 

2 

2 

2 

2 

R240 

R242 

R248 

R262 

R263 

R266 

10K 

10K 

NO-POP 

10K 

10K 

10K 

+ 

C187 

C186 

10uF 

0.1uF 

A-17

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


TP24 

CTS 

RXD 

D GND 

RTS 

D 

VDD_IO1 

TXD 

VDD_IO1 

R121 

10K 

R125 

10K 

JP3 

POP 

1 2 

UART_EN 

R2 

10K 

1 

13 

12 

16 

9 

EN_L 

T1IN 

T2IN 

R1IN 

R2IN 

U5 

VCC 19 

T1OUT 

T2OUT 

R1OUT 

R2OUT 

17 

8 

15 

10 

VDD_IO1 

J1 

2 

CONNECTOR DB9 

I2S3_DX 

C1+ 

2,5 UART_TX 

4 

C1- 

V+ 

3 

5 

I2S3_CLK 

C2+ 

V- 

7 

GND SHIELD 

2,5 UART_RTS 

6 

C2- 

NC-1 

14 

C95 C100 

NC-2 

11 

R5 

C4 C3 C92 

0.1uF 0.1uF 

18 

GND 

SHUTDOWN 20 

10K 

0.1uF 0.1uF 0.1uF 

C C 

MAX3222 

I2S3_FS 

2,5 UART_CTS 

I2S3_RX 

2,5 UART_RX 

256K-Bit I2C EEPROM 

VDD_IO1 

U6 

R130 

1 

R129 10K 

A0 VCC 8 

2 

R128 10K 

A1 WP 7 

3 

C91 

B 10K 

NC SCL 

6 

4 

B 

VSS SDA 5 

0.1uF 

24WC256 

2,5,14,15,18,19 I2C_SDA 

2,5,14,15,18,19 I2C_SCL 

R114 

R115 

256K-Bit SPI EEPROM 

VDD_IO1 

U9 

2,18 SPI_CS0 

1 

CS 

VCC 8 

2,18 

2,18 

SPI_DX 

SPI_CLK 

5 

HOLD 7 

C115 

SIN 

6 

SCLK WP 3 

0.1uF 

4 

GND 

SO 2 

A CAT25C256K 


A 

SPI_RX 2,18 

Title: 



RS232(UART)/EEPROM 

Revision: 

Size: B 

DWG NO 512702-0001 

A 

Date: 


0 

0 

5 

9 

4 

8 

3 

7 

2 

6 

1 

11 

10 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


LAYOUT NOTE: 

These 3 connectors need to be placed 

in specific coordinates to allow for Interfacing 

to the ADS Codec Daughter Card 

V1.8 V3.3 

J14 

J10 

J13 

D D 

GPAIN0 

ADS_GPIO4 

GPIO11 

GPAIN0 

2 

1 R260 NO-POP 

2 

1 

GPAIN1 

V5 

ADS_GPIO4 

1 

2 

GPIO11 2 

GPAIN1 

4 

3 R249 NO-POP 

4 

3 

2,17 SPI_CLK 

3 

4 

GPAIN2 

GPIO6 

ADS_GPIO10 

GPAIN2 

6 

5 R246 NO-POP 

6 

5 

I2S1_CLK 

5 

6 

ADS_GPIO10 2 

GPAIN3 

ADS_GPIO1 

GPAIN3 

8 

7 R243 NO-POP 

8 

7 

2,17 SPI_CS0 

7 

8 

ADS_GPIO1 2 

10 

9 

10 

9 

GPIO7 

I2S1_FS 

9 

10 

12 

11 

ADS_GPIO0 

2,17 SPI_DX 

11 

12 

ADS_GPIO0 2 

14 

13 

GPIO9 

2,17 SPI_RX 

13 

14 

I2S1_RX 2 

16 

15 

INT1 

15 16 

18 

17 

HEADER 5X2 

XF 

17 18 

I2C_SCL 2,5,14,15,17,19 

20 

19 

GPIO8 

I2S1_DX 

19 

20 

I2C_SDA 2,5,14,15,17,19 

ADS_GPIO3 ADS_GPIO2 

2 ADS_GPIO3 

21 22 

ADS_GPIO2 2 

HEADER 10X2 

HEADER 11x2 

TP14 

ADS_GPIO5 

ADS_GPIO5 2 

GPIO5 

C C 

TP29 

VDD_SAR 

GND 

R273 

20k 

R253 

GPAIN 

R272 

R280 

R99 R98 

R270 R271 

R268 

R267 R269 

Remove R105 for 

Internal Voltage 

Measurement 

24.9K 1% 

5.36K 1% 

5.49K 1% 

B B 

C197 

C196 

SW9 

SW13 

SW15 

SW12 

SW11 

SW10 

SW7 

SW14 SW8 SW6 

NO-POP 

0.1uF 

Shift 

STOP 

REC 

FWD 

PLAY 

RWD 

UP 

DN 

MODE MENU 

6.34K 1% 

4.75K 1% 

6.49K 1% 

17.4K 1% 

22.6K 1% 

60.4K 1% 

GPAIN Battery 

Measurement 

GPAIN0 

R89 

13 

Battery_Measurement 


A 

Title: 



SAR RESISTOR NETWORK 

Revision: 

Size: B 

DWG NO 512702-0001 

A 

Date: 


2 

2 

2 

2 

2 

0 

0 

2 

2 

2 

2 

2 

2 

A-19

5 

5 

+ 

0 

4 

4 

3 

3 

0 

0 

2 

2 

0 

0 

0 

0 

1 

1 


V1.8 

JP40 NO-POP 

1 2 

FB11 1 2 


PWRJP 

C17 C107 

C117 C25 

R292 0 

22uF 0.1uF 

0.1uF 22uF 

VDD_IO1 

FB12 1 2 

JP14 NO-POP 

2 1 

GND-A 


D D 

PWRJP 

C32 C126 

R192 0 

10uF 0.1uF 

JP12 

Route all mic lines away from digital signals! 

V3.3A 

3 

JP7 NO-POP 

MIC_BIAS 2 

1 

1 2 

R186 R187 

C108 C18 

PWRJP 

V3.3A 2.2K 2.2K 

Remove if not 

0.1uF 22uF 

R139 0 

C44 

R209 

using with I2C 

U12 

R188 

NO-POP 

MIC_DET 

10uF 

TLV320AIC3204IRHBT 

GND-A 

M1 GND-A 

1 

MIC1_IN 

C37 

R144 NO-POP 

nRESET 2,12,20 

2 

0.1uF 

AIC_MBIAS 

19 

LEFT MIC 

AIC_MIC1L 

MICBIAS 

13 

AIC_RST 

AIC_RST 2 

GND-A 

AIC_MIC1R 

IN1_L 

RESET 

31 

14 

M2 

AIC_LINE2L 

IN1_R 

15 

AIC_IISCLK 

R161 

+ 

I2S2_CLK 2 

MIC2_IN 

AIC_LINE2R 

AIC_IISFS 

C 1 

C38 

IN2_L 

BCLK 2 

16 

I2S2_FS 2 

C 

2 

0.1uF 

AIC_LINE3L 

WCLK 3 

R165 

IN2_R 

20 

AIC_IISD0 

R169 

I2S2_DX 2 

AIC_LINE3R 

IN3_L 

DIN 4 

21 

AIC_IISD1 

RIGHT MIC 

IN3_R 

DOUT 

5 

R173 

I2S2_RX 2 

GND-A 

25 

J9 

AUDIO_MCLK 3 

C164 

HPL 

MCLK 1 

2 

27 

0.47uF 

HPR 

4 

22 

LOL 

5 

23 

STEREO IN 1 

C168 

LOR 

3 

1 

0.47uF 

R177 

SCL/SSZ 

9 

I2C_SCL 2,5,14,15,17,18 

30 

SDA/MOSI 

10 

R180 

LDO_SEL 

I2C_SDA 2,5,14,15,17,18 

32 

GND-A 

GPIO 

SPI_SEL 

12 

SJ1-3515-SMT, 5PJACK STEREO 

MISO 11 

SCLK/MIC_DET 

8 

18 

J12 

2 

C176 

REF 

4 

0.47uF 

5 

VDD_IO1 

STEREO IN 2 

3 

C180 

1 

0.47uF 

V3.3 

V3.3A 

FB4 

R136 

J5 

GND-A 

NO-POP 

1 2 

SJ1-3515-SMT, 5PJACK STEREO 


B AIC_MOSI 

4 

B 

J4 

2 CONN_HP_LOUT C5 220uF HEADPHONE_LOUT 

C30 C128 

AIC_SPI_SEL 

3 

4 

GND-A 

AIC_MISO 

2 HDR4 

Tie Analog Power to Digital Power through single 

5 

10uF 0.1uF 

AIC_SCLK 

1 

point connection or Ferrite Bead. 

HEADPHONES OUT 

3 CONN_HP_ROUT C1 220uF HEADPHONE_ROUT 

1 

FB1 

MIC_DET 

R135 

GND-A 

1 2 

4.7K 


SJ1-3515-SMT, 5PJACK STEREO GND-A 

VDD_IO1 

TP15 

GND-A 

J7 

2 

R170 100 C114 AIC3254_LOUT 

4 

1uF 

R141 NO-POP 

5 

GND 

STEREO OUT 

3 

R197 100 C145 AIC3254_ROUT 

1 

1uF 

C121 

0 = LDO_OFF 

.047uF C156 

.047uF 

R140 1 = LDO_ON 

SJ1-3515-SMT, 5PJACK STEREO GND-A 

4.7K 

AVDD 24 

HPVDD 26 

IOVDD 6 

DVDD 29 

9 

8 

TP5 

PPAD 

IOVSS 

AVSS 

DVSS 

AIC_GPIO 


33 

7 

17 

28 

9 

8 

+ 

+ 

9 

8 

9 

8 

GND-A 

GND-A 


A 


CODEC 

Title: 


Revision: 

DWG NO 512702-0001 

A 

20 

Sheet o f Monday, February 01, 2010 19 Size: B 

Date:

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


V13 

C202 

C194 

4.7uF,16V 

10uF,16V 

C200 

C201 

D14 

D15 

10uF 

10uF MMBD4148 MMBD4148 

D D 

3 

1 3 

1 

R281 0 

VDD_IO1 

J19 

1 

NC-1( GND ) 

2 

VCC 

3 

VCOMH 

4 

R275 50 

VDDIO 

5 

VSL 

6 

LCD_DATA7 

NC-6 

LCD_DATA7 

7 

LCD_DATA6 

D7 

LCD_DATA6 

8 

LCD_DATA5 

D6 

LCD_DATA5 

9 

LCD_DATA4 

D5 

LCD_DATA4 

10 

LCD_DATA3 

D4 

LCD_DATA3 

11 

LCD_DATA2 

D3 

LCD_DATA2 

12 

LCD_DATA1 

D2 

VDD_IO1 

LCD_DATA1 

13 

LCD_DATA0 

D1 

LCD_DATA0 

14 

D0 

LCD_RE 

15 

R274 NO-POP 

E/RDn 

LCD_nWE 

16 

R/Wn 

17 

R277 0 

BS0 

18 

BS1 

LCD_BIAS_OE 

19 

CSn 

C LCD_ALE 

20 

D/Cn 

C 

2,12,19 nRESET 

21 

R276 560K 1% 

RESETn 

22 

IREF 

23 

GPIO1 

24 

GPIO0 

25 

NC-25 

26 

VDD 

27 

VCI 

C199 C204 C198 C203 

28 

VDD_IO1 

R279 NO-POP 

VSS 

29 

NO-POP NO-POP NO-POP 1uF 

R278 0 

NC-29 

30 

NC-30( GND ) 

B B 

LCD POWER 13V 

V3.3 

V13 

GPIO11_LCD_PWR 

1 

1 

R94 


A 

10K 

Z3 

Z4 

1 

1 

Title: 



COLOR LCD INTERFACE 

Revision: 

Size: B 

DWG NO 512702-0001 

A 

Date: Sheet o f Monday, February 01, 2010 20 20 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

0SD-2828GDEDF11 

2 

2 

OEL Display Module 

C195 C205 

10uF 4.7uF 

This board uses a mirrored footprint for J19 

D6 

L10 2.2uH 

MBR0520 C193 R96 C192 

U28 

1uF 1.6M 1% 10pF 

5 

Vin SW 1 

C74 

C71 

GND 2 

10uF,16V 

R97 

10uF 

4 

EN FB 3 

180K 

TPS61041 

Z1 

Z2 

A-21



Appendix B 

Mechanical Information 

This appendix contains the mechanical information about the 

TMS320C5515 EVM produced by Spectrum Digital. 

B-1


THIS DRAWING IS NOT TO SCALE 

B-2 TMS320C5515 EVM Technical Reference

Printed in U.S.A., February 2010 

512705-0001 Rev. A

TMS320C5515 Evaluation Module (EVM) - Spectrum Digital Support

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