C6A816x/AM389x Evaluation Module - Spectrum Digital Support

C6A816x/AM389x 

Evaluation Module 

Technical 

Reference 

2011 DSP Development Systems

C6A816x/AM389x Evaluation 

Module Technical Reference 

513830-0001 Rev. A 

January 2011 

SPECTRUM DIGITAL, INC. 

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Tel: 281.494.4505 Fax: 281.494.5310 

sales@spectrumdigital.com www.spectrumdigital.com

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WARNING 

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Copyright © 2011 Spectrum Digital, Inc.

Contents 

1 Introduction to the C6A816x/AM389x Evaluation Module . . . . . . . . . . . . . . . . . . . . . . 1-1 

Provides you with a description of the C6A816x/AM389x Evaluation Module, key features, and 

block diagram. 

1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 

1.2 Functional Overview of the C6A816x/AM389x EVM . . . . . . . . . . . . . . . . . . . . . . . . 1-4 

1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 

1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 

1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 

1.6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 

2 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 

Describes the operation of the major board components on the C6A816x/AM389x Evaluation 

Module. 

2.1 EMIF-A Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 

2.1.1 EMIF-B SDRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 

2.1.2 Memory Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 

2.1.3 UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 

2.1.4 USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 

2.1.5 HDMI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 

2.1.6 Video DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 

2.1.7 PCIe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 

2.2 AIC3106 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 

2.3 Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 

2.4 I 2 C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 

2.5 SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 

2.6 Power Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 

2.7 Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

3 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 

Describes the physical layout of the C6A816x/AM389x Evaluation Module and its connectors. 

3.1 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 

3.2 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 

3.2.1 J1, 12V Power In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 

3.2.2 J2, HD15 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 

3.2.3 J3, F Type Video Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 

3.2.4 J4, Composite Video Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 

3.2.5 J5, Component Video , RCA Jack - Green . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 

3.2.6 J6, Component Video , RCA Jack - Blue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 

3.2.7 J7, Component Video , RCA Jack - Red . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 

3.2.8 J8, Disk Drive Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 

3.2.9 J9, SCART21 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 

3.2.10 J10, Ethernet Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 

3.2.11 J11, SATA Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 

3.2.12 J12, SATA Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 

3.2.13 J13-1/J13-2, USB-A Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 

3.2.14 J14, MSP430 Programming Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 

3.2.15 J15, CTI JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 

3.2.16 J16, VLYNQ/Transport Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 

3.2.17 J17, Video/Transport Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 

3.2.18 J18, GPMC Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 

3.2.19 J19, MCASP/XXX Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 

3.2.20 J20, Serial Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 

3.2.21 P1, S-Video Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 

3.2.22 P2, Headphone Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 

3.2.23 P3, Line Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 

3.2.24 P4, Line In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 

3.2.25 P5, Mic In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 

3.2.26 P6, HDMI Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 

3.2.27 P7, DB9 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 

3.2.28 P8, PCIe Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 

3.2.29 P9, SD/MMC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 

3.2.30 P10, DB9 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30 

3.2.31 P11, Fan Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 

3.3 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 

3.4 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 

3.4.1 SW1, On/Off Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 

3.4.2 SW2, User Readable Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 

3.4.3 SW3, Boot Mode/Configuration Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 

3.4.4 SW4, On Board Memory Enable Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 

3.4.5 SW5, PCI/WDOG Reset Enable Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 

3.4.6 SW6, Reset Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38 

3.5 Infra-red Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38 

3.6 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 

A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 

Contains the schematics for the C6A816x/AM389x Evaluation Module 

B Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 

Contains the mechanical information about the C6A816x/AM389x Evaluation Module

About This Manual 

Notational Conventions 

This document describes the board level operations of the C6A816x/AM389x 

Evaluation Module (EVM). The EVM is based on the Texas Instruments 

C6A816x/AM389x Processor. 

The C6A816x/AM389x Evaluation Module is a table top card that allows engineers and 

software developers to evaluate certain characteristics of the C6A816x/AM389x 

processor to determine if the processor meets the designers application requirements. 

Evaluators can create software to execute on board or expand the system in a variety 

of ways. 

This document uses the following conventions. 

The C6A816x/AM389x Evaluation Module will sometimes be referred to as the 

C6A816x/AM389x EVM or EVM. 

Program listings, program examples, and interactive displays are shown in a special 

italic typeface. Here is a sample program listing. 

equations 

!rd = !strobe&rw; 

Information About Cautions 

This book may contain cautions. 

This is an example of a caution statement. 

A caution statement describes a situation that could potentially damage your software, 

or hardware, or other equipment. The information in a caution is provided for your 

protection. Please read each caution carefully.

Related Documents, Application Notes and User Guides 

Information regarding the C6A816x/AM389x can be found at the following Texas 

Instruments website: 

http://www.ti.com 

Table 1: Manual History 

Revision 

A 

Alpha 

History 

Table 2: Board History 

PWB 

Revision 

A 

Alpha Release 

History

Chapter 1 

Introduction to the 

C6A816x/AM389x EVM 

Chapter One provides a description of the C6A816x/AM389x EVM along 

with the key features and a block diagram of the circuit board. 

Topic 

Page 

1.1 Key Features 1-2 

1.2 Functional Overview of the C6A816x/AM389x EVM 1-4 

1.3 Basic Operation 1-5 

1.4 Memory Map 1-6 

1.5 Boot Switch Settings 1-7 

1.6 Power Supply 1-8 

1-1

Spectrum Digital, Inc 

1.1 Key Features 

The C6A816x/AM389x EVM is a standalone development platform that enables users 

to evaluate and develop applications for the C6A816x/AM389x processor. Schematics 

and application notes are available to ease hardware development and reduce time to 

market. The block diagram for this EVM is shown below. 

HD PWR PWR Mon 

RS-232 

SD / MMC 

SW4 

User 

LEDs/DIP 

Switches 

MSP430 

RS-232 

NAND 

SPI 

ROM 

SW2 

I2C 

GPIO 

UART2 

SPI 

SW3 

IR 

UART1 

SD/MMC 

I 2 C Bus 

GPMC 

I2C 

ROM 

Video 

THS7360 

EMIF0 

EMIF1 

DDR2 / DDR3 DIMM Module 

816X / 389X 

THS7375 

SATA 

PCIe 

SATA0 

SATA1 

GMII 

McASP 

JTAG 

AIC3106 

PCIe 

ENET 

PHY 

Reset 

USB 

0/1 

ENET 

RJ45 

SCART 

PWR SW 

12V DC 

RF Out 

VGA 

Cr 

Cb 

Y 

C 

S-Video 

HDMI 

Mic In 

Line In 

Line Out 

HP Out 

Figure 1-1, Block Diagram C6A816x/AM389x EVM 

J16 

J17 

Video 

Video In/Out 

J18 

GPMC 

Video 

GPMC 

UART0/1/2 

Video 

GMII 

McASP/Ethernet 

J19 

J20 

UART & 

Misc I/O 

UART0/1/2 

SC0/1 

816X / 398X 

McASP 

Figure 1-2, Block Diagram C6A816x/AM389x EVM Expansion Connectors 

1-2 C6A816x/AM389x EVM Technical Reference


The EVM comes with a full complement of on board devices that suit a wide variety of 

application environments. Key features include: 

• A Texas Instruments C6A816x/AM389x device with a C674x DSP floating point 

processor and an ARM Cortex A8 processor operating up to 1 GHz. 

• 1 Gigabyte DDR2 RAM on dual EMIF DIMM card 

• 32 Megabit SPI Flash 

• 2 gigabyte NAND Flash 

• Composite video out 

• Component video out 

• Dual Host USB Interfaces 

• Video/GPMC/MCASP/Serial Expansion Interfaces 

• On-chip HDMI Interface 

• 10/100/1000 Ethernet Interface 

• SD media card interface 

• TLV320AIC3106 Stereo Codec (Line In/Out, Mic in, Headphone out) 

• 2 SATA drive interfaces 

• PCIe connector with 2 lanes 

• RS-232 Interface 

• Infra-red receiver 

• On chip real time clock 

• Configurable boot load options 

• 4 user LEDs/4 position user DIP switch 

• Single voltage power supply (+12V) 

• 20 Pin CTI JTAG Interface 

• On board power monitoring 

1-3


Figure 1-3, C6A816x/AM389x EVM 

1.2 Functional Overview of the C6A816x/AM389x EVM 

The C6A816x/AM389x on the EVM interfaces to on-board peripherals through multiple 

on-chip interfaces. The DDR2 memory is connected to a dedicated dual 32 bit DIMM. 

HDMI and video interfaces support up to 1080p resolution, along with gigabit ethernet 

and RS-232 interfaces which provide direct support for operating systems running on 

the EVM. 

An on-board AIC3106 codec allows the DSP to transmit and receive analog audio 

signals. The I 2 C bus is used for the codec control interface, while the McASP controls 

the audio stream. Signal interfacing is done through 3.5mm audio jacks that correspond 

to microphone input, headphone output, line input, and line output. 

The EVM includes 4 user LEDs, a 4 position user DIP switch, and on chip real time 

clock. On board connectors allows ease of interfacing to the daughter cards. 

An included +12V external power supply is used to power the board. On-board 

switching voltage regulators provide the CPU core voltage, +3.3V, +1.8V for peripheral 

interfacing. The board is held in reset by the on board power controller until these 

supplies are within operating specifications. 

Code Composer Studio communicates with the EVM through an 20 pin compact TI 

JTAG header. 



1.3 Basic Operation 

The EVM is designed to work with TI’s Code Composer Studio IDE TM , or 

Ubuntu/Code Sorcery tool environments. Code Composer communicates with the 

board through an on board JTAG emulator. This EVM is shipped with an EVM specific 

Code Composer Studio environment. 

1.4 Memory Map 

The C6A816x/AM389x processor has a byte addressable address space. Program 

code and data can be placed anywhere in the unified address space. Addresses are 

multiple sizes depending on hardware implementation. Refer to the appropriate device 

data sheets for more details. 

The part incorporates a triple EMIF interface. Two dedicated 32-bit wide DDR2 

interface directly to the on board dual DIMM. GPMC (General Purpose Memory 

Controller) has multiple separate addressable regions called chip enable spaces. The 

EVM uses this interface as a peripheral interface to daughter card connectors and 

NAND Flash interfaces. The memory maps for both of the processors in the 

C6A816x/AM389x device can be found in TI document SPRS680. The address ranges 

for the off chip DDR2 and NAND memory are shown in the table below. 

Table 1: DDR2 and NAND Memory Ranges 

Interface Memory Type Address Range Size 

DDR0 DDR2 0x8000 0000 0x2000 0000 

DDR1 DDR2 0xC000 0000 0x2000 0000 

GPMC 

NAND 

GPMC_CS0, 

see NAND controller 

information 

2 Gigabyte 

1-5


1.5 Boot Switch Settings 

The EVM uses 9 positions of a 10 position DIP switch (SW3) to configure the 

operational state of the processor when it is released from reset and determine the 

source for processor booting. Five (5) positions indicate the boot mode and four (4) 

positions determine the memory configuration. By default as shipped the switches are 

configured to SD Card boot. The tables below shows the boot mode sources and their 

respective switch positions. 

Table 2: Memory Boot Load Order 

BTMODE[4] (Position5)= 1 

MEMORY BOOTING PREFERRED 

First Second Third Fourth 

BTMODE[3:0] 

Switch 

Position[4:1] 

XIP UART EMAC SD 0 0 0 0 

XIPWAIT UART EMAC SD 0 0 0 1 

NAND NANDI2C SPI UART 0 0 1 0 

NAND NANDI2C SD UART 0 0 1 1 

NAND NANDI2C SPI EMAC 0 1 0 0 

NANDI2C SD EMAC UART 0 1 0 1 

SPI SD UART EMAC 0 1 1 0 

SD SPI UART EMAC 0 1 1 1 

SPI SD PCIE_32 Reserved 1 0 0 0 


Reserved Reserved Reserved Reserved 1 0 1 0 





GP Fast 

External 

Boot 

EMAC UART PCIE_32 1 1 1 1 



Table 3: Peripheral Boot Load Order 


PERIPHERAL BOOTING PREFERRED 


BTMODE[3:0] 

Switch 

Position[4:1] 


UART XIPWAIT SD SPI 0 0 0 1 

UART SPI NAND NANDI2C 0 0 1 0 

UART SPI XIP SD 0 0 1 1 

EMAC SPI NAND NANDI2C 0 1 0 0 



EMAC SD SPI XIP 0 1 1 1 

PCIE_32 Reserved Reserved Reserved 1 0 0 0 







GP Fast 

External 

Boot 

UART EMAC PCIE_64 1 1 1 1 

The photo below shows the switch settings for SD card boot. 

Figure 1-4, Boot Load Switch Settings 

1-7


An additional switch (SW4) enables the chip select for on board NAND and SPI 

Flash. This switch allows for daughter cards to override on board configurations. 

This switch must disable the on board NAND and SPI when SD card boot is selected. 

The photo below shows the default switch settings for SW4. 

Figure 1-5, SW4, NAND/SPI Select Switch Settings 

1.6 Power Supply 

The EVM operates from a single +12V external power supply connected to the main 

power input (J1), a 2.5 MM. barrel-type plug. On the EVM, the +12V input is converted 

into core voltage (1 volt constant and 1 volt variable [AVS]), +1.5V, +1.8V, +3.3V and 

+5V using Texas Instruments controllers and regulators. The +3.3V supply is used for 

the CPU's I/O buffers. 


Chapter 2 

Board Components 

This chapter describes the operation of the major board components on 

the C6A816x/AM389x EVM. 

Topic 

Page 

2.1 EMIF-A Interfaces 2-2 

2.1.1 EMIF-B SDRAM Memory Interface 2-2 

2.1.2 Memory Card Interface 2-2 

2.1.3 UART Interface 2-2 

2.1.4 USB Interface 2-2 

2.1.5 HDMI Interface 2-2 

2.1.6 Video DAC 2-2 

2.1.7 PCIe 2-3 

2.2 AIC3106 Interface 2-3 

2.3 Ethernet Interface 2-4 

2.4 I 2 C0, I 2 C1 Interfaces 2-4 

2.5 SPI Flash 2-5 

2.6 Power Monitoring 2-5 

2.7 Daughter Card Interface 2-5 

2-1


2.1 GPMC Interface 

A separate 16 bit EMIF with multiple chip enables divide up the internal address space 

and allow for asynchronous memory accesses on the EVM. The EVM uses this 

interface for memory interfaces to the daughter card and on board NAND Flash. 

2.1.1 DDR Memory Interfaces 

The C6A816x/AM389x device incorporates two dedicated 32 bit wide DDR memory 

interfaces. The EVM incorporates a dual DIMM connector that supports 1 Gigabyte of 

memory for program, data, and video storage. The internal memory controller uses a 

PLL to control the memory timing. Memory refresh is handled automatically by the 

C6A816x/AM389x internal controller. 

2.1.2 Memory Card Interface 

The EVM supports SD/MMC media card interfaces. This interface is directly supported 

via an on chip peripheral. 

2.1.3 UART Interface 

The internal UART2 on the C6A816x/AM389x device is driven to connector P10. The 

UART’s interface is routed to the RS-232 line drivers prior to being brought out to a 

DB-9 connector. 

2.1.4 USB Interface 

The C6A816x/AM389x incorporates two on chip USB controllers. The two interfaces 

are brought out to dual host A type connector, J13. 

2.1.5 HDMI Interface 

The C6A816x/AM389x has an on chip HDMI peripheral which supports up to 

1080p @ 60 Hz. resolution. This interface is a direct interface to an HDMI connector, 

P6. 

2.1.6 Video DAC 

The EVM supports composite, S-video, Scart, and component output via internal video 

DACs. The interfaces are buffered via THS7360 and THS7375 video DACs to 

connectors J2, J9, J4, J5, J6, and J7. 



2.1.7 PCIe 

The EVM provides a PCIe connector and supports 2 lanes of transmit and receive 

interfaces. 

2.2 AIC3106 Interface 

The EVM incorporates a Texas Instruments TLV320AIC3106 stereo codec for input and 

output of audio signals. The codec samples analog signals on the microphone or line 

inputs and converts them into digital data so it can be processed by the DSP. When the 

DSP is finished with the data it uses the codec to convert the samples back into analog 

signals on the line output so the user can hear the output. 

The codec communicates using two serial channels, one to control the codec’s internal 

configuration registers and one to send and receive digital audio samples. The I 2 C bus 

is used as the AIC3106’s control channel. The control channel is generally only used 

when configuring the codec, it is typically idle when audio data is being transmitted, 

McASP1 is used as the bi-directional data channel. All audio data flows through the 

data channel. Many data formats are supported based on the three variables of 

sample width, clock signal source and serial data format. The EVM examples generally 

use a 16-bit sample width with the codec in master mode so it generates the frame 

sync and bit clocks at the correct sample rate without effort on the DSP side. 

The codec is clocked via a 24.576 Mhz oscillator. The internal sample rate generator 

subdivides the default system clock to generate common audio frequencies. The 

sample rate is set by a codec register. The figure below shows the codec interface on 

the C6A816x/AM389x EVM. 

SCL 

SDA 

I 2 C 

Control 

I 2 C Format 

SCL 

SDA 

AIC3106 Codec 

Control Registers 

MIC IN 

LINE IN 

McASP 

AXR[0] 

AXR[5] 

ACLKR 

ACLKX 

AFSR 

AFSX 

Digital 

DOUT 

DIN 

BCLK 

WCLK 

ADC 

DAC 

Analog 

MIC IN 

LINE IN 

LINE OUT 

HP OUT 

LINE OUT 

HP OUT 

Figure 2-1, C6A816x/AM389x EVM CODEC INTERFACE 

2-3


2.3 Ethernet Interface 

The C6A816x/AM389x incorporates two ethernet MAC’s that support 10/100/1000 Mbit 

interfaces. Ethernet 0 is interfaced to an external Phy and brought out to an RJ-45 

standard ethernet connector, J10. The ethernet address is stored on chip within the 

CPU. 

The RJ-45 jack has 2 LEDs integrated into the connector. The LEDs are green and 

yellow and provide link and transmit status from the ethernet controller. 

2.4 I 2 C0, I 2 C1 Interfaces 

The I 2 C0 and I 2 C1 bus on the C6A816x/AM389x is ideal for interfacing to the control 

registers of many devices. On the C6A816x/AM389x EVM the I 2 C0 bus is used to 

configure the Codec, I 2 C ROM, and bit addressable latch. The format of the bus is 

shown in the figure below. 

Start Slave Address W 

ACK Sub Address ACK-S Data ACK-S Stop 

Write Sequence 

Start Slave Address R Data STOP 

Read Sequence 

Figure 2-3, I 2 C Bus Format 

The addresses of the on board peripherals are shown in the tables below. 

Table 1: I 2 C0 Address Map 

Device Address R/W Function 

TLV320AIC3106 0x18 R/W CODEC 

PCF8575 0x20 R/W Bit I/O 

MSP430 0x25 R/W Power Monitor 

I 2 C EEPROM 0x50 R/W I 2 C EEPROM 

Table 2: I 2 C1 Address Map 

Device Address R/W Function 

PCF8575 0x20 R/W Bit I/O 



2.5 SPI Flash 

The EVM has a 32 megabit SPI Flash that can be used for booting and/or storage. Note 

that the switch S2 enables the SPI chip select and must be set properly when using the 

device. 

2.6 Power Monitoring 

The EVM uses an MSP430 CPU connected to multiple INA2201DCN I 2 C power 

monitors to monitor the voltage and currents on the EVM. The MSP430 outputs this 

information in real time via its dedicated RS-232 port, P7. 

2.7 Daughter Card Interfaces 

The EVM provides expansion connectors that can be used to accept plug-in daughter 

cards. The daughter card allows users to build on their EVM platform to extend its 

capabilities and provide customer and application specific I/O. The expansion 

connectors are interfaces which include McASP, and serial I/O expansion. The EMIF-A 

signals are brought out as LCD, peripheral, or EMIF signals. 

The daughter card connectors used on the EVM are shown in the table below. 

Reference 

Designator 

Table 3: Daughter Card Connectors 

Part Numbers Used 

On EVM 

Manufacturer 

J16 QSH-030-01-L-D-A-K Samtec 





2-5


One of the compatible mating daughter card connectors used to interface to the EVM 

are shown in the table below (other heights are available). 

Reference 

Designator 

Table 4: Mating Daughter Card Connectors 

Mating 

connector 

Manufacturer 

XJ16 QTH-030-02-L-D-A-K Samtec 






Chapter 3 

Physical Description 

This chapter describes the physical layout of the C6A816x/AM389x EVM 

and its interfaces. 

Topic 

Page 

3.1 Board Layout 3-3 

3.2 Connectors 3-5 

3.2.1 J1, 12V Power In 3-6 

3.2.2 J2, HD15 Connector 3-6 

3.2.3 J3, F Type Video Connector 3-7 

3.2.4 J4, Composite Video Out 3-7 

3.2.5 J5, Component Video, RCA Jack - Green 3-7 

3.2.6 J6, Component Video, RCA Jack - Blue 3-8 

3.2.7 J7, Component Video, RCA Jack - Red 3-8 

3.2.8 J8, Disk Drive Power Connector 3-8 

3.2.9 J9, SCART21 Connector 3-9 

3.2.10 J10, Ethernet Connector 3-10 

3.2.11 J11, SATA Header 3-10 

3.2.12 J12, SATA Header 3-11 

3.2.13 J13-1/13-2, USB-A Connectors 3-12 

3.2.14 J14, MSP430 Programming Header 3-13 

3.2.15 J15, CTI JTAG Interface 3-14 

3.2.16 J16, VLYNQ/Transport Connector 3-15 

3.2.17 J17, Video/Transport Connector 3-16 

3.2.18 J18, GPMC Expansion Connector 3-18 

3.2.19 J19, MCASP/XXX Expansion 3-20 

3.2.20 J20, Serial Expansion Connector 3-22 

3-1


Topic 

Page 

3.2.21 P1, S-Video Connector 3-23 

3.2.22 P2, Headphone Out 3-24 

3.2.23 P3, Line Out 3-24 

3.2.24 P4, Line In 3-25 

3.2.25 P5, Mic In 3-25 

3.2.26 P6, HDMI Connector 3-26 

3.2.27 P7, DB9 Connector 3-27 

3.2.28 P8, PCIe Interface 3-28 

3.2.29 P9, SD/MMC Connector 3-29 

3.2.30 P10, DB9 Connector 3-30 

3.2.31 P11, Fan Connector 3-31 

3.3 LEDs 3-32 

3.4 Switches 3-32 

3.4.1 SW1, On/Off Power Switch 3-32 

3.4.2 SW2, User Readable Switches 3-33 

3.4.3 SW3, Boot Mode/Configuration Switch 3-34 

3.4.4 SW4, On Board Memory Enable Switch 3-37 

3.4.5 SW5, PCI/WDOG Reset Enable Switch 3-37 

3.4.5 SW6, Reset Switch 3-38 

3.5 Infra-red Receiver 3-38 

3.6 Test Points 3-39 



3.1 Board Layout 

The C6A816x/AM389x EVM is a 12.5 x 8.4 inch (317 x 213 mm.) six (6) layer printed 

circuit board which is powered by an external +5 volt only power supply. Figure 3-1 

shows the layout of the top side of the C6A816x/AM389x EVM. 

J8 

SW1 

DS1 

P11 

J1 

J3 

SW2 

DS2-5 

J2 

P7 

P9 

J14 

P10 

SW4 

IR 

SW3 

J7 

J6 

J5 

J4 

P1 

P6 

P5 

P4 

P3 

P2 

J10 

J9 

J15 

J11 

J12 

SW5 

P8 

J13 

SW6 

Figure 3-1, C6A816x/AM389x EVM, Interfaces Top Side 

3-3


Figure 3-2 shows the layout of the bottom side of the C6A816x/AM389x EVM. 

J19 

J17 

J16 

J18 

J20 

Figure 3-2, C6A816x/AM389x EVM, Interfaces Bottom Side 



3.2 Connectors 

The EVM has numerous connectors and option jumpers to control and provide 

connections to various peripherals. These connectors and jumpers are described in the 

following sections. 

Table 1: Connectors 

Connector 

Size 

Board 

Side 

Schematic 

Page 

Function 

J1 2 Top 51 12V Power In 

J2 15 Top 37 HD15 Connector 

J3 2 Top 37 F Type Video Connector 

J4 2 Top 37 Composite Video 

J5 2 Top 37 RCA Jack - Green 

J6 2 Top 37 RCA Jack - Blue 

J7 2 Top 37 RCA Jack - Red 

J8 9 Top 51 Drive Input Power Connector 

J9 21 Top 38 SCART21 Connector 

J10 14 Top 35 Ethernet Output Connector 

J11 9 Top 12 SATA Header 

J12 9 Top 12 SATA Header 

J13-1 6 Top 25 USB-A Connector 

J13-2 6 Top 25 USB-A Connector 

J14 2 x 7 Top 45 MSP430 Programming Header 

J15 20 Top 14 CTI JTAG Interface 

J16 2 x 32 Bottom 40 VLYNQ/Transport Connector 

J17 2 x 64 Bottom 39 Video/Transport Connector 

J18 2 x 64 Bottom 41 GPMC Expansion Connector 

J19 2 x 64 Bottom 43 MCASP/XXX Expansion 

J20 2 x 32 Bottom 42 Serial I/O Expansion Connector 

P1 7 Top 37 S-video Connector 

P2 4 Top 36 Headphone Out 

P3 4 Top 36 Line Out 

P4 4 Top 36 Line In 

P5 4 Top 36 Mic In 

P6 23 Top 11 HDMI 

P7 11 Top 45 DB9 Connector 

P8 2 x 32 Top 23 PCIe Interface 

P9 28 Top 30 SD/MMC Connector 

P10 11 Top 28 DB9 Connector 

P11 3 Top 51 Fan Connector 

3-5


3.2.1 J1, 12V Power In 

Connector J1 is the input power connector. This connector brings in +12 volts to the 

EVM. This is a 2.5mm. jack. The inside of the jack is tied to through a fuse to 

EVM_12V. The other side is tied to ground and LED DS1. The figure below shows this 

connector as viewed from the card edge. 

J1 

+12V 

Ground 

PC Board 

Front View 

Figure 3-3, J1, +12 Volt Input Connector 

3.2.2 J2, HD15 Connector 

Connector J2 is a 15 pin header that allows a high definition video device to be plugged 

into the EVM. The signals on this connector are shown in the table below. 

Table 2: J2, HD15 Connector 

Pins 

Signal 

1 U4, Pin 12, SF3_OUT 



4 NC 

5 Ground 

6 Ground 

7 Ground 

8 Ground 

9 NC 

10 Ground 

11 NC 

12 NC 

13 NC 

14 NC 

15 NC 



3.2.3 J3, F Type Video Connector 

Connector J3 provides an RF output (RFOUT) from the processor, U31, Pin AU21. 

3.2.4 J4, Composite Video Out 

J4 is an RCA jack used as a video output from the THS7360 driver. Do NOT plug into 

this connector with the power on. The figure below shows this connector as viewed 

from the card edge. 

Pin 2, Shield (ground) 

Pin 1, Signal output 

Figure 3-4, J4, Composite Video Out 

Table 3: J4, Composite Video Out, RCA Jack 

Pin # 

Signal Name 

1 THS7360, Pin 20, SD1_OUT 

2 GND 

3.2.5 J5, Component Video, RCA Jack - Green 

J5 is an RCA jack used to provide the Green component video output from the 

THS7360 driver, U4, pin 14, SF1_OUT. The pinout on this connector is shown in the 

figure below. 


Pin 1, Signal output (green) 

Figure 3-5, J5, Component Video Out - Green 

WARNING: Do NOT plug into this connector with the power on. 

3-7


3.2.6 J6, Component Video, RCA Jack - Blue 

J6 is an RCA jack used to provide the Blue component video output from the 


figure below. 


Pin 1, Signal output (blue) 

Figure 3-6, J6, Component Video Out - Blue 


3.2.7 J7, Component Video, RCA Jack - Red 

J7 is an RCA jack used to provide the Red component video output from the 


figure below. 


Pin 1, Signal output (red) 

Figure 3-7, J7, Component Video Out - Red 


3.2.8 J8, Disk Drive Power Connector 

Connector J8 provides power for a hard disk drive. This is the standard connector used 

on a personal computer. The signals on this connector are shown in the table below. 

Table 4: J8, Disk Driver Power Connector 

Pin # 

Signal Name 

1 EVM_12V, +12 volts 

2,3 Ground 

4 EVM_5V0, +5 volts 

6,7,8,9 No connect 



3.2.9 J9, SCART21 Connector 

Connector J9 is a SCART21 video output connector. The signals on this connector 

are shown in the table below. 

Table 5: J9, SCART21 Connector 

Pin # Signal Name Pin # Signal Name 

1 SCART_AUDIO_OUT_R 

3 SCART_AUDIO_OUT_L 

5 Ground 

7 U8, Pin 13, CH2_OUT 

9 Ground 

11 U8, Pin 14, CH1_OUT 

13 Ground 

15 U8, Pin 12, CH3_OUT 

17 Ground 

19 SCART_COMPOSITE 

21 Ground 

2 No connect 

4 Ground 

6 No connect 

8 No connect 

10 No connect 

12 No connect 

14 Ground 

16 U8, Pin 11, CH4_OUT 

18 No connect 

20 No connect 

3-9


3.2.10 J10, Ethernet Connector 

Connector J10 is an Ethernet connector that uses differential signals. The signals 

on this connector are shown below. 

Table 6: J10, Ethernet Connector 

Pins 

Signal 

1 Ground 

2 PHY_VDD_25V 

3 TRD[3]P 

4 TRD[3]N 

5 TRD[2]P 

6 TRD[2]N 

7 TRD[1]P 

8 TRD[1]N 

9 TRD[0]P 

10 TRD[0]N 

11 Earth Ground 

12 Earth Ground 

D1 ENET_LED_LINK 

D2 

Ground 

D3 ENET_LED_RX 

D4 EVM_3V3 

3.2.11 J11, SATA Header 

J11 is a 9 pin SATA disk interface header. There are 2 pair of differential signals to 

interface to the processor, U31. This signals on this connector are shown below. 

Pins 

Table 7: J11, SATA Header 

Signal 

1 Ground 

2 CON.SATA_TXP1, U31, Pin V33 

3 CON.SATA_TXN1, U31, Pin U33 

4 Ground 

5 CON.SATA_RXN1, U31, Pin V35 

6 CON.SATA_RXP1, U31, Pin W35 

7 Ground 

8 No connect 

9 No connect 



3.2.12 J12, SATA Header 

J12 is a 9 pin SATA disk interface header. There are 2 pair of differential signals to 

interface to the processor, U31. This signals on this connector are shown below. 

Pins 

Table 8: J12, SATA Header 

Signal 

1 Ground 

2 CON.SATA_TXP0, U31, Pin T32 

3 CON.SATA_TXN0, U31, Pin T31 

4 Ground 

5 CON.SATA_RXN0, U31, Pin V37 

6 CON.SATA_RXP0, U31, Pin V36 

7 Ground 

8 No connect 

9 No connect 

3-11


3.2.13 J13-1/13-2, USB-A Connectors 

Connector J13-1, J13-2 are stacked USB connectors. The J13-1 connector is the lower 

connector in the stacked pair. The signals on each of these connectors are shown in 

the tables below. 

Table 9: J13-1, USB-A Connector 

Pin Name 

MHX1/MH1 

VBUS/A1 

D-/A2 

D+/A3 

GND/A4 

MH2 

Signal 

SHIELD USB0 

USB0_VBUS_CONN 

USB0_DM 

USB0_DP 

Ground 

SHIELD USB0 

Table 10: J13-2, USB-A Connector 

Pin Name 

MHX1/MH3 

VBUS/B1 

D-/B2 

D+/B3 

GND/B4 

MHX2/MH4 

Signal 

SHIELD USB1 


USB1_DM 

USB1_DP 

Ground 

SHIELD USB1 



3.2.14 J14, MSP430 Programming Header 

J14 is a 2 x 7 double row header used to program the MSP430 microcontroller, U38. 

This header is only to be used at the factory. The layout of this header is shown in the 

figure below. 

1 

2 

MSP430 JTAG 

Header Dimensions 

Pin-to-Pin spacing, 0.100 in. (X,Y) 

Pin width, 0.025-in. square post 

Pin length, 0.235-in. nominal 

J14 

Figure 3-8, J14, MSP430 Programming Header 

The signals on the pins of this connector are shown bin the table below. 

Table 11: J14, MSP430 Programming Header 

Pin # Signal Pin # Signal 

1 430_TDO/TDI 2 No connect 

3 No connect 4 EVM_3V3 

5 No connect 6 No connect 

7 MSP430_TCK 8 No connect 

9 Ground 10 No connect 



3-13


3.2.15 J15, CTI JTAG Interface 

Connector J15 is a compact 20 pin TI JTAG header. The signals on the pins of this 

connector are shown in the table below. 

Table 12: J15, CTI JTAG Interface 

Pin # Signal Pin # Signal 

1 TMS 2 TRSTn 

3 TDI 4 Ground 

5 EVM_3V3 6 No connect (key) 

7 TDO 8 Ground 

9 RTCK 10 Ground 

11 TCK 12 Ground 

13 EMU0 14 EMU1 

15 EMU_RSTn 16 Ground 

17 EMU2 18 EMU3 

19 EMU4 20 Ground 



3.2.16 J16, VLYNQ/Transport Connector 

Connector J16 is the VLYNQ/Transport interface located on the bottom side of the 

board. The signals on this connector are shown in the table below. 

Table 13: J16, VLYNQ/Transport Connector 

Pin Signal Pin Signal 

2 TSI3_PACVAL 1 TSI6_PACERR 

4 Ground 3 Ground 

6 TSI4_DCLK 5 TSI2_PACERR 

8 TSI3_DATA 7 TSI0_PACVAL 


12 TSI2_DCLK 11 TSI2_PACVAL 

14 TSI2_DATA 13 TSI0_PACERR 


18 TSI6_BYTSTRT 17 TSI0_DCLK 

20 TSI6_PACVAL 19 TSO0_DCLK 


24 TSI4_PACERR 23 TSI0_BYTSTRT 

26 TSI4_BYTSTRT 25 TSO0_DATA 


30 TSI3_PACERR 29 TSO0_BYTSTRT 

32 VLYNQ_RXD1 31 TSO0_PACERR 


36 VLYNQ_TXD1 35 VLYNQ_SCRUN 

38 TSO1_PACERR 37 TSO0_PACVAL 


42 VLYNQ_TXD3 41 VLYNQ_TXD2 

44 VLYNQ_RXD2 43 VLYNQ_CLOCK 


48 TSI4_PACVAL 47 TSI1_PACERR 

50 VLYNQ_RXD3 49 TSI3_DCLK 


54 VLYNQ_TXD0 53 VLYNQ_RXD0 






3-15


3.2.17 J17, Video/Transport Connector 

Connector J17 is the Video/Transport interface located on the bottom side of the 

board. This connector is in two sections. The signals on each section of this connector 

are shown in the tables below. 

Table 14: J17, Video/Transport Connector, Section 1 


2 VIN0_D0 1 No connect 


6 VIN0_D2 5 No connect 

8 VIN0_D9 7 VIN0_CLK1 


12 VOUT_G_Y_YC2 11 VIN0_D1 

14 VOUT_G_Y_YC6 13 VIN0_D4 


18 VOUT_R_CR4 17 VIN0_D11 

20 VIN0_D6 19 VIN0_D5 


24 VIN0_D8 23 VIN0_D12 

26 VIN0_D3 25 VIN0_D10 


30 VIN0_D7 29 VIN0_D14 

32 VOUT0_G_Y_YC4 31 VIN0_D13 


36 VOUT0_B_CB_C8 35 VIN0_D15 

38 VOUT0_G_Y_YC5 37 VOUT0_CLK 


42 VOUT0_B_CB_C6 41 VOUT0_G_Y_YC8 

44 VOUT0_B_CB_C5 43 VOUT0_G_Y_YC7 


48 EVM_12V 47 EVM_3V3 

50 EVM_12V 49 EVM_3V3 


54 EVM_12V 53 EVM_5V0 

56 EVM_12V 55 EVM_5V0 


60 VOUT0_B_CB_C3 59 VOUT0_B_CB_C9 



Table 15: J17, Video/Transport Connector, Section 2 


62 VOUT0_B_CB_C7 61 VOUT0_R_CR2 


66 VOUT0_G_Y_YC3 65 VOUT0_R_CR6 

68 VOUT0_G_Y_YC9 67 VOUT0_R_CR5 


72 VIN0_CLK0 71 VOUT0_R_CR9 

74 VOUT0_B_CB_C4 73 TSI5_BYTSTRT 


78 VOUT0_B_CB_C2 77 TSI5_PACERR 

80 VOUT0_R_CR3 79 TSI7_PACERR 


84 TSI5_DATA 83 TSO1_DATA 

86 TSI5_PACVAL 85 TSI7_PACVAL 


90 TSI1_PACVAL 89 TSO1_PACVAL 

92 TSI7_DATA 91 TSO1_DCLK 


96 TSI5_DCLK 95 TSI6_DATA 

98 VOUT0_R_CR7 97 TSI3_BYTSTRT 


102 VOUT0_R_CR8 101 TSI2_BYTSTRT 

104 TSI7_BYTSTRT 103 TSI4_DATA 


108 TSI1_BYTSTRT 107 TSI0_DATA 

110 TSI7_DCLK 109 TSI6_DCLK 


114 TSI1_DCLK 113 MSP430_SCL 

116 TSI1_DATA 115 MSP430_SDA 


120 TSO1_BYTSTRT 119 No connect 





3-17


3.2.18 J18, GPMC Expansion Connector 

Connector J18 is the GPMC expansion connector located on the bottom side of the 

board. This connector is in two sections. The signals on each section of this connector 

are shown in the tables below. 

Table 16: J18, GPMC Expansion Connector, Section 1 


2 MSP430_SCL 1 No connect 


6 MSP430_SDA 5 GPMC_CS3 

8 No connect 7 GPMC_CS0 





18 GPMC_CS4 17 GPMC_WEN 

20 GPMC_A8 19 GPMC_CS5 


24 GPMC_A7 23 GPMC_OEN_REN 

26 GPMC_A3 25 GPMC_BE1N 


30 GPMC_A2 29 GPMC_A5 




38 GPMC_DIR 37 GPMC_A10 


42 GPMC_WAIT 41 GPMC_A11 

44 GPMC_WPN 43 GPMC_D0 


48 EVM_12V 47 EVM_3V3 

50 EVM_12V 49 EVM_3V3 


54 EVM_12V 53 EVM_5V0 

56 EVM_12V 55 EVM_5V0 


60 GPMC_A6 59 GPMC_D2 



Table 17: J18, GPMC Expansion Connector, Section 2 


62 GPMC_BE0N_CLE 61 GPMC_D5 


66 GPMC_D4 65 GPMC_D7 




74 GPMC_A27 73 GPMC_D11 


78 GPMC_ADVN_ALE 77 GPMC_D10 

80 GPMC_D6 79 GPMC_CLK 



86 GPMC_D13 85 POWER_GOOD2 








102 GPMC_D14 101 SPI_CS0 

104 No connect 103 SPI_CLK 


108 SPI_MOSI 107 SPI_CS3 

110 SOI_MISO 109 SPI_CS1 


114 UART0_RXD 113 UART1_RXD 

116 UART0_RTSN 115 UART1_TXD 


120 UART0_TXD 119 UART2_RXD 





3-19


3.2.19 J19, MCASP/XXX Expansion 

Connector J19 is the MCASP/XXX expansion connector located on the bottom side of 

the board. This connector is in two sections. The signals on each section of this 

connector are shown in the tables below. 

Table 18: J19, MCASP/XXX Expansion Connector, Section 1 


2 IIC1_SDA 1 PM_I2C_SCL 


6 IIC0_SCL 5 PM_I2C_SDA 

8 IIC0_SDA 7 EXP_MCA2_AXR0 


12 IIC0_SCL 11 EXP_MCA2_AMUTE 

14 No connect 13 EXP_MCA2_AXR1 


18 MCA0_AMUTE 17 EXP_MCA2_ACLKHX 

20 MCA0_AXR3 19 EXP_MCA2_ACLKX 


24 MCA0_AXR2 23 EXP_MCA2_AFSR 

26 MCA1_AMUTE 25 EXP_MCA2_AFSX 


30 MCA0_ACLKHX 29 EXP_MCA2_AHCLKR 

32 MCA0_AFSR 31 EXP_MCA2_ACLKR 


36 MCA0_ACLKX 35 MCA1_AXR1 

38 MCA0_AFSX 37 MCA1_AXR0 


42 MCA1_AFSX 41 MTSO_DATA1 

44 MCA0_AXR1 43 MTSI_DATA5 


48 EVM_12V 47 EVM_3V3 

50 EVM_12V 49 EVM_3V3 


54 EVM_12V 53 EVM_5V0 

56 EVM_12V 55 EVM_5V0 


60 MTSI_DATA7 59 MCA1_ACLKHX 



Table 19: J19, MCASP/XXX Expansion Connector, Section 2 


62 MCA0_AXR5 61 MDIO_MDIO 


66 MCA0_AXR4 65 MDIO_MDCLK 

68 MCA0_AXR0 67 MCA1_ACLKX 


72 MCA1_ACLKR 71 MTSI_DCLK 

74 MCA1_AHCLKR 73 MTSI_DATA0 


78 MCA1_AFSR 77 MTSI_DATA2 

80 MTSO_DATA0 79 MTSI_DATA1 



86 MTCL_SDI 85 MTSI_DATA3 



92 MCARD_MDET 91 MTSI_BYTSTRT 


96 MTCL_SCTL 95 MTSO_DCLK 

98 MCARD_CD2 97 MTSO_DATA2 


102 MCARD_CD1 101 MTSO_DATA3 

104 MCA0_ACLKR 103 MTSO_DATA5 


108 MCA0_AHCLKR 107 MTSO_DATA4 

110 MCARD_VS1 109 MCTL_SCLK 


114 MTCL_SDO 113 MTSO_BYTSTRT 

116 MCARD_VCCEN 115 MCARD_VPPEN 


120 MCARD_VS2 119 MCARD_RESET 





3-21


3.2.20 J20, Serial Expansion Connector 

Connector J20 is the serial expansion connector located on the bottom side of the 

board. The signals on this connector are shown in the table below. 

Table 20: J20, Serial Expansion Connector 


2 UART0_CTSN 1 UART1_RTSN 


6 UART0_DTRN 5 UART2_TXD 

8 UART0_DCDN 7 SC0_RST 


12 UART0_DSRN 11 SC1_RST 

14 UART0_RIN 13 SC1_DET 


18 SPI_SCS2 17 TIM6_OUT 

20 UART1_CTSN 19 SC1_VPPEN 


24 SC0_VPPEN 23 TIM7_OUT 

26 SC0_VCCEN 25 SC1_VCCEN 


30 SC1_CLK 29 CLK_OUT 

32 SC0_C4 31 GP0_IO5 


36 UART2_RTSN 35 TIM4_OUT 

38 UART2_CTSN 37 No connect 


42 SC0_DET 41 No connect 

44 RSTOUTn 43 No connect 


48 SC0_CLK 47 No connect 

50 SC1_C4 49 GP0_IO7 


54 SC0_DATA 53 GP0_IO4 

56 SC1_DATA 55 EXP_WARM_RESET 


60 GP0_IO6 59 TIM5_OUT 





3.2.21 P1, S-Video Connector 

Connector P1 is a four pin mini din S-video connector which interfaces to the THS7360. 

This connector brings out a video signal (LUMA). Do NOT plug into this connector with 

the power on. The figure below shows this connector as viewed from the card edge. 

Pin 3 

Pin 1 

Pin 4 

Pin 2 

Figure 3-9, P1, Front View, Mini Din Connector 

Table 21: P1, S-Video Connector 

Pin # 

Signal Name 

1,2,5,6 Ground 

3 S-VIDEO_LUMA, U4, Pin 19, SD2_OUT 

4 U4, Pin 18, SD3_OUT 

7 No connect 

3-23


3.2.22 P2, Headphone Out 

The P2 connector is a 3.5 mm. stereo headphone output from the TVL320AIC3106 on 

the EVM. The signals on the mating plug are shown in the figure below The signals 

present on this connector are defined in the following table. 

Ground (sleeve) 

Right Line Out (ring) 

Left Line Out (tip) 

Figure 3-10, P2, Headphone Out Stereo Jack 

Table 22: P2, Headphone Out Interface 

Pin # 

AIC3106 Signal 

1(sleeve) GND_AC 

2(ring U2, Pin 18, HPLOUT 

3(tip) U2, Pin 23,HPROUT 

4 NC 

3.2.23 P3, Line Out 

The audio line out connector P3, is a stereo output. The output connector is a 3.5 mm 

stereo jack. The signals on the mating plug are shown in the figure below. 


Right Line Out (ring) 

Left Line Out (tip) 

Figure 3-11, P3, Audio Line Out Stereo Jack 

Table 23: P3, Audio Line Out Stereo Jack 

Pin # 


1 (sleeve) GND_AC 

2 (ring) U2, Pin 29, LEFT_LO+ 

3 (tip) U2, Pin 31, RIGHT_LO+ 

4 (sleeve) NC 



3.2.24 P4, Line In 

Connector P4 is an stereo audio line input. The input connector is a 3.5 mm stereo jack. 

The signals on the mating plug are shown in the figure below. 


Left Line In (ring) 

Right Line In (tip) 

Figure 3-12, P4, Audio Line In Stereo Jack 

Table 24: P4, Line In Interface 

Pin # 



2 (ring) U2, Pin 3, LINE1L+ 

3 (tip) U2, Pin 5, LINE1R+ 


3.2.25 P5, Mic In 

Connector P5 is an stereo microphone line input. The input connector is a 3.5 mm 

stereo jack. The signals on the mating plug are shown in the figure below. 


Left Line In (ring) 

Right Line In (tip) 

Figure 3-13, P5, Microphone In Stereo Jack 

Table 25: P5, Microphone In Interface 

Pin # 



2 (ring) U2, Pin 11,14, MIC3L/MIC3R 

3 (tip) U2, Pin 11/14, MIC3L/MIC3R 


3-25


3.2.26 P6, HDMI Connector 

Connector P6 provides an HDMI interface for the processor card. The signals on this 

connector are shown below. 

Pins 

Table 26: P6, HDMI Connector 

Signal 

1 HDMI_TMDSOP2 

2 Ground 

3 HDMI_TMDSDN2 

4 HDMI_TMDSDP1 

5 Ground 


7 HDMI_TMDSDP0 

8 Ground 


10 HDMI_TMDSCLKP 

11 Ground 

12 HDMI_TMDSCLKN 

13 U1, Pin 23,CE_REMOTE_OUT 

14 No connect 

15 U1, Pin 22, DDC_CLK_OUT 

16 U1, Pin 21, DDC_DAT_OUT 

17 Ground 

18 U1, Pin 38, 5V_OUT 

19 U1, Pin 20, HOTPLUG_DET_OUT 

MTG1 

Ground 

MTG2 

Ground 

MTG3 

Ground 

MTG4 

Ground 



3.2.27 P7, DB9 Connector 

The P7 connector is a 9 pin male D-connector which provides a UART interface to the 

EVM. This connector interfaces to the MAX 3221 RS-232 line driver (U39) and is 

located on the top side of the board. A view of the connector from the card edge is 

shown in the figure below. The signals present on this connector are defined in the 

following table. 

5 

4 

3 

2 

1 

9 

8 

Figure 3-14, P7, DB9 Male Connector 

7 

The pin numbers and their corresponding signals are shown in the table below. This 

corresponds to a standard dual row to DB-9 connector interface used on personal 

computers. 

Table 27: P7, RS-232 Pinout 

6 

Pin # 

Signal Name 

1 NC 

2 R_IN, Rx Data 

3 T_OUT, Tx Data 

4 NC 

5 GND 

6 NC 

7 Pin 8 

8 Pin 7 

9 NC 

3-27


3.2.28 P8, PCIe Interface 

Connector P8 provides a PCIe interface on the processors board. The signals on this 

connector are shown in the table below. 

Table 28: P8, PCIe Interface 


B1 EVM_12V A1 Pin B31 

B2 EVM_12V A2 EVM_12V 

B3 EVM_12V A3 EVM_12V 

B4 Ground A4 Ground 

B5 No connect A5 Ground 

B6 No connect A6 PCI_3V3 

B7 Ground A7 No connect 

B8 PCI_3V3 A8 PCI_3V3 

B9 Ground A9 PCI_3V3 

B10 No connect A10 PCI_3V3 

B11 No connect A11 U43, Pin 4, U41, Pin 2,EVM_3V3 

KEY 


B13 Ground A14 REFCLKp 

B14 CON.PCIE_TXP0 A14 REFCLKn 

B15 CON.PCIE_TXN0 A15 Ground 

B16 Ground A16 CON.PCIE_RXP0 

B17 No connect A17 CON.PCIE_RXN0 

B18 Ground A18 Ground 

B19 CON.PCIE_TXP1 A19 No connect 

B20 CON.PCIE_TXN1 A20 Ground 

B21 Ground A21 CON.PCIE_RXP1 

B22 Ground A22 CON.PCIE_RXN1 








B30 No connect A30 No connect 

B31 Pin A1 A31 Ground 




3.2.29 P9, SD/MMC Connector 

The P92 MMC/SD connector is located on the top side of the board and is used to 

provide an interface to the following: MMC+, SD, and MMC. The pinout for the P9 

connector is shown in the table below. 

Table 29: P9, MMC/SD Connector 

Pin # 

Signal 

1 MMC_DAT3 

2 MMC_CMD 

3 Ground 

4 U66, Pin 2,3 

5 MMC_CLK 

6 Ground 

7 MMC_DAT0 

8 MMC_DAT1 

9 MMC_DAT2 

10 No connect 

11 No connect 

12 No connect 

13 No connect 

14 MMC_SD_WP 

15 MMC_SD_CD 

16 No connect 

17 No connect 

18 Ground 

19 No connect 

20 No connect 

21 Ground 

22 No connect 

23 No connect 

24 No connect 

25 No connect 

26 No connect 

27 Ground 

28 Ground 

3-29


3.2.30 P10, DB9 Connector 

The P10 connector is a 9 pin male D-connector which provides a UART interface to the 

EVM. This connector interfaces to the MAX 3221 RS-232 line driver (U57) and is 

located on the top side of the board. A view of the connector from the card edge is 

shown in the figure below. The signals present on this connector are defined in the 

following table. 

5 

4 

3 

2 

1 

9 

8 

Figure 3-15, P10, DB9 Male Connector 

7 

The pin numbers and their corresponding signals are shown in the table below. This 

corresponds to a standard dual row to DB-9 connector interface used on personal 

computers. 

Table 30: P10, RS-232 Pinout 

6 

Pin # 

Signal Name 

1 NC 

2 R_IN, Rx Data 

3 T_OUT, Tx Data 

4 NC 

5 GND 

6 NC 

7 Pin 8 

8 Pin 7 

9 NC 



3.2.31 P11, Fan Connector 

Connector P11 provides power for a 12 volt DC fan. The layout of the connector is 

shown in the figure below. 

P11 

FAN POWER 

1 

Header Dimensions 

Pin-to-Pin spacing, 0.100 in. (X,Y) 

Pin width, 0.025-in. square post 

Pin length, 0.235-in. nominal 

Figure 3-16, P11, Fan Connector 

The signals on the pins of this connector are shown bin the table below. 

Table 31: P11, Fan Connector 

Pin # 

Signal 

1 Ground 

2 EVM_12V 

3 No connect 

3-31


3.3 LEDs 

The EVM has six (6) LEDs which are located on the top side of the board. 

Information regarding the LEDs are shown in the table below. 

Table 32: LEDs 

LED # Use Color 

DS1 Power LED Green 

DS2 USER_LED1 Green 




3.4 Switches 

The EVM has six (6) switches. The function of these switches are shown in the table 

below. 

Table 33: Switches 

Switch 

Schematic 

Page 

Function 

Type 

SW1 51 On/Off Power Switch Toggle 

SW2 27 User Readable Switches 4 Position DIP 

SW3 6 Boot Load Select 10 Position DIP 

SW4 6 On Board Memory Enable 2 Position DIP 

SW5 23 PCI/WDOG Reset Enable 2 Position DIP 

SW6 51 Reset Switch Push Button/Momentary 

3.4.1 SW1, On/Off Power Switch 

Switch SW1 is an on/off toggle switch that allows +12 volts from the J1 connector to be 

applied to the board. 



3.4.2 SW2, User Readable Switches 

Switch SW2 is a 4 position DIP switch that is read via the I 2 C bus. A board image of the 

switch is shown in the figure below. 

SW2 

USER 

1 2 3 4 

Figure 3-17, SW2, User Readable 4 Position DIP Switch 

The table below shows what signal each position appears on. 

Table 34: SW3, User Readable 4 Position DIP Switch 

Position Signal 

1 - 8 USER_SW1 




3-33


3.4.3 SW3, Boot Mode/Configuration Switch 

Switch SW3 is a 10 position DIP switch. Five (5) of the positions are used for selecting 

the boot load option. Four (4) positions are used for system configuration. The 

remaining switch position is a spare unused position. An image of the switch is shown 

in the figure below in the as shipped configuration. 

SW3 

BOOT/CFG 

SPARE 

CS0WAIT 

Raised 

CS0BW 

Actuator 

CS0MUX1 

CS0MUX0 

BTM4 

BTM3 

BTM2 

BTM1 

BTM0 

1 

Figure 3-18, SW3, Boot Mode/Configuration Switch 

The boot mode options are described in the table below. 

Table 35: SW3, Boot Mode Select DIP Switch 

Position Label Pins Signal 

1 BTM0 1-20 BTMODE0 







The tables below shows the boot mode sources and their respective switch positions. 

Table 36: Memory Boot Load Order 


MEMORY BOOTING PREFERRED 


BTMODE[3:0] 

Switch 

Position[4:1] 

XIP UART EMAC SD 0 0 0 0 

XIPWAIT UART EMAC SD 0 0 0 1 

NAND NANDI2C SPI UART 0 0 1 0 

NAND NANDI2C SD UART 0 0 1 1 

NAND NANDI2C SPI EMAC 0 1 0 0 

NANDI2C SD EMAC UART 0 1 0 1 

SPI SD UART EMAC 0 1 1 0 

SD SPI UART EMAC 0 1 1 1 








GP Fast 

External 

Boot 

EMAC UART PCIE_32 

1 1 1 1 

3-35


Table 37: Peripheral Boot Load Order 


PERIPHERAL BOOTING PREFERRED 


BTMODE[3:0] 

Switch 

Position[4:1] 


UART XIPWAIT SD SPI 0 0 0 1 

UART SPI NAND NANDI2C 0 0 1 0 

UART SPI XIP SD 0 0 1 1 

EMAC SPI NAND NANDI2C 0 1 0 0 



EMAC SD SPI XIP 0 1 1 1 








GP Fast 

External 

Boot 

UART EMAC PCIE_64 

1 1 1 1 

The configuration options are described in the table below. 

Table 38: SW3, Configuration Switches 

Position Label Pins Signal State Function 

6 CS0MUX0 5-16 CS0MUX0 

7 CS0MUX1 6-15 CS0MUX1 

8 CS0BW 7-14 CS0BW 

9 CS0WAIT 8-13 CS0WAIT 

Open 

Closed 

Open 

Closed 

Open 

Closed 

Open 

Closed 



3.4.4 SW4, On Board Memory Enable Switch 

Switch SW4 is a 2 position DIP switch which allows the user to select which on board 

memory device to boot from. Only one device should be enabled at any given time. A 

board image of the switch is shown in the figure below in the as shipped configuration. 

NAND/SPI-ON 

Raised 

Actuator 

SPI 

NAND 

SW4 

Figure 3-19, SW4, On Board Memory Enable Switch 


Table 39: SW4, On Board Memory Enable Switch 

Position Signal 

1 - 4 NAND_BOOTn 

2 - 3 SPI_BOOTn 

3.4.5 SW5, PCI/WDOG Reset Enable Switch 

Switch SW5 is a 2 position DIP switch which allows the user to select which on board 

memory device to boot from. Only one device should be enabled at any given time. A 

board image of the switch is shown in the figure below. 

Pin 1 

PCIe RST 

SW5 

OPTON 

WDOG EN 

Figure 3-20, SW5, On Board Memory Enable Switch 


Table 40: SW5, On Board Memory Enable Switch 

Position 

Signal 

1 - 4 OPT_SW1, PCI reset mode IN or OUT 

2 - 3 OPT_SW2, WDOG reset enabled 

3-37


3.4.6 SW6, Reset Switch 

Switch SW2 is a push button reset switch that will RESET the board. 

3.5 Infra-red Receiver 

The EVM has an infra-red receiver, U61. This is used to receive signals from a 

television remote control handset. The logic for this is shown on page 29 of the 

schematics. 



3.6 Test Points 

The EVM has 25 test points which appear on the top of the board. The following figure 

identifies the position of each test point. The next table lists each test point and the 

signal appearing on that test point. 

TP2 

TP5 

TP9 

TP11 

TP12 

TP14 

TP13 

TP18 

TP19 

TP23 

TP8 

TP7 

TP20 

TP10 

TP17 

TP25 

TP6 

TP16 

TP4 

TP3 

TP1 

TP26 

TP21 

TP22 

TP15 

Figure 3-21, C6A816x/AM389x EVM, Test Points 

3-39


Table 41: C6A816x/AM389x EVM Test Points 

Test 

Point # 

Schematic 

Page 

Signal 

TP1 51 Ground 

TP2 51 EVM_12V 

TP3 36 U2, Pin 27, MONO_LO+ 

TP4 36 U2, Pin 28, MONO_LO- 

TP5 51 Ground 

TP6 51 Ground 

TP7 50 U5, Pin 1, RESET, EVM_3V3 

TP8 50 U10, Pin 7, SW, 1V8_DIGITAL 

TP9 50 U10, Pin 5, PGn, EVM_5V0 

TP10 50 U10, Pin 14, VDLO1, 1V8_ANALOG 

TP11 50 U10, Pin 17, VLDO2, 0V9_A 

TP12 49 EVM_1V0_AVS 

TP13 47 Ground 

TP14 49 EVM_1V0_AVS 

TP15 13 U30, Pin 23, OSCOUT 




TP19 47 U33, Pin 14, PWRGRD 

TP20 47 U33, Pin 9, SS/TR 


TP22 24 U56, Pin 9, SS/TR 





Appendix A 

Schematics 

This appendix contains the schematics for the C6A816x/AM389x EVM. 

A-1

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


REV DESCRIPTION 

DATE APPROVED 

SEE LAST PAGE OF SCHEMATIC FOR REVISION 

08/01/2010 RRP 

D D 

SCHEMATIC CONTENTS 

01) TITLE PAGE 

02) NETRA MCASP'S 

03) NETRA SERIAL I/O 

04) NETRA ETHERNET INTERFACE 

05) NETRA USB INTERFACE 

06) NETRA GPMC 

07) NETRA DDR0 EMIF 

08) NETRA DDR1 EMIF 

09) NETRA ANALOG VIDEO 

10) NETRA VIDEO PORT/TRANSPORT LAYER 

11) NETRA HDMI INTERFACE 

12) NETRA SATA/PCIe 

13) SERDES CLOCKS 

14) NETRA JTAG 

15) NETRA CLOCKS 

16) NETRA POWER 1 



19) NETRA GROUND PINS 

20) DECOUPLING CAPS 

21) DDR3/DDR2 EMIFA BANK DIMM 

22) DDR3/DDR2 EMIFB BANK DIMM 

23) PCIe INTERFACE CONNECTOR 

24) PCIe 3V3 POWER 

25) USB HOST INTERFACE CONNECTORS 

26) I2C EEPROM 

27) I2C EXPANDER 

28) RS232 INTERFACE 

29) IR RECIEVER 

30) SD/MMC CONNECTOR 

31) SPI EEPROM 

32) NAND FLASH 

33) ETHERNET PHY 

34) ETHERNET POWER 

35) ETHERNET CONNECTOR 

36) AUDIO CODEC TLV320AIC3106 

37) ANALOG VIDEO OUT 

38) SCART ANALOG VIDEO OUT 

39) VIDEO PORT/TRANSPORT EXPANSION CONNECTOR 

40) VLYNQ/TRANSPORT EXPANSION CONNECTOR 

41) GPMC EXPANSION CONNECTOR 

42) SERIAL I/O EXPANSION CONNECTOR 

43) MCASP EXPANSION CONNECTOR 

44) POWER MONITORS 

45) POWER MONITOR CPU 

46) POWER 5V0,3V3,1V0_CONN 

47) POWER 1V5/1V8 MEMORY 

48) POWER 1V5 ALT 

49) POWER 1V0 AVS CORE 

50) POWER 0V9/1V8_ANALOG/1V8_DIGITAL 

51) POWER IN 

52) POWER SEQUENCING 

53) REVISIONS 

POWER DOMAINS 

EVM_12V0 12 VOLT INPUT FROM EXTERNAL POWER SUPPLY 

EVM_5V0 5.0 VOLT OUTPUT FROM TPS65232 


EVM_1V8_A 1.8 VOLT ANALOG LDO OUTPUT FROM TPS65001 

EVM_1V8_D 1.8 VOLT DIGITAL OUTPUT FROM TPS65001 

EVM_1V5 1.5 /1.8 VOLT OUTPUT FROM TPS54620 

ALT_EVM_1V5 1.5 /1.8 VOLT OUTPUT FOR NON-MEMORY INTERFACE 

EVM_1V0_AVS 1.0 VOLT CORE FROM TPS40041 

EVM_1V0_CONN 1.0 VOLT NON-CORE FROM TPS65232 


BASE BINARY 

C C 

BASE BINARY 

I2C0 ADDRESS MAP 

HEX BASE ( RJ ) DEVICE 

PCF8575 

I2C1 ADDRESS MAP 

I2C EEPROM 

TLV320AIC3106 

RJ - Right Justified 

HEX BASE ( RJ ) DEVICE 

PCF8575 

B B 

SHEET 

27 

31 

36 

SHEET 

27 

RJ - Right Justified 

REVISION STATUS OF SHEETS 

REV 

B B 

SH 

51 

52 53 

REV 

A A A 

A A 

SH 41 42 43 44 45 46 47 48 49 50 

REV 

A A 

A A A A 

DWN 

DATE 

SH 31 32 33 34 35 36 37 38 39 40 

R.R.P. 02/15/2010 

A CHK 

DATE 

SPECTRUM DIGITAL INCORPORATED 

A 

REV 

A A A A A A A A 

T.W.K. 02/15/2010 

ENGR 

DATE 

SH 21 22 23 24 25 26 27 28 29 30 

R.R.P. 02/15/2010 

Title: 

NETRA EVM with DIMM MEMORY 

ENGR-MGR 

DATE 

REV 

A A A A 

R.R.P. 02/15/2010 

Page Contents: TITLE PAGE 

QA 

DATE 

SH 11 12 13 14 15 16 17 18 19 20 

C.M.D. 02/15/2010 

Revision: 

MFG 

DATE 

Size: B 

DWG NO 513832-0001 

C 

REV 

A A A A A A A A NEXT ASSY 

USED ON 

R.R.P. 02/15/2010 

RLSE 

DATE 

Date: Wednesday, November 03, 2010 Sheet 1 o f 52 

SH 

3 5 

10 APPLICATION 

R.R.P. 02/15/2010 

A 

A 

A 

A 

A 

C 

1 

A 

A 

A 

2 

A 

A 

A 

4 

A 

A 

A 

A 

6 

A 

7 

A 

8 

A 

9 

A 

B 

A-2 C6A816x/AM389x EVM Technical Reference

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


U31-9 

43 

43 

43 

MCARD_CD1 

MCARD_CD2 

MCARD_MDET 

MCARD_CD1 

MCARD_CD2 

MCARD_MDET 

AL28 

AL29 

AM29 

RSV34 

RSV35 

RSV33 

MCA[0]_AHCLKX AH31 

MCA[0]_AHCLKR AJ27 

MCA[0]_ACLKR AK28 

MCA[0]_ACLKX AH30 

MCA[0]_AFSR AG29 

MCA0_AFSX AJ31 

MCA[0]_AMUTE AJ35 

CPU.MCA0_AHCLKX R414 1 2 22 MCA0_AHCLKX 

CPU.MCA0_AHCLKR R396 1 2 22 MCA0_AHCLKR 

CPU.MCA0_ACLKR R397 1 2 22 MCA0_ACLKR 

CPU.MCA0_ACLKX R411 1 2 22 MCA0_ACLKX 

MCA0_AFSR 

MCA0_AFSX 

MCA0_AMUTE 

MCA0_AHCLKX 43 

MCA0_AHCLKR 43 

MCA0_ACLKR 43 

MCA0_ACLKX 43 

MCA0_AFSR 43 

MCA0_AFSX 43 

MCA0_AMUTE 43 

D D 

43 MCARD_RESET 

MCARD_RESET 

AT28 

MCA0_AXR0 

RSV40 

MCA[0]_AXR[0] 

AK37 

MCA0_AXR0 43 

MCA0_AXR1 

MCA0_AXR1 43 

MCARD_VCCEN 

MCA[0]_AXR[1] 

AJ32 

43 MCARD_VCCEN 

AR29 

MCA0_AXR2 

RSV38 

MCA[0]_AXR[2]/MCB_FSX AJ33 

MCA0_AXR2 43 

MCA0_AXR3 

MCA0_AXR3 43 

43 MCARD_VPPEN 

MCARD_VPPEN 

MCA[0]_AXR[3]/MCB_FSR AJ34 

AT29 

MCA0_AXR4 

RSV39 

MCA[0]_AXR[4]/MCB_DX AJ36 

MCA0_AXR4 43 

MCA0_AXR5 

MCA[0]_AXR[5]/MCB_DR AJ37 

MCA0_AXR5 43 

43 MCARD_VS1 

MCARD_VS1 

AN29 

RSV36 

43 MCARD_VS2 

MCARD_VS2 

AP29 

RSV37 

CPU.MCA1_AHCLKX R150 22 MCA1_AHCLKX 

MCA[1]_AHCLKX AM37 

1 2 

MCA1_AHCLKX 43 

CPU.MCA1_AHCLKR R152 22 MCA1_AHCLKR 

MCA[1]_AHCLKR AL37 

1 2 

MCA1_AHCLKR 43 

CPU.MCA1_ACLKR R155 22 MCA1_ACLKR 

MCA1_ACLKR 43 

MCTL_SCLK 

MCA[1]_ACLKR AK36 

1 2 

43 MCTL_SCLK 

AT30 

CPU.MCA1_ACLKX R144 1 2 22 MCA1_ACLKX 

EMAC[1]_TXCLK 

MCA[1]_ACLKX AL36 

MCA1_ACLKX 43 

MCA1_AFSR 

MCA1_AFSR 43 

43 MCTL_SCTL 

MCTL_SCTL 

MCA[1]_AFSR AK35 

AR30 

MCA1_AFSX 

EMAC[1]_COL 

MCA[1]_AFSX AK34 

MCA1_AFSX 43 

MCA1_AMUTE 

MCA1_AMUTE 43 

43 MCTL_SDI 

MCTL_SDI 

MCA[1]_AMUTE AK33 

AN31 

EMAC[1]_CRS 

43 MCTL_SDO 

MCTL_SDO 

AN30 

MCA1_AXR0 

MCTL_SDO 

MCA[1]_AXR[0] 

AL33 

MCA1_AXR0 43 

MCA1_AXR1 

MCA[1]_AXR[1] 

AK32 

MCA1_AXR1 43 

C C 

MTSI_BYTSTRT 

EVM_3V3 

43 MTSI_BYTSTRT 

AT33 

EMAC[1]_RXDV 

43 MTSI_DCLK 

MTSI_DCLK 

AT37 

EMAC[1]_RXCLK 

CPU.MCA2_ACLKHX 

MCA2_ACLKHX 

MTSI_DATA0 

MCA[2]_AHCLKX/MCB_CLKR AN36 

R138 1 2 22 

43 MTSI_DATA0 

AT36 

CPU.MCA2_AHCLKR R401 22 EXP_MCA2_AHCLKR 

EXP_MCA2_AHCLKR 43 

C515 

MTSI_DATA1 

EMAC[1]_RXD[0] 

MCA[2]_AHCLKR/MCB_CLKS AM34 

1 2 

43 MTSI_DATA1 

AT35 

CPU.MCA2_ACLKR R405 22 EXP_MCA2_ACLKR 

EXP_MCA2_ACLKR 43 

.1uF 

43 MTSI_DATA2 

MTSI_DATA2 

EMAC[1]_RXD[1] MCA[2]_ACLKR/MCB_CLKR/MCB_DR AL34 

1 2 

AU36 

CPU.MCA2_ACLKX R141 22 MCA2_ACLKX 

c402-25 

43 MTSI_DATA3 

MTSI_DATA3 


MCA[2]_ACLKX/MCB_CLKX AM36 

1 2 

AT34 

EXP_MCA2_AFSR 

EXP_MCA2_AFSR 43 

U63 

43 MTSI_DATA4 

MTSI_DATA4 

EMAC[1]_RXD[3] MCA[2]_AFSR/MCB_CLKX/MCB_FSR AM35 

AU35 

MCA2_AFSX 

43 MTSI_DATA5 

MTSI_DATA5 

EMAC[1]_RXD[4] MCA[2]_AFSX/MCB_CLKS/MCB_FSX AN35 

EXP_MCA2_AMUTE 

Vcc 

24 

AR33 

EXP_MCA2_AMUTE 43 

43 MTSI_DATA6 

MTSI_DATA6 


MCA[2]_AMUTE AP36 

AU34 

MCA2_AFSX 

3 

B_AIC_WCLK 36 

43 MTSI_DATA7 

MTSI_DATA7 


MCA2_ACLKX 

1A1 1B1 

2 

AP32 


4 

B_AIC_BCLK 36 

MCA2_AXR0 

MCA2_ACLKHX 

1A2 1B2 

5 

MCA[2]_AXR[0] 

AR36 

7 

B_AIC_MCLK 36 

MCA2_AXR1 

MCA2_AXR1 

1A3 1B3 

6 

MCA[2]_AXR[1]/MCB_DX AR37 

8 

B_AIC_DOUT 36 

MCA2_AXR0 

1A4 1B4 

9 

11 

B_AIC_DIN 36 

MTSO_BYTSTRT 

1A5 1B5 

10 

43 MTSO_BYTSTRT 

AU30 

EMAC[1]_TXEN 

1 

MTSO_DCLK 

1OE 

43 MTSO_DCLK 

AU33 

EMAC[1]_GMTCLK 

14 

EXP_MCA2_AXR0 

MTSO_DATA0 

2A1 2B1 

15 

EXP_MCA2_AXR0 43 

EXP_MCA2_AXR1 

43 MTSO_DATA0 

AP31 

MTSO_DATA1 

EMAC[1]_TXD[0] 

17 

2A2 2B2 

16 


EXP_MCA2_ACLKHX 

43 MTSO_DATA1 

AR32 

B MTSO_DATA2 


18 

2A3 2B3 

19 

EXP_MCA2_ACLKHX 43 

EXP_MCA2_ACLKX 

43 MTSO_DATA2 

AT32 

EXP_MCA2_ACLKX 43 B 

MTSO_DATA3 


21 

2A4 2B4 

20 

EXP_MCA2_AFSX 

43 MTSO_DATA3 

AU32 

22 

EXP_MCA2_AFSX 43 

MTSO_DATA4 


2A5 2B5 

23 

43 MTSO_DATA4 

AU31 

MTSO_DATA5 


43 MTSO_DATA5 

AT31 

13 

MTSO_DATA6 


2OE GND 12 

43 MTSO_DATA6 

AP30 

MTSO_DATA7 


SN74CBTLV3384PW 

43 MTSO_DATA7 

AM30 


NETRA_3 

EVM_3V3 

C497 

.1uF 

MCLK: MCA2_AHCLKX (drive this clock into McASP) 

BCLK: MCA2_ACLKX (McASP will drive this into the AIC) 

27 AIC_EXPANSION 

1 

WCLK: MCA2A_FSX (McASP will drive this into the AIC) 

4 

DIN: MCA2_AXR[0] 

2 

DOUT: MCA2_AXR1[1] 

U62 

A Drive the MCLK into McASP1 Tx. 

SN74LVC1G00DCKRG4 


A 

McASP generates the Tx bit and frame clocks. 

Configure McASP such that the Rx section 

Title: 


operates off of the Tx section clocks. 

Page Contents: NETRA McASP/MCARD 

EVM_3V3 

3 

5 

EVM_3V3 3,5,6,11,13,14,15,18,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,38,39,41,43,44,45,46,48,49,50,51 

Size: B 

DWG NO 

513832-0001 

Revision: 

A 

Date: 

Sheet o f Wednesday, November 03, 2010 2 52 

A-3

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


U31-4 

CLKOUT R185 CPU.CLKOUT 

42 CLKOUT 

1 2 22 

F1 

CLKOUT 

MMC_POW 

SD_POW/GPMC_A[14]/GP1[0] 

U4 

MMC_POW 30 

CPU.MMC_CLK R168 22 MMC_CLK 

TIM4_OUT 

SD_CLK/GPMC_A[13]/GP1[1] 

U2 

1 2 

MMC_CLK 30 

42 TIM4_OUT 

H33 

TIM4_OUT/GP0[28] 

CPU.MMC_CMD 

MMC_CMD 

MMC_CMD 30 

TIM5_OUT 

SD_CMD/GPMC_A[21]/GP1[2] 

U3 

1 2 

D 42 TIM5_OUT 

H34 

TIM5_OUT/GP0[29] 

D 

42 

42 

TIM6_OUT 

TIM7_OUT 

TIM6_OUT 

TIM7_OUT 

H1 

G1 

TIM6_OUT/GPMC_A[24]/GP0[30] 

TIM7_OUT/GPMC_A[12]/GP0[31] 

SD_DAT[0]/GPMC_A[20]/GP1[3] 

SD_DAT[1]_SDIRQ/GPMC_A[19]/GP1[4] 

SD_DAT[2]_SDRW/GPMC_A[18]/GP1[5] 

SD_DAT[3]/GPMC_A[17]/GP1[6] 

U1 

T1 

T2 

T13 

MMC_DAT0 

MMC_DAT1 

MMC_DAT2 

MMC_DAT3 

MMC_DAT0 30 

MMC_DAT1 30 

MMC_DAT2 30 

MMC_DAT3 30 

42 

SC0_VCCEN 

42 

SC0_C4 

SC0_VCCEN 

SC0_C4 

J4 

J5 

GPMC_A[23]/GP1[14] 

GP1[13] 

SD_SDCD/GPMC_A[16]/GP1[7] 

SD_SDWP/GPMC_A[15]/GP1[8] 

R5 

R13 

MMC_SD_WP 

MMC_SD_CD 

MMC_SD_WP 30 

MMC_SD_CD 30 

42 

42 

SC0_CLK 

SC0_DATA 

SC0_CLK 

SC0_DATA 

J6 

J7 

GPMC_A[26]/GP1[11] 

GPMC_A[25]/GP1[12] 

UART0_TXD N8 

UART0_TXD 

UART0_TXD 41 

42 

SC0_DET 

SC0_DET 

K8 

GPMC_A[27]/GP1[9 

UART0_RXD N10 

UART0_RXD 

UART0_RXD 41 

42 

SC0_RST 

SC0_RST 

K2 

GPMC_A[22]/GP1[10] 

UART0_RIN/GPMC_A[17]/GPMC_A[22]/GP1[19] 

N3 

UART0_RIN 

UART0_RIN 42 

42 

SC0_VPPEN 

SC0_VPPEN 

J3 

GPMC_A[24]/GP1[15] 

UART0_RTSn/GP1[27] 

N9 

UART0_RTSN 

UART0_RTSN 41 

UART0_DTRn/GPMC_A[20]/GPMC_A[12]/GP1[16] 

N6 

UART0_DTRN 

UART0_DTRN 42 

42 SC1_VCCEN 

SC1_VCCEN 

H3 

UART0_DSRN 

GPMC_A[21]/GP0[26] 

UART0_DSRn/GPMC_A[19]/GPMC_A[24]/GP1[17] 

N4 

UART0_DSRN 42 

C C 

42 SC1_C4 

SC1_C4 

H4 

UART0_CTSN 

GP0[25] 

UART0_CTSn/GP1[28] 

N7 

UART0_CTSN 42 

42 

42 

SC1_CLK 

SC1_DATA 

SC1_CLK 

SC1_DATA 

H5 

H6 

GPMC_A[14]/GP0[23] 

GPMC_A[13]/GP0[24] 

UART0_DCDn/GPMC_A[18]/GPMC_A[23]/GP1[18] 

N5 

UART0_DCDN 

UART0_DCDN 42 

42 

42 

42 

SC1_DET 

SC1_RST 

SC1_VPPEN 

SC1_DET 

SC1_RST 

SC1_VPPEN 

J2 

J1 

H2 

GPMC_A[16]/GP0[21] 

GPMC_A[15]/GP0[22] 

GPMC_A[12]/GP0[27] 

UART1_TXD/GPMC_A[25]/GPMC_A[19] 

UART1_RXD/GPMC_A[26]/GPMC_A[20] 

UART1_RTSn/GPMC_A[14]/GPMC_A[18]/GP1[25] 

N2 

N1 

M2 

UART1_TXD 

UART1_RXD 

UART1_RTSN 

UART1_TXD 41 

UART1_RXD 29,41 

UART1_RTSN 42 

31,41 

SPI_MISO 

SPI_MISO 

N11 

SPI_D[0] 

UART1_CTSn/GPMC_A[13]/GPMC_A[17]/GP1[26] 

L3 

UART1_CTSN 

UART1_CTSN 42 

31,41 

31,41 

SPI_MOSI 

SPI_SCLK 

SPI_MOSI 

SPI_SCLK R171 1 2 22 CPU.SPI_SCLK 

P13 

R2 

SPI_D[1] 

SPI_SCLK 

UART2_TXD L2 

UART2_RXD M1 

UART2_TXD 

UART2_RXD 

UART2_TXD 28,42 


R427 22 

SPI_CS0 

UART2_RTSN 

31,41 SPI_CS0 

R1 

SPI_CS1 

SPI_SCS[0]n 

UART2_RTSn/GPMC_A[15]/GPMC_A[26]/GP1[23] 

L9 

UART2_RTSN 42 

41 SPI_CS1 

P2 

SPI_CS2 

SPI_SCS[1]n/GPMC_A[23] 

UART2_CTSN 

42 SPI_CS2 

P3 

UART2_CTSN 42 

B SPI_CS3 

SPI_SCS[2]n/GPMC_A[22] 

UART2_CTSn/GPMC_A[16]/GPMC_A[25]/GP1[24] 

K7 

41 SPI_CS3 

P1 

B 

SPI_SCS[3]n/GPMC_[A21]/GP1[22] 

EVM_3V3 EVM_3V3 

I2C[0]_SCL 

N32 

I2C[0]_SDA N33 

I2C[1]_SDA N35 

I2C[1]_SCL 

N34 

R20 

2.2K 

R14 

2.2K 

R289 

2.2K 

R279 

2.2K 

NETRA_3 

IIC0_SCL 26,27,36,43,45 

IIC0_SDA 26,27,36,43,45 

IIC1_SCL 27,43 

IIC1_SDA 27,43 

A SPECTRUM DIGITAL INCORPORATED 

A 

EVM_3V3 

Title: 


EVM_3V3 2,5,6,11,13,14,15,18,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,38,39,41,43,44,45,46,48,49,50,51 

Page Contents: 

NETRA SERIAL I/O 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 



5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


D D 

U31-10 

CPU_GMII0_GMTCLK 

GMII0_GMTCLK 

EMAC[0]_GMTCLK AC37 

1 2 

GMII0_GMTCLK 33 









AD37 

AD36 

AC36 

AD35 

AC35 

AD25 

AC25 

AE36 

GMII0_RXD0 

GMII0_RXD1 

GMII0_RXD2 

GMII0_RXD3 

GMII0_RXD4 

GMII0_RXD5 

GMII0_RXD6 

GMII0_RXD7 

GMII0_RXD0 33 

GMII0_RXD1 33 

GMII0_RXD2 33 

GMII0_RXD3 33 

GMII0_RXD4 33 

GMII0_RXD5 33 

GMII0_RXD6 33 

GMII0_RXD7 33 

EMAC[0]_RXCLK AE37 

GMII0_RCLK 

GMII0_RCLK 33 

EMAC[0]_RXDV AE35 

EMAC[0]_RXER AE34 

EMAC[0]_COL 

AB25 

EMAC[0]_CRS AA25 

GMII0_RXDV 

GMII0_RXER 

GMII0_COL 

GMII0_CRS 

GMII0_RXDV 33 

GMII0_RXER 33 

GMII0_COL 33 

GMII0_CRS 33 

R165 22 

C C 

AE33 

CPU_GMII0_TXD0 

1 2 

R417 22 GMII0_TXD0 


GMII0_TXD0 33 

AE32 


1 2 R419 22 

GMII0_TXD1 


GMII0_TXD1 33 

AE31 


1 2 R420 22 

GMII0_TXD2 


GMII0_TXD2 33 

AE30 


1 2 R421 22 GMII0_TXD3 


GMII0_TXD3 33 

AG28 


1 2 R423 22 

GMII0_TXD4 


GMII0_TXD4 33 

AF36 


1 2 R160 22 

GMII0_TXD5 


GMII0_TXD5 33 

AG36 


1 2 R158 22 

GMII0_TXD6 


GMII0_TXD6 33 

AG35 


1 2 R416 22 

GMII0_TXD7 


GMII0_TXD7 33 

EMAC[0]_TXEN AG37 

CPU_GMII0_TXEN 

R159 1 2 22 

GMII0_TXEN 

GMII0_TXEN 33 

EMAC[0]_TXCLK AF37 

CPU_GMII0_TCLK 

R161 1 2 22 

GMII0_TCLK 

GMII0_TCLK 33 

MDIO_MCLK AH37 

MDIO_MDCLK 

MDIO_MDCLK 33,43 

MDIO_MDIO 

MDIO_MDIO 33,43 

NETRA_3 

B B 


A 

Title: 



NETRA ETHERNET 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


A-5

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


EVM_3V3 

E5 

NFM21PC474R1C3D 

3 

1 

3.3 VOLT 

C611 

0.1uF 

C610 

0.001uF 

C609 

0.01uF 

CPU_VDDA33USB 

C612 

1uF 

DIFFERENTIAL PAIR 

90 OHM DIFFERENTIAL 

IMPEDANCE 

SHORT AND STRAIGHT AS 

POSSIBLE, 

MINIMUM NUMBER OF VIAS 

D D 

U31-12 

EVM_1V8_D 

E6 


1 3 

1.8 VOLT 

T29 

USB0_VBUS 

VDD_USB0_3P3 

VDD_USB0_VBUS N36 

USB0_VBUS 25 

R29 

VDD_USB0_3P3 

USBB0_DRV_VBUS 

USB0_DRVVBUS P35 

USBB0_DRV_VBUS 25 

USB0_DP 

USB0_DP P37 

USB0_DP 25 

USB0_DM 

USB0_DM 25 

CPU_VDDA18USB 

USB0_DN P36 

R25 

VDD_USB0_1P8 

2 

2 

C640 C639 

C642 C641 

0.1uF 0.001uF 

USB0_R1 

N37 R172 10K 1% 

1uF 1uF 

T28 

RSV5 

VDD_USB1_VBUS T36 

USB1_VBUS 

USB1_VBUS 25 


USB1_DRVVBUS R35 

USBB1_DRV_VBUS 25 

C T30 

VDD_USB1_3P3 

C 

R30 

VDD_USB1_3P3 

USB1_DP 

USB1_DP R37 

USB1_DP 25 

USB1_DM 

USB1_DN R36 

USB1_DM 25 

T25 

VDD_USB1_1P8 

USB1_R1 

T37 

R169 10K 1% 

T27 

RSV6 

N27 

VDD_USB_0P9 

NETRA_3 



IMPEDANCE 


POSSIBLE, 


B B 

EVM_0V9 

0.9 VOLT 

C634 

0.1uF 

EVM_1V8_D 

EVM_1V8_D 15,16,44,47,50 


A 

EVM_3V3 

Title: 


EVM_3V3 2,3,6,11,13,14,15,18,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,38,39,41,43,44,45,46,48,49,50,51 

Page Contents: NETRA USB 

EVM_0V9 

Revision: 

EVM_0V9 44,50 

Size: B 

DWG NO 513832-0001 

A 

Date: 



5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


EVM_3V3 

SW3 

BTMODE0 BTMODE0 

20 1 

1K 

R352 


19 2 

1K 

R349 


18 3 

1K 

R340 


17 4 

1K 

R336 

D BTMODE4 BTMODE4 

D 

16 5 

1K 

R331 

CS0MUX0 CS0MUX0 

15 6 

1K 

R327 

CS0MUX1 CS0MUX1 

14 7 

1K 

R322 

CS0BW CS0BW 

13 8 

1K 

R316 

U31-5 

CS0WAIT CS0WAIT 

12 9 

1K 

R308 

11 10 10 

1K 

R304 

32,41 GPMC_WAIT 

AE8 

GPMC_WAIT 

GPMC_A[0]/GP0[8] 

AE6 

GPMC_A0 41 

DIP_SWITCH-10 

GPMC_A[1]/GP0[9]/BTMODE[0] 

AE5 

GPMC_A1 41 

32,41 GPMC_D0 

AC1 

GPMC_D[0] 


AE4 

GPMC_A2 41 

32,41 GPMC_D1 

AA4 

GPMC_D[1] 


AE3 

GPMC_A3 41 

32,41 GPMC_D2 

AB2 

GPMC_D[2] 

32,41 GPMC_D3 

AA3 

GPMC_D[3] 

32,41 GPMC_D4 

Y3 

GPMC_D[4] 


AE1 

GPMC_A4 41 

32,41 GPMC_D5 

AA2 

GPMC_D[5] 


AE2 

GPMC_A5 41 

32,41 GPMC_D6 

Y10 

GPMC_D[6] 

GPMC_A[6]/GP0[14]/CS0MUX[0] 

AD8 

GPMC_A6 41 

32,41 GPMC_D7 

Y2 

GPMC_D[7] 

GPMC_A[7]/GP0[15]/CS0MUX[1] 

AD3 

GPMC_A7 41 

GPMC_A[8]/GP0[16]/CS0BW AD4 

GPMC_A8 41 

32,41 GPMC_D8 

W4 

GPMC_D[8] 

GPMC_A[9]/GP0[17]/CS0WAIT 

AD2 

GPMC_A9 41 

32,41 GPMC_D9 

Y1 

GPMC_D[9] 

GPMC_A[10]/GP0[18] 

AD1 

GPMC_A10 41 

32,41 GPMC_D10 

W3 

GPMC_D[10] 

GPMC_A[11]/GP0[19] 

AC2 

GPMC_A11 41 

32,41 GPMC_D11 

W1 

GPMC_D[11] 

C 32,41 GPMC_D12 

W2 

GPMC_D[12] 

GPMC_A[27]/GP0[20] 

AC5 

GPMC_A27 41 

GPMC_A1 INTERNAL PULL UP 

C 

32,41 GPMC_D13 

V10 

GPMC_D[13] 

32,41 GPMC_D14 

V3 

GPMC_D[14] 

GPMC_CLK/GP1[29] 

V1 

GPMC_CLK 41 

32,41 GPMC_D15 

V2 

GPMC_D[15] 

GPMC_A2 INTERNAL PULL DOWN 

GPMC_ADV_ALE AE10 

GPMC_ADVN_ALE 32,41 

GPMC_BE0_CLE AE11 

GPMC_BE0N_CLE 32,41 GPMC_A3 INTERNAL PULL DOWN 

GPMC_BE1N 41 


GPMC_DIR 41 

GPMC_WEN 32,41 GPMC_A5 INTERNAL PULL DOWN 

GPMC_OE_REn 

AF2 

GPMC_OEN_REN 32,41 


GPMC_WPn 

AE9 

GPMC_WPN 32,41 

GPMC_CS[0]n 

AH7 

GPMC_ CS0 32,41 GPMC_A7 INTERNAL PULL DOWN 

GPMC_CS[1]n 

AH1 

GPMC_ CS1 41 

GPMC_CS[2]n 

AH2 

GPMC_ CS2 41 

GPMC_CS[3]n 

AG9 

GPMC_ CS3 41 


EVM_3V3 

GPMC_CS[4]n/GP1[21] 

AG3 

GPMC_ CS4 41 

GPMC_CS[5]n/GPMC_A[12] 

AG1 

GPMC_ CS5 41 

B GPMC_A9 INTERNAL PULL DOWN 

B 

40 VLYNQ_SCRUN 

AK2 

RSV43 


A 

EVM_3V3 

Title: 


EVM_3V3 2,3,5,11,13,14,15,18,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,38,39,41,43,44,45,46,48,49,50,51 


NETRA GPMC/VLYNQ INTERFACE 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


1 

2 

3 

4 

5 

6 

7 

8 

9 

10K 

10K 

3K 

10K 

3K 

10K 

3K 

10K 

10K 

3K 

R305 

R309 

R317 

R323 

R328 

R332 

R337 

R341 

R350 

R353 

GPMC_BE1n 

AF1 

GPMC_DIR/GP1[20] 

AE7 

GPMC_WEn 

AG2 

40 VLYNQ_CLOCK 

AJ1 

RSV42 

Place Switch by NAND and SPI ROM 

R83 R82 

40 VLYNQ_RXD0 

AB13 

10K 10K 

RSV51 

40 VLYNQ_RXD1 

AJ6 

RSV50 

40 VLYNQ_RXD2 

AJ5 

SW4 

RSV49 

40 VLYNQ_RXD3 

AJ4 

RSV48 

1 

4 NAND_BOOTn 

NAND_BOOTn 32 

2 

3 SPI_BOOTn 

SPI_BOOTn 31 

40 VLYNQ_TXD0 

AJ3 

RSV47 

40 VLYNQ_TXD1 

AK3 

RSV46 

SW DIP-2 

40 VLYNQ_TXD2 

AJ2 

RSV45 

40 VLYNQ_TXD3 

AH8 

RSV44 

ENABLE ON BOARD MEMORIES 

NETRA_3 

A-7

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


U31-3 

DDR0_D0 

DDR0_BA0 

21 DDR0_D0 

B1 

DDR0_D1 

DDR[0]_D[0] 

DDR[0]_BA[0] 

F13 

DDR0_BA0 21 

DDR0_BA1 

21 DDR0_D1 

F2 

DDR0_D2 

DDR[0]_D[1] 

DDR[0]_BA[1] 

B14 

DDR0_BA1 21 

DDR0_BA2 

21 DDR0_D2 

E2 

DDR0_D3 

DDR[0]_D[2] 

DDR[0]_BA[2] 

N15 

DDR0_BA2 21 

21 DDR0_D3 

G4 

DDR0_D4 

DDR[0]_D[3] 

D 21 DDR0_D4 

D2 

DDR0_D5 

DDR[0]_D[4] 

DDR0_A0 

D 

21 DDR0_D5 

B2 

DDR0_A0 21 

DDR0_D6 

DDR[0]_D[5] 

DDR[0]_A[0] 

A13 

DDR0_A1 

21 DDR0_D6 

F3 

DDR0_A1 21 

DDR0_D7 

DDR[0]_D[6] 

DDR[0]_A[1] 

N17 

DDR0_A2 

21 DDR0_D7 

C1 

DDR[0]_D[7] 

DDR[0]_A[2] 

D15 

DDR0_A2 21 

DDR0_A3 

DDR[0]_A[3] 

G13 

DDR0_A3 21 

21 DDR0_DQM0 

DDR0_DQM0 

C2 

DDR[0]_DQM[0] 

DDR0_A4 

DDR0_DQS0 

DDR[0]_A[4 

H13 

DDR0_A4 21 

21 DDR0_DQS0 

F4 

DDR0_A5 

DDR0_A5 21 

21 DDR0_DQSN0 

DDR0_DQSN0 

DDR[0]_DQS[0] 

DDR[0]_A[5] 

J13 

E3 

DDR0_A6 

DDR[0]_DQS[0]n 

DDR[0]_A[6] 

L13 

DDR0_A6 21 

DDR0_A7 

DDR[0]_A[7] 

A14 

DDR0_A7 21 

DDR0_D8 

21 DDR0_D8 

C5 

DDR0_D9 

DDR[0]_D[8] 

DDR0_A8 

21 DDR0_D9 

D7 

DDR0_D10 

DDR[0]_D[9] 

DDR0]_A[8] 

N14 

DDR0_A8 21 

DDR0_A9 

21 DDR0_D10 

C6 

DDR0_D11 

DDR[0]_D[10] 

DDR[0]_A[9] 

K13 

DDR0_A9 21 

DDR0_A10 

21 DDR0_D11 

D6 

DDR0_D12 

DDR[0]_D[11] 

DDR[0]_A[10] 

C14 

DDR0_A10 21 

DDR0_A11 

21 DDR0_D12 

A5 

DDR0_A11 21 

DDR0_D13 

DDR[0]_D[12] 

DDR[0]_A[11] 

B13 

21 DDR0_D13 

B6 

DDR0_D14 

DDR[0]_D[13] 

21 DDR0_D14 

A3 

DDR0_D15 

DDR[0]_D[14] 

DDR0_A12 

21 DDR0_D15 

B3 

DDR[0]_D[15] 

DDR[0]_A[12] 

N16 

DDR0_A12 21 

DDR0_A13 

DDR[0]_A[13] 

B16 

DDR0_A13 21 

DDR0_A14 

DDR0_A14 21 

21 DDR0_DQM1 

DDR0_DQM1 

DDR[0]_A[14] 

D17 

B5 

DDR[0]_DQM[1] 

C 21 DDR0_DQS1 

DDR0_DQS1 

B4 

C 

21 DDR0_DQSN1 

DDR0_DQSN1 

DDR[0]_DQS[1] 

A4 

DDR0_CSN0 


DDR[0]_CS[0]n 

B17 

DDR0_CSN0 21 

DDR0_CSN1 

DDR0_D16 

DDR[0]_CS[1]n 

F18 

DDR0_CSN1 21 

21 DDR0_D16 

C8 

DDR0_D17 

DDR[0]_D[16] 

DDR0_CKE 

21 DDR0_D17 

A7 

DDR0_D18 

DDR[0]_D[17] 

DDR[0]_CKE C18 

DDR0_CKE 21 

21 DDR0_D18 

H10 

DDR0_D19 

DDR[0]_D[18] 

DDR0_CASN 

21 DDR0_D19 

B7 

DDR0_CASN 21 

DDR0_D20 

DDR[0]_D[19] 

DDR[0]_CASn 

C13 

21 DDR0_D20 

F8 

DDR0_D21 

DDR[0]_D[20] 

DDR0_RASN 

21 DDR0_D21 

D8 

DDR0_RASN 21 

DDR0_D22 

DDR[0]_D[21] 

DDR[0]_RASn 

D13 

21 DDR0_D22 

F9 

DDR0_D23 

DDR[0]_D[22] 

DDR0_ODT1 

21 DDR0_D23 

E7 

DDR[0]_D[23 

DDR[0_ODT[1] 

A16 

DDR0_ODT1 21 

DDR0_ODT0 

DDR0_DQM2 

DDR[0]_ODT[0] 

E18 

DDR0_ODT0 21 

21 DDR0_DQM2 

G9 

DDR[0]_DQM[2] 

DDR0_WEN 

21 DDR0_DQS2 

DDR0_DQS2 

DDR[0]_WEn 

E13 

DDR0_WEN 21 

B8 

21 DDR0_DQSN2 

DDR0_DQSN2 

DDR[0]_DQS[2] 

A8 

DDR0_CLK0 


DDR[0]_CLK[0] 

B12 

DDR0_CLK0 21 

DDR0_CLK0N 

DDR[0]_CLK[0]n 

A12 

DDR0_CLK0N 21 

DDR0_D24 

21 DDR0_D24 

E9 

DDR0_D25 

DDR[0]_D[24] 

DDR0_CLK1 

21 DDR0_D25 

B11 

DDR0_D26 

DDR[0]_D[25] 

DDR[0]_CLK[1] 

A15 

DDR0_CLK1 21 

DDR0_CLK1N 

21 DDR0_D26 

B10 

DDR0_D27 

DDR[0]_D[26] 


B15 

DDR0_CLK1N 21 

21 DDR0_D27 

E8 

B DDR0_D28 

DDR[0]_D[27] 

21 DDR0_D28 

G10 

B 

DDR0_D29 

DDR[0]_D[28] 

21 DDR0_D29 

C11 

DDR0_D30 

DDR[0]_D[29] 

DDR[0]_VTP A6 

R199 49.9 

21 DDR0_D30 

J11 

DDR0_D31 

DDR[0]_D[30] 

21 DDR0_D31 

C9 

DDR[0]_D[31] 

DDR0_RST 

DDR0_DQM3 

DDR[0]_RSTn 

D18 

DDR0_RST 21 

21 DDR0_DQM3 

D9 

DDR[0]_DQM[3] 

DDR0_DQS3 

EVM_1V5 

21 DDR0_DQS3 

B9 

21 DDR0_DQSN3 

DDR0_DQSN3 

DDR[0]_DQS[3] 

A9 

DDR[0]_DQS[3]n VREFSSTL_DDR[0] 

A17 

NETRA_3 

C705 

NO-POP 

DIFFERENTIAL PAIRS 

DDR0_VREFSSTL0 

DDR0_VREFSSTL0 21 

C708 

NO-POP 


A 

EVM_1V5 

Title: 



NETRA DDR0 INTERFACE 

EVM_1V5 8,17,20,21,22,44,47,48,50,51 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 



5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


U31-14 

DDR1_D0 

DDR1_BA0 

22 DDR1_D0 

B37 

DDR1_D1 

DDR[1]_D[0] 

DDR[1]_BA[0] 

F25 

DDR1_BA0 22 

DDR1_BA1 

22 DDR1_D1 

F36 

DDR1_D2 

DDR[1]_D[1] 

DDR[1]_BA[1] 

B24 

DDR1_BA1 22 

DDR1_BA2 

22 DDR1_D2 

E36 

DDR1_D3 

DDR[1]_D[2] 

DDR[1]_BA[2] 

N23 

DDR1_BA2 22 

D 22 DDR1_D3 

G34 

DDR1_D4 

DDR[1]_D[3] 

D 

22 DDR1_D4 

D36 

DDR1_D5 

DDR[1]_D[4] 

DDR1_A0 

22 DDR1_D5 

B36 

DDR1_A0 22 

DDR1_D6 

DDR[1]_D[5] 

DDR[1]_A[0] 

A25 

DDR1_A1 

22 DDR1_D6 

F35 

DDR1_A1 22 

DDR1_D7 

DDR[1]_D[6] 

DDR[1]_A[1] 

N21 

DDR1_A2 

22 DDR1_D7 

C37 

DDR[1]_D[7] 

DDR[1]_A[2] 

D23 

DDR1_A2 22 

DDR1_A3 

DDR[1]_A[3] 

G25 

DDR1_A3 22 

22 DDR1_DQM0 

DDR1_DQM0 

C36 

DDR[1]_DQM[0] 

DDR1_A4 

DDR1_DQS0 

DDR[1]_A[4] 

H25 

DDR1_A4 22 

22 DDR1_DQS0 

F34 

DDR1_A5 

DDR1_A5 22 

22 DDR1_DQSN0 

DDR1_DQSN0 

DDR[1]_DQS[0] 

DDR[1]_A[5] 

J25 

E35 

DDR1_A6 


DDR[1]_A[6] 

L25 

DDR1_A6 22 

DDR1_A7 

DDR[1]_A[7] 

A24 

DDR1_A7 22 

DDR1_D8 

22 DDR1_D8 

C33 

DDR1_D9 

DDR[1]_D[8] 

DDR1_A8 

22 DDR1_D9 

D31 

DDR1_D10 

DDR[1]_D[9] 

DDR[1]_A[8] 

N24 

DDR1_A8 22 

DDR1_A9 

22 DDR1_D10 

C32 

DDR1_D11 

DDR[1]_D[10] 

DDR[1]_A[9] 

K25 

DDR1_A9 22 

DDR1_A10 

22 DDR1_D11 

D32 

DDR1_D12 

DDR[1]_D[11] 

DDR[1]_A[10] 

C24 

DDR1_A10 22 

DDR1_A11 

22 DDR1_D12 

A33 

DDR1_D13 

DDR[1]_D[12] 

DDR[1]_A[11] 

B25 

DDR1_A11 22 

22 DDR1_D13 

B32 

DDR1_D14 

DDR[1]_D[13] 

22 DDR1_D14 

A35 

DDR1_D15 

DDR[1]_D[14] 

DDR1_A12 

22 DDR1_D15 

B35 

DDR[1]_D[15] 

DDR[1]_A[12] 

N22 

DDR1_A12 22 

DDR1_A13 

DDR[1]_A[13] 

B22 

DDR1_A13 22 

DDR1_A14 

DDR1_A14 22 

22 DDR1_DQM1 

DDR1_DQM1 

DDR[1]_A[14] 

D21 

B33 

DDR[1]_DQM[1] 

C C 

22 DDR1_DQS1 

DDR1_DQS1 

B34 

22 DDR1_DQSN1 

DDR1_DQSN1 

DDR[1]_DQS[1] 

A34 

DDR1_CSN0 


DDR[1]_CS[0]n 

B21 

DDR1_CSN0 22 

DDR1_CSN1 

DDR1_D16 

DDR[1]_CS[1]n 

F20 

DDR1_CSN1 22 

22 DDR1_D16 

C30 

DDR1_D17 

DDR[1]_D[16] 

DDR1_CKE 

22 DDR1_D17 

A31 

DDR1_D18 

DDR[1]_D[17] 

DDR[1]_CKE C20 

DDR1_CKE 22 

22 DDR1_D18 

H28 

DDR1_D19 

DDR[1]_D[18] 

DDR1_CASN 

22 DDR1_D19 

B31 

DDR1_CASN 22 

DDR1_D20 

DDR[1]_D[19] 

DDR[1]_CASn 

C25 

22 DDR1_D20 

F30 

DDR1_D21 

DDR[1]_D[20] 

DDR1_RASN 

22 DDR1_D21 

D30 

DDR1_RASN 22 

DDR1_D22 

DDR[1]_D[21] 

DDR[1]_RASn 

D25 

22 DDR1_D22 

F29 

DDR1_D23 

DDR[1]_D[22] 

DDR1_ODT1 

22 DDR1_D23 

E31 

DDR[1]_D[23] 

DDR[1]_ODT[1] 

A22 

DDR1_ODT1 22 

DDR1_ODT0 

DDR1_DQM2 

DDR[1]_ODT[0] 

E20 

DDR1_ODT0 22 

22 DDR1_DQM2 

G29 

DDR[1]_DQM[2] 

DDR1_WEN 

22 DDR1_DQS2 

DDR1_DQS2 

DDR[1]_WEn 

E25 

DDR1_WEN 22 

B30 

22 DDR1_DQSN2 

DDR1_DQSN2 

DDR[1]_DQS[2] 

A30 

DDR1_CLK0 


DDR[1]_CLK[0] 

B26 

DDR1_CLK0 22 

DDR1_CLK0N 


A26 

DDR1_CLK0N 22 

DDR1_D24 

DDR1_CLK1 

22 DDR1_D24 

E29 

DDR1_D25 

DDR[1]_D[24] 

DDR[1]_CLK[1] 

A23 

DDR1_CLK1 22 

DDR1_CLK1N 

22 DDR1_D25 

B27 

DDR1_D26 

DDR[1]_D[25] 


B23 

DDR1_CLK1N 22 

22 DDR1_D26 

B28 

B DDR1_D27 

DDR[1]_D[26] 

22 DDR1_D27 

E30 

B 

DDR1_D28 

DDR[1]_D[27] 

22 DDR1_D28 

G28 

DDR1_D29 

DDR[1]_D[28] 

22 DDR1_D29 

C27 

DDR1_D30 

DDR[1]_D[29] 

DDR[1]_VTP A32 

R198 49.9 

22 DDR1_D30 

J27 

DDR1_D31 

DDR[1]_D[30] 

22 DDR1_D31 

C29 

DDR[1]_D[31] 

22 DDR1_DQM3 

DDR1_DQM3 

D29 

DDR[1]_DQM[3] 

DDR1_RST 

22 DDR1_DQS3 

DDR1_DQS3 

DDR[1]_RSTn 

D20 

DDR1_RST 22 

B29 

DDR1_DQSN3 

DDR[1]_DQS[3] 

EVM_1V5 

22 DDR1_DQSN3 

A29 


VREFSSTL_DDR[1] 

A21 

NETRA_3 

C706 

NO-POP 


EVM_DDR_REF_OUT 


A C709 


A 

NO-POP 

EVM_1V5 

Title: 



NETRA DDR1 INTERFACE 

EVM_1V5 7,17,20,21,22,44,47,48,50,51 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


A-9

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


CPU_VDDA_1P0V 

AE21 

RSV52 

C582 

IOUTA AT21 

IOUTA 37 

0.1uF 

AM22 

RSV59 

EVM_1V8_A 

IOUOTB 37 

E1 

IOUTB AR21 


AG22 

CPU_VDDA_1P8V 

RSV53 

3 

1 

AG23 

D C62 C64 

RSV54 

D 

IOUTC AP21 

IOUTC 37 

0.1uF 

0.1uF 

2 

IOUTD AR20 

IOUTD 37 

AL22 

RSV59 

AK22 

RSV57 

EVM_1V0_CON 

IOUTE 37 

E2 

IOUTE AT19 


3 

1 

CPU_VDDA_1P0V 

AG20 

VDDA_SD_1P0 

IOUTF 37 

C61 

IOUTF 

AT20 

0.1uF 

AN20 

VSSA_SD 

IOUTG AU20 

IOUTG 38 

CPU_VDDA_1P8V 

AH20 

RSV41 

AU21 

RFOUT 37 

C573 C575 C574 

VDDA_SD_1P8 

AJ21 

VDDA_SD_1P8 

AH21 

0.1uF 0.1uF 0.1uF 

VDDA_SD_1P8 

EVM_1V0_CON 

C C 

R394 1.21K AP19 

VDAC_RBIAS_SD 

EVM_1V0_CON 11,15,16,17,20,44,46,50 

AU19 

VSSA_SD 

AL20 

VSSA_SD 

AM20 

VSSA_SD 

EVM_1V8_A 

EVM_1V8_A 44,50 

CPU_VDDA_1P8V 

AJ23 

C86 C70 

RSV56 

AH23 

RSV55 

0.1uF 

0.1uF 

AM21 

RSV60 

AN21 

CPU_VDDA_1P8V 

RSV60 

CPU_VDDA_1P8V 16 

CPU_VDDA_1P8V 

AT22 

VDDA_REF_1P8 

B B 

C65 

0.5 Volts 

AH19 

0.1uF 

VDAC_VREF 

C563 

AU22 

0.1uF 

VSSA_REF_1P8 

EVM_1V8_A 

CPU_VDDA_1P0V AG21 

VDDA_HD_1P0 

C587 

R490 

1K 

0.1uF 

CPU_VDDA_1P8V 

AL21 

VSSA_HD 

CPU_VDDA_1P8V 

AJ22 

C97 

C537 C548 

VDDA_HD_1P8 

AH22 

1uF 

VDDA_HD_1P8 

0.1uF 0.1uF 

1 

R361 1.21K AE22 

VDAC_RBIAS_HD 


A 

2 

4 VREF_1.24V 

R487 15.0K 

AK21 

VSSA_HD 

Title: 


AK20 

U69 

C802 C215 

R488 

VSSA_HD 

TLV431ADBV 0.1uF 0.1uF 

10.0K 

Page Contents: ANALOG VIDEO OUTPUT 

U31-7 

NETRA_3 

Revision: 

Size: B 

DWG NO 513832-0001 

B 

5 3 

2 

Date: 



5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


U31-6 

40 TSO0_BYTSTRT 

TSO0_BYTSTRT R153 1 2 22 

AL2 

TSI0_BYTSTRT 

40 TSO0_DATA 

TSO0_DATA 

RSV25 

AN2 

R149 

RSV30 

1 2 22 

TSI0_BYTSTRT 40 

R151 1 2 22 

AM2 

TSI0_DATA 

TSI0_DATA 39 

40 TSO0_PACERR 

TSO0_PACERR 

RSV24 

AU3 

R124 

RSV29 

1 2 22 

R156 1 2 22 

AL1 

TSI0_PACERR 

TSI0_PACERR 40 

40 TSO0_PACVAL 

TSO0_PACVAL 

RSV32 

RSV27 

AR1 

R137 1 2 22 

R157 1 2 22 

AK1 

R136 1 2 22 TSI0_PACVAL 

RSV31 

RSV26 

AT1 

TSI0_PACVAL 40 

D 40 TSO0_DCLK 

TSO0_DCLK R143 1 2 22 

AP1 

TSI0_DCLK 

RSV28 

RSV23 

AP2 

R142 1 2 22 

TSI0_DCLK 40 

D 


TSO1_BYTSTRT R363 1 2 22 

AP7 

TSI1_BYTSTRT 

TSO1_DATA 

VOUT[1]_C[5]/VIN[1]A_D[11] 

AP8 

R365 

VOUT[1]_Y_YC[3]/VIN[1]A_D[1] 

1 2 22 


39 TSO1_DATA 

R112 1 2 22 

AU7 

TSI1_DATA 

TSI1_DATA 39 


TSO1_PACERR 


VOUT[1]_C[4]/VIN[1]A_D[10] 

AN7 

R379 1 2 22 

R415 1 2 22 

AJ7 

TSI1_PACERR 


39 TSO1_PACVAL 

TSO1_PACVAL 


VOUT[1]_C[7]/VIN[1]A_D[13] 

AD13 

R424 1 2 22 

R113 1 2 22 

AU6 

TSI1_PACVAL 


VOUT[1]_C[6]/VIN[1]A_D[12] 

AN8 

R368 1 2 22 


39 

TSO1_DCLK 

TSO1_DCLK 

R114 1 2 22 

AT7 

VOUT[1]_CLK/VIN[1]A_CLK 

VOUT[1]_C[3]/VIN[1]A_D[9] 

AM8 

R364 1 2 22 

TSI1_DCLK 

TSI1_DCLK 39 

39 

39 

VIN0_CLK0 

VIN0_CLK1 

VIN0_CLK0 

VIN0_CLK1 

R371 1 2 22 

R120 1 2 22 

CPU_VIN0_CLK0 

CPU_VIN0_CLK1 

AR14 

AR19 

VIN[0]A_CLK 

VIN[0]B_CLK 

VIN[0]A_D[21]/VIN[0]B_FLD AU4 

VIN[0]A_D[20]/VIN[0]B_DE AN3 

VIN[0]A_D[23]/VIN[0]B_HSYNC AT2 

VIN[0]A_D[22]/VIN[0]B_VSYNC AR2 

R117 1 2 22 

R404 1 2 22 

R132 1 2 22 

R140 1 2 22 

TSI2_BYTSTRT 

TSI2_DATA 

TSI2_PACERR 

TSI2_PACVAL 


TSI2_DATA 40 



39 VIN0_D0 

VIN0_D0 

AJ19 

TSI2_DCLK 

VIN0_D1 

VIN[1]A_D[14] 

AM3 

R399 

VIN[0]A_D[0] 

1 2 22 

TSI2_DCLK 40 

39 VIN0_D1 

AU18 

VIN0_D2 

VIN[0]A_D[1] 

39 VIN0_D2 

AH18 

VIN0_D3 

VIN[0]A_D[2] 

39 VIN0_D3 

AR18 

TSI3_BYTSTRT 

39 VIN0_D4 

VIN0_D4 


AT6 

R116 

VIN[0]A_D[3] 

1 2 22 


AT18 

TSI3_DATA 

TSI3_DATA 40 

39 VIN0_D5 

VIN0_D5 


AR6 

R400 

VIN[0]A_D[4] 

1 2 22 

AT17 

TSI3_PACERR 


39 VIN0_D6 

VIN0_D6 

VOUT[1]_C[2]/VIN[1]A_D[8] 

AK6 

R413 

VIN[0]A_D[5] 

1 2 22 

AP18 

TSI3_PACVAL 


39 VIN0_D7 

VIN0_D7 

VIN[0]A_D[6] 


AP6 

R378 1 2 22 

AR17 

VIN[0]A_D[7] 

TSI3_DCLK 

C VOUT[1]_Y_YC[6]/VIN[1]A_D[4] 

AC13 

R425 1 2 22 

TSI3_DCLK 40 

C 

39 

39 

39 

39 

39 

39 

39 

39 

VIN0_D8 

VIN0_D9 

VIN0_D10 

VIN0_D11 

VIN0_D12 

VIN0_D13 

VIN0_D14 

VIN0_D15 

VIN0_D8 

VIN0_D9 

VIN0_D10 

VIN0_D11 

VIN0_D12 

VIN0_D13 

VIN0_D14 

VIN0_D15 

AP17 

AE16 

AT16 

AU17 

AU16 

AT15 

AU15 

AU14 

VIN[0]A_D[8] 

VIN[0]A_D[9] 

VIN[0]A_D[10] 

VIN[0]A_D[11] 

VIN[0]A_D[12] 

VIN[0]A_D[13] 

VIN[0]A_D[14] 

VIN[0]A_D[15] 

VIN[0]A_D[17]/VIN[1]A_VSYNC/VOUT[1]_VSYNC AL5 

VIN[0]A_D[16]/VIN[1]A_HSYNC/VOUT[1]_FLD AT5 

VIN[0]A_D[19]/VIN[1]A_DE/VOUT[1]_C[9] 

AK4 

VIN[0]A_D[18]/VIN[1]A_FLD/VOUT[1]_C[8] 

AK5 

VOUT[1]_HSYNC/VIN[1]A_D[15] 

AR5 

R410 1 2 22 

R118 1 2 22 

R408 1 2 22 

R418 1 2 22 

R362 1 2 22 

TSI4_BYTSTRT 

TSI4_DATA 

TSI4_PACERR 

TSI4_PACVAL 

TSI4_DCLK 


TSI4_DATA 39 



TSI4_DCLK 40 

VOUT0_CLK 

39 

39 

39 

39 

39 

39 

39 

39 

39 

VOUT_C2 

VOUT_C3 

VOUT_C4 

VOUT_C5 

VOUT_C6 

VOUT_C7 

VOUT_C8 

VOUT_C9 

VOUT0_CLK 

VOUT_C2 

VOUT_C3 

VOUT_C4 

VOUT_C5 

VOUT_C6 

VOUT_C7 

VOUT_C8 

VOUT_C9 

R96 1 2 22 

R370 1 2 22 

R373 1 2 22 

R386 1 2 22 

R389 1 2 22 

R374 1 2 22 

R388 1 2 22 

R375 1 2 22 

R108 1 2 22 

CPU_VOUT_CLK 

CPU_VOUT_C2 

CPU_VOUT_C3 

CPU_VOUT_C4 

CPU_VOUT_C5 

CPU_VOUT_C6 

CPU_VOUT_C7 

CPU_VOUT_C8 

CPU_VOUT_C9 

AT14 

AP13 

AL13 

AN13 

AK13 

AJ13 

AM13 

AH13 

AT12 

VOUT[0]_CLK 

VOUT[0]_B_CB_C[2] 








VOUT[0]_B_CB_C[1]/VOUT[1]_HSYNC/VOUT[1]_AVID AT9 

VOUT[0]_B_CB_C[0]/VOUT[1]_C[9]/VIN[1]B_HSYNC_DE AR9 

VOUT[0]_G_Y_YC[1]/VOUT[1]_FLD/VIN[1]B_FLD AU8 

VOUT[0]_G_Y_YC[0]/VOUT[1]_VSYNC/VIN[1]B_VSYNC AP9 

VOUT[0]_R_CR[0]/VOUT[1]_C[8]/VOUT[1]_CLK AJ11 

VIN[0]A_VSYNC AM4 

VIN[0]A_HSYNC AU5 

VIN[0]A_DE AT3 

VIN[0]A_FLD AL4 

R100 1 2 22 

R369 1 2 22 

R111 1 2 22 

R384 1 2 22 

R367 1 2 22 

R403 1 2 22 

R115 1 2 22 

R131 1 2 22 

R407 1 2 22 

TSI5_BYTSTRT 

TSI5_DATA 

TSI5_PACERR 

TSI5_PACVAL 

TSI5_DCLK 

TSI6_BYTSTRT 

TSI6_DATA 

TSI6_PACERR 

TSI6_PACVAL 


TSI5_DATA 39 



TSI5_DCLK 39 


TSI6_DATA 39 



B 39 VOUT_YC2 

VOUT_YC2 

R393 1 2 22 CPU_VOUT_YC2 AE15 

TSI6_DCLK 

B 

VOUT_YC3 

CPU_VOUT_YC3 

VOUT[1]_AVID/VIN[1]B_CLK AT4 

R125 

VOUT[0]_G_Y_YC[2] 

1 2 22 

TSI6_DCLK 39 

39 VOUT_YC3 

R372 1 2 22 

AP14 

39 VOUT_YC4 

VOUT_YC4 

R391 CPU_VOUT_YC4 


1 2 22 

AL14 

39 VOUT_YC5 

VOUT_YC5 



1 2 22 

AM14 

39 VOUT_YC6 

VOUT_YC6 



1 2 22 

AE14 

TSI7_BYTSTRT 


39 VOUT_YC7 

VOUT_YC7 

CPU_VOUT_YC7 


VOUT[0]_FLD AL9 

R381 1 2 22 

R97 1 2 22 

AT13 

TSI7_DATA 

TSI7_DATA 39 

39 VOUT_YC8 

VOUT_YC8 

CPU_VOUT_YC8 


VOUT[0]_VSYNC AN9 

R383 1 2 22 

R107 1 2 22 

AU13 

TSI7_PACERR 


39 VOUT_YC9 

VOUT_YC9 

CPU_VOUT_YC9 


VOUT[0]_R_CR[1] 

AT8 

R101 1 2 22 

R387 1 2 22 

AR13 

TSI7_PACVAL 


VOUT[0]_AVID AR8 

R102 1 2 22 


39 

39 

39 

39 

39 

39 

39 

39 

VOUT_CR2 

VOUT_CR3 

VOUT_CR4 

VOUT_CR5 

VOUT_CR6 

VOUT_CR7 

VOUT_CR8 

VOUT_CR9 

VOUT_CR2 

VOUT_CR3 

VOUT_CR4 

VOUT_CR5 

VOUT_CR6 

VOUT_CR7 

VOUT_CR8 

VOUT_CR9 

R98 1 2 22 

R385 1 2 22 

R392 1 2 22 

R99 1 2 22 

R109 1 2 22 

R382 1 2 22 

R366 1 2 22 

R110 1 2 22 

CPU_VOUT_CR2 

CPU_VOUT_CR3 

CPU_VOUT_CR4 

CPU_VOUT_CR5 

CPU_VOUT_CR6 

CPU_VOUT_CR7 

CPU_VOUT_CR8 

CPU_VOUT_CR9 

AT11 

AR11 

AG13 

AT10 

AU10 

AL10 

AK10 

AU9 

VOUT[0]_R_CR[2]/VOUT[0]_HSYNC/VOUT[1]_Y_YC[2] 

VOUT[0]_R_CR[3]/VOUT[0]_VSYNC/VOUT[1]_Y_YC[3] 

VOUT[0]_R_CR[4]/VOUT[0]_FLD/VOUT[1]_Y_YC[4] 

VOUT[0]_R_CR[5]/VOUT[0]_AVID/VOUT[1]_Y_YC[5] 

VOUT[0]_R_CR[6]/VOUT[0]_G_Y_YC[0]/VOUT[1]_Y_YC[6] 

VOUT[0]_R_CR[7]/VOUT[0]_G_Y_YC[1]/VOUT[1]_Y_YC[7] 

VOUT[0]_R_CR[8]/VOUT[0]_B_CB_C[0]/VOUT[1]_Y_YC[8] 

VOUT[0]_R_CR[9]/VOUT[0]_B_CB_C[1]/VOUT[1]_Y_YC[9] 

VOUT[0]_HSYNC AM9 

R380 1 2 22 

TSI7_DCLK 

TSI7_DCLK 39 

A NETRA_3 


A 

Title: 



DIGITAL VIDEO PORTS AND TRANSPORT STREAMS 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


A-11

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 




IMPEDANCE 


POSSIBLE, 


Place Filters as close to U31 

as possible 

EVM_3V3 

R260 

10K 

EVM_5V0 

D D 

C446 

0.1uF 

C447 

0.1uF 

U31-8 

P6 

HDMI_TMDSDP2 

U1 

HDMI_TMDSDP2 

HDMI_TMDSDP2 

AT27 

1 

HDMI_TMDSDN2 

D2+ 

HDMI_TMDSDN2 

AU27 

2 

R480 NO-POP(301) 

HDMI_TMDSDN2 

D2 SHIELD 

1 

5V_SUPPLY 

5V_OUT 

38 

3 

L22 10nH 

2 

HDMI_TMDSDP1 

HDMI_TMDSDP1 

LV_SUPPLY 

ESD_BYP 37 

D2- 

4 

D1+ 

HDMI_TMDSDP1 

AT26 

1 2 

3 

HDMI_TMDSDN1 

GND.1 

GND.2 

36 

5 

4 

HDMI_TMDSDN1 

D1 SHIELD 

HDMI_TMDSDN1 

AU26 

TMDSI_D2+ 

TMDSO_D2+ 

35 

6 

R481 NO-POP(301) 

5 

HDMI_TMDSDP0 

D1- 

TMDS_GND.1 

TMDS_GND.5 

34 

7 

L23 10nH 

D0+ 

6 

HDMI_TMDSDP0 TMDSI_D2- 

TMDSO_D2- 

33 

8 

1 2 

1206 

7 

HDMI_TMDSDN0 

D0 SHIELD 

HDMI_TMDSDP0 

AT25 

HDMI_TMDSDN0 

TMDSI_D1+ 

TMDSO_D1+ 

32 

9 

8 

HDMI_TMDSCLKP 

D0- 

HDMI_TMDSDN0 

AU25 

TMDS_GND.2 

TMDS_GND.6 

31 

10 

CK+ 

AN19 

R482 NO-POP(301) 

RSV22 

9 

TMDSI_D1- 

TMDSO_D1- 

30 

11 

L24 10nH 

10 

HDMI_TMDSCLKN 

CK SHIELD 

AN18 

RSV21 

HDMI_TMDSCLKP 

TMDSI_D0+ 

TMDSO_D0+ 

29 

12 

1 2 

1206 

CK- 

HDMI_TMDSCLKP AT24 

11 

HDMI_TMDSCLKN 

TMDS_GND.3 

TMDS_GND.7 

28 

13 

CE REMOTE 

HDMI_TMDSCLKN AU24 

12 

TMDSI_D0- 

TMDSO_D0- 

27 

14 

R483 NO-POP(301) 

NC.14 

13 

TMDSI_CK+ 

TMDSO_CK+ 

26 

15 

L25 10nH 

DDC CLK 

14 

TMDS_GND.4 

TMDS_GND.8 

25 

16 

C 1 2 

1206 

DDC DATA 

AP23 

VDDA_HDMI 

HDMI_CEC AP25 

15 

TMDSI_CK- 

TMDSO_CK- 

24 

17 

GND 

C 

AN23 

VDDA_HDMI 

16 

CE_REMOTE_IN CE_REMOTE_OUT 

23 

18 

+5V 

AP24 

VDDA_HDMI 

17 

DDC_CLK_IN 

DDC_CLK_OUT 

22 

19 

HP DET 

AN24 

VDDA_HDMI 

18 

DDC_DAT_IN 

DDC_DAT_OUT 

21 

AR27 

1206 

VDDA_HDMI 

HDMI_SCL 

AL25 

19 

HOTPLUG_DET_IN HOTPLUG_DET_OUT 

20 

HDMI_SDA AK25 

MTG1 

MTG1 

MTG2 

MTG2 

TPD12S521 

MTG3 

MTG3 

HDMI_HPDET 

AE24 

MTG4 

R249 

MTG4 

10K 

HDMI-RA-19-TYPEA 

C453 

0.1uF 

C454 

0.1uF 

HDMI_EXTSWING AN25 

EVM_5V0 EVM_5V0 EVM_3V3 

R395 

NETRA_3 

5.9K 1% 

R250 R251 R252 

VDDA_HDMI 

2K 

2K 

27K 

EVM_1V0_CON VDDA_HDMI 

L17 

1 VOLT 

EVM_3V3 

B B 

0.82Uh 

C565 

10uF 

C533 

10uF 

C542 

1uF 

C551 

0.1uF 

C555 

0.01uF 

C556 

0.01uF 

R4 

100K 

R3 

47K 

R2 

47K 

R1 

47K 

PLACE THESE CAPACITORS AS CLOSE TO VDDA PINS AS POSSIBLE 

DIFFERENTIAL SIGNALS ROUTE THROUGH ESD DEVICE 

EVM_1V0_CON 

EVM_1V0_CON 9,15,16,17,20,44,46,50 

A EVM_3V3 


A 

EVM_3V3 2,3,5,6,13,14,15,18,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,38,39,41,43,44,45,46,48,49,50,51 

Title: 


EVM_5V0 


HDMI 

Revision: 

EVM_5V0 23,25,39,41,43,44,46,49,50,51 

Size: B 

DWG NO 513832-0001 

C 

Date: 



5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


D D 

J12 

Pin # Function 

8 

1 Ground 

MH1 1 

1 

2 A+ (Transmit) 

2 

2 

3 A- (Transmit) 

3 

3 

4 Ground 

4 

4 

5 B- (Receive) 

5 

5 

6 B+ (Receive) 

6 

6 

7 Ground 

9 

MH9 7 

7 

- coding notch 

SATA HEADER 7 

A 7-pin Serial ATA data cable 



IMPEDANCE 


POSSIBLE, 


CON.SATA_TXP0 

CON.SATA_TXN0 

CON.SATA_RXN0 

CON.SATA_RXP0 

C107 .1uF 

C113 .1uF 

C106 .1uF 

C112 .1uF 

SATA_TXP0 

SATA_TXN0 

SATA_RXN0 

SATA_RXP0 



IMPEDANCE 


POSSIBLE, 



XXXX OHM DIFFERENTIAL 

IMPEDANCE 


POSSIBLE, 


C T32 

PCIE_RXN0 

CON.PCIE_RXN0 

PCIE_RXN0 

V29 

R209 0 ohms 

CON.PCIE_RXN0 23 C 

J11 

SATA_TXP0 

T31 

PCIE_RXP0 

R210 0 ohms CON.PCIE_RXP0 

SATA_TXN0 

PCIE_RXP0 

Y29 

CON.PCIE_RXP0 23 

Pin # Function 

8 

PCIE_RXN1 

1 Ground 

MH1 1 

1 

CON.SATA_TXP1 

PCIE_RXN1 

V30 

PCIE_RXP1 

2 A+ (Transmit) 

2 

2 

C78 .1uF 

V37 

SATA_RXN0 

PCIE_RXP1 

V31 

CON.PCIE_RXN1 

3 A- (Transmit) 

3 

3 

V36 

R212 0 ohms 

CON.PCIE_RXN1 23 

CON.SATA_TXN1 

SATA_RXP0 

R211 0 ohms CON.PCIE_RXP1 

4 Ground 

4 

4 

C89 .1uF 


PCIE_TXN0 

5 B- (Receive) 

5 

5 

SATA_TXP1 

PCIE_TXN0 

AB30 

PCIE_TXP0 

6 B+ (Receive) 

6 

6 

V33 

7 Ground 

SATA_TXN1 

SATA_TXP1 

PCIE_TXP0 

AB31 

9 

MH9 7 

7 

U33 

- coding notch 

CON.SATA_RXN1 C88 .1uF 

SATA_TXN1 

PCIE_TXN1 

CON.PCIE_TXN0 

PCIE_TXN1 

AB28 

C196 .1uF 

CON.PCIE_TXN0 23 

SATA HEADER 7 

PCIE_TXP1 

A 7-pin Serial ATA data cable 

CON.SATA_RXP1 C77 .1uF 

SATA_RXN1 

PCIE_TXP1 

Y27 

V35 

C211 .1uF CON.PCIE_TXP0 

CON.PCIE_TXP0 23 

SATA_RXP1 

SATA_RXN1 

W35 

SATA_RXP1 

U31-11 

C159 .1uF 

CON.PCIE_TXN1 

CON.PCIE_TXN1 23 

AB34 

C160 .1uF CON.PCIE_TXP1 

SERDES_CLKP 

CON.PCIE_TXP1 23 

AB33 

SERDES_CLKN 

R154 

NETRA_3 

NO-POP 

B B 

SERDES_IN_REFP 

C116 .1uF CPU_SERDES_IN_REFP 

13 SERDES_IN_REFP 

SERDES_IN_REFN 

C115 .1uF CPU_SERDES_IN_REFN 

13 SERDES_IN_REFN 


A 

Title: 



SATA INTERFACE 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


A-13

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


3V3_VDDA 

3V3_VDDA 3V3_VDDA 

D D 

EVM_3V3 

3V3_VDDA 

L13 

Ferrite Chip 

C91 C557 C567 C564 

10.0uF 0.01uF 0.001uF 0.1uF 

EVM_3V3 

VDD_CDC 

L26 

C569 C568 C109 C572 C571 FERRITE CHIP 

LVDS OUTPUT 

OSCOUT PIN = OFF 

0.1uF 0.1uF 10.0uF 0.1uF 0.1uF 

C U30 

C 

3V3_VDDA 

CE = '1' = ON 

PCI_CONN_REFP 

PCI_CONN_REFN 

SERDES_IN_REFP 

SERDES_IN_REFN 

GND.1 

22 

8 

NC.8 

Y2 

REG_CAP2 

17 

REG_CAP1 

19 

25.0000MHz 

C75 C76 

C87 

103274-0025R 

B 33 

TP15 

NO-POP 

B 

PWR_PAD 

1 

10.0uF 10.0uF 

101782-1334R 

ECS-250-20-33-A-E-L-TR 

OSCOUT 

23 

14,33,36,42 

RSTOUTn 

PCI_CONN_REFP 23 

PCI_CONN_REFN 23 

R147 10K 

SERDES_IN_REFP 12 

SERDES_IN_REFN 12 



IMPEDANCE 


POSSIBLE, 


3 

4 

R148 

1 

2 

NO-POP 

R406 NO-POP 

R135 10K 

R409 0 R139 10K 

R402 NO-POP 

R129 10K 

R398 0 

R123 10K 

R377 NO-POP 

R104 10K 

R103 0 

R95 10K 

R128 0 

R122 10K 

26 

25 

24 

15 

14 

13 

10 

11 

7 

12 

PR1 

PR0 

NC.24 

OD2 

OD1 

OD0 

OS1 

OS0 

CE 

RSTn 

VCC_PLL1 

18 

VCC_PLL2 

16 

VCC_VCO 9 

VCC_IN 20 

VCC_OUT.1 

VCC_OUT.2 

OUTP1 

OUTN1 

OUTP0 

OUTN0 

XIN 21 

CDCM61002 

1 

4 

3 

2 

6 

5 

TP 

27 

30 

28 

29 

31 

32 

NC.27 

NC.30 

NC.28 

NC.29 

NC.31 

NC.32 

VCO = PRE-SCALE X DIVIDER X FIN 

VCO = 3 X 24 X 25MHZ 

VCO = 1800 MHZ 

OUTCLOCK = VCO FREQ /( PRESCALE*OD) = 100mHZ 

OUTCLOCK = 1800 /( 6*3) = 100mHZ 

R475 

EVM_3V3 

EVM_3V3 2,3,5,6,11,14,15,18,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,38,39,41,43,44,45,46,48,49,50,51 


A 

Title: 



SERDES CLOCKS 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


0 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


EVM_3V3 

EVM_3V3 

R430 

10K 

C658 

0.1uF 

D D 

EMU_RSTn 1 

42 EXP_WARM_RESET 

2 

EVM_3V3 

U37 

U31-13 

4 

G33 

RESETn 

RSTOUTn 

G37 

RSTOUTn 13,33,36,42 

F37 


PORn 

WD_OUT 

WD_OUT 

H36 

G36 

NMIn 

23 

OPT_SW2 

WD_OUT 

1 

2 

4 

C659 

0.1uF 

U36 


EVM_3V3 

PORz 

TCK_T 

RTCK 

J37 

J36 

GP0[0] 

K31 

GP0[1] 

L29 

GP0[2] 

K30 

GP0[3]/TCLKIN J31 

GP0[4] 

H32 

GP0[5]/MCA[2]_AMUTEIN/GPMC_A[24] 

G2 

TCLK GP0[6]/MCA[1]_AMUTEIN/GPMC_A[23] 

G5 

GP0[7]/MCA[0]_AMUTEIN H35 

RTCK 

GP0_IO0 49 

GP0_IO1 49 

GP0_IO2 49 

GP0_IO3 49 

GP0_IO4 42 

GP0_IO5 42 

GP0_IO6 42 

GP0_IO7 42 

3 

5 

1 

2 

U34 

4 

R180 1 2 22 


TDI_T 

J34 

TDI 

GP1[30]/SATA_ACT0_LED J32 

MSP430_INT 45 

C EVM_3V3 

GP1_IO30 45 

C 

TDO R428 

GP1[31]/SATA_ACT1_LED J33 

1 2 22 

N30 

TDO 

GP1_IO31 33 

TMS 

N31 

TMS 

ENET_INTn 33 

C660 

0.1uF 

EVM_3V3 

TRSTn 

K36 

TRSTn 

U35 

51 CPU_PORz 

1 

4 

23 PCI_PORz 

2 

R182 

10K 

EMU0 R429 1 2 22 

J35 

EMU1 R177 

EMU0 

1 2 22 

L36 

EMU2 R176 

EMU1 

1 2 22 

L37 

CPU_NMIn 

EMU3 R173 

EMU2 

1 2 22 

M36 

EMU4 R175 22 

EMU3 

1 2 

M37 

R181 

EMU4 

NO-POP 

NETRA_3 

B B 

EVM_3V3 

R163 

TRSTn 

EVM_3V3 

R162 

EVM_3V3 J15 

4.7K 

EVM_3V3 

TMS 

1 

TDI_T R189 22 TDI 

TMS TRSTn 

2 

3 

R193 

R192 

TDI 

TDIS 4 

5 

4.7K 

4.7K 

TDO 

KEY 6 

R164 

TVD 

7 

RTCK 

GND.1 

8 

4.7K 

TDO 

9 

TCK_T 

TCK 

GND.2 

10 

R191 22 

TCKRTN 

11 

EMU0 

TCLK GND.3 

12 

13 

EMU1 

EMU_RSTn 

EMU0 EMU1 

14 

15 

EMU2 

SRST GND.4 

16 

17 

EMU3 

EMU4 

EMU2 EMU3 

18 

19 

EMU4 GND.5 

20 


A 

20 PIN CTI INTERFACE 

Title: 


EVM_3V3 


JTAG/GPIO/RESET 

EVM_3V3 2,3,5,6,11,13,15,18,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,38,39,41,43,44,45,46,48,49,50,51 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


0 

3 

5 

3 

5 

C661 

0.1uF 


R190 

0 

3 

5 

A-15

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


U31-15 

1.8 VOLT 

N19 

CPU_DEVOSC 

RSV3 

DEVOSC_DVDD18 

E19 

5 

OUT IN 1 

EVM_3V3 

U55 

N20 

C757 C759 

D RSV4 

18 pF C224 0.001uF 

GND 2 

C336 

D 

DEV_MXI/DEV_CLKIN A19 

0.1uF C764 C768 

1uF 1uF 4 

0.1uF 

NC/FB ENn 

3 

Y4 

27MHz 

TPS77018DBV 

18 pF C264 

DEV_MXO C19 

EVM_3V3 

H37 

CLKIN32 

DEVOSC_VSS B19 

EVM_1V8_D 

R213 

10K 

RSV18 

P33 

RSV16 

R34 

EVM_1V0_CON 

3 

R146 1K 

Q8 

C 1 

C 

FJV3109R 

2 

X2USB P34 

R74 

10K 

C153 

0.1uF 

RSV17 

P32 

NETRA_3 

R188 0 

B B 


L5 

EVM_1V0_CON 

EVM_1V0_CON 9,11,16,17,20,44,46,50 

R68 

10K 

1 

U15 

EN 

VCC 4 

BLM21PG221SN1D 2 

1 

C26 

.1uF 

c402-25 

2 

GND OUT 

3 

EVM_1V8_D 

32K HERTZ 

EVM_1V8_D 5,16,44,47,50 


A 

Title: 


EVM_3V3 

Page Contents: NETRA CLOCKS 

EVM_3V3 2,3,5,6,11,13,14,18,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,38,39,41,43,44,45,46,48,49,50,51 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 



5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


EVM_ALT_1V5 

1.5 VOLT 

1.5 VOLT 

E3 

U31-2 


3 

1 CPU_VDDA_PLL 

B18 

VDDA_PLL 

VDDR_SATA V25 

A18 

VDDA_PLL 

VDDR_SATA U25 

C618 C608 

D C214 C195 C174 

0.001uF 0.1uF 

D 

0.1uF 0.001uF 0.01uF 

EVM_ALT_1V5 

2 

CPU_VDDA_1P8V 

1.8 VOLT 

1.5 VOLT 

B20 

VSSA_PLL 

A20 

VSSA_PLL 

U19 

VSSA_PLL 

VDDR_PCIE Y25 

VDDR_PCIE W25 

C632 C617 

0.001uF 0.1uF 

AJ24 

DVDD1P8 

EVM_ALT_1V5 

C552 C534 

0.1uF 0.001uF 

EVM_1V0_CON 

E4 

1.0 VOLT 


CPU_VDDT 

VDDT_SATA V32 

1 3 

CPU_VDDA_1P8V 

VDDT_SATA 

C584 

1.8 VOLT 

Y33 

VDDT_SATA Y34 

C583 0.1uF 

VDDT_SATA V34 

C585 C586 

AJ20 

0.01uF 0.001uF 0.1uF 

DVDD1P8 

C C 

C90 C67 

0.1uF 0.001uF 

2 

EVM_1V8_D 

1.8 VOLT 

1.0 VOLT 

R422 0 

VPP_1V8 

AG25 

CPU_VDDT 

RSV12 

VDDT_PCIE AB27 

AG24 

RSV13 

VDDT_PCIE Y28 

AH25 

C576 

RSV14 


AH24 

C579 C578 C577 0.1uF 

RSV15 

VDDT_PCIE Y30 

0.01uF 0.001uF 0.1uF 


C581 C580 

0.1uF 0.001uF 

NETRA_3 

U31-17 

U31-22 

B B 

CPU_VDDA_1P8V 

RSV20 

D14 

N28 

RSV10 

CPU_VDDA_1P8V 9 

RSV8 

D24 

N29 

RSV11 

EVM_1V0_CON 

RSV1 

AB36 

EVM_1V0_CON 9,11,15,17,20,44,46,50 

RSV2 

P25 

RSV9 

AU37 

EVM_1V0_CON 

RSV7 

AE23 

EVM_1V0_CON 9,11,15,17,20,44,46,50 

NETRA_3 

NETRA_3 

EVM_1V8_D 

A A 

EVM_1V8_D 5,15,44,47,50 


Title: 


EVM_ALT_1V5 

Page Contents: NETRA POWER PINS 

EVM_ALT_1V5 44,48 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


A-17

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


1 VOLT 

EVM_1V0_CON U31-18 

EVM_1V0_CON 

EVM_1V0_CON 

N13 

EVM_1V0_CON 

CVDDC 

CVDDC AE13 

N25 

CVDDC 

CVDDC AE25 

C63 

C74 C538 C72 C540 C92 C554 C85 C549 C84 C550 

P14 

CVDDC 

CVDDC AC14 

+ C117 

33uF P15 

C532 

C562 

D 0.1uF 

CVDDC 

CVDDC AC15 

C69 C535 C66 

C530 C55 C52 

C529 C95 33uF 

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 

0.1uF 

0.1uF 

D 

P23 

c201-6p6spc 

c201-6p6spc 

CVDDC 

CVDDC AC23 

0.1uF 0.1uF 0.1uF 

0.1uF 0.1uF 0.1uF 

0.1uF 0.1uF 

c201-6p6spc c201-6p6spc c201-6p6spc c201-6p6spc 

c201-6p6spc c201-6p6spc c201-6p6spc 

c201-6p6spc 

P24 

c201-6p6spc 

c201-6p6spc 

CVDDC 

CVDDC AC24 



c201-6p6spc c201-6p6spc 

R14 

CVDDC 

CVDDC AD14 

R15 

CVDDC 

CVDDC AD15 

R23 

CVDDC 

CVDDC AD23 

R24 

CVDDC 

CVDDC AD24 

EVM_1V0_CON 

NETRA_3 

EVM_1V0_CON 9,11,15,16,20,44,46,50 

1.5 VOLT 

U31-19 

EVM_1V5 

EVM_1V5 

EVM_1V5 

A2 

EVM_1V5 

DVDD_DDR[0] 

DVDD_DDR[0] 

K15 

A11 

DVDD_DDR[0] 

DVDD_DDR[0] 

K16 

E1 

DVDD_DDR[0] 

DVDD_DDR[0] 

K17 

E11 

C189 

C680 C207 

C674 

C208 

DVDD_DDR[0] 

DVDD_DDR[0] 

K18 

C185 C205 C184 

C187 C186 

0.1uF 

0.1uF 0.1uF 

0.1uF 

0.1uF 

DVDD_DDR[0] 

K19 

C142 

C203 

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 

C C 

c201-6p6spc c201-6p6spc c201-6p6spc c201-6p6spc c201-6p6spc 

J15 



DVDD_DDR[0] 

DVDD_DDR[0] 

L14 

c201-6p6spc 

c201-6p6spc 

J14 

DVDD_DDR[0] 

DVDD_DDR[0] 

L15 

J16 

DVDD_DDR[0] 

DVDD_DDR[0] 

L16 

J17 

DVDD_DDR[0] 

DVDD_DDR[0] 

L17 

J18 

EVM_1V5 

DVDD_DDR[0] 

DVDD_DDR[0] 

L18 

K14 

EVM_1V5 

DVDD_DDR[0] 

DVDD_DDR[0] 

L19 

+ C354 

33uF C647 

C646 

C679 

C188 

C151 C183 

0.1uF 

0.1uF 

0.1uF 

0.1uF 

NETRA_3 

0.1uF 0.1uF 

c201-6p6spc c201-6p6spc c201-6p6spc c201-6p6spc 

c201-6p6spc 

C230 

C206 C204 33uF 

0.1uF 0.1uF 

c201-6p6spc c201-6p6spc c201-18p5x15 

EVM_1V5 

1.5 VOLT 

U31-20 

EVM_1V5 

B EVM_1V5 

DVDD_DDR[1] 

K20 

A27 

B 

DVDD_DDR[1] 

DVDD_DDR[1] 

K21 

A36 

DVDD_DDR[1] 

K22 

C176 C201 C202 C149 

DVDD_DDR[1] 

D37 

DVDD_DDR[1] 

K23 

C223 

+ C368 

DVDD_DDR[1] 

E27 

C198 

DVDD_DDR[1] 

K24 

C200 

C197 

C150 

C199 33uF 

33uF 0.1uF 0.1uF 0.1uF 0.1uF 

DVDD_DDR[1] 

0.1uF 

0.1uF 

0.1uF 

0.1uF 

0.1uF 


J19 

DVDD_DDR[1] 

DVDD_DDR[1] 

L20 

J21 

DVDD_DDR[1] 

DVDD_DDR[1] 

L21 

J20 

DVDD_DDR[1] 

DVDD_DDR[1] 

L22 

J22 

DVDD_DDR[1] 

DVDD_DDR[1] 

L23 

J23 

EVM_1V5 

EVM_1V5 

DVDD_DDR[1] 

DVDD_DDR[1] 

L24 

J24 

DVDD_DDR[1] 

C683 C648 C700 

C681 

C682 

0.1uF 

0.1uF 0.1uF 0.1uF 0.1uF 

C180 

C178 

C182 

C181 C177 

C179 


0.1uF 

0.1uF 

0.1uF 

0.1uF 0.1uF 

0.1uF 

NETRA_3 

c201-6p6spc c201-6p6spc c201-6p6spc c201-6p6spc c201-6p6spc c201-6p6spc 

EVM_1V5 

EVM_1V5 

EVM_1V5 7,8,20,21,22,44,47,48,50,51 


A 

Title: 



NETRA POWER PINS II 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


+ 

+ 

+ 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


EVM_3V3 

3.3 VOLT 

SMALLEST BODY USED U31-21 

SMALLEST BODY USED 

EVM_3V3 

EVM_3V3 

L1 

EVM_3V3 

DVDD_3P3 

DVDD_3P3 

AC27 

L5 

DVDD_3P3 

DVDD_3P3 

AC28 

C138 C139 C98 

C559 C541 C96 C561 C546 C539 

L30 

DVDD_3P3 

DVDD_3P3 

AC29 

L35 

C637 C124 

0.1uF 

0.1uF 

DVDD_3P3 

AD9 

C128 

C120 C111 C591 C566 C146 C108 C589 

0.1uF 0.1uF 

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 

DVDD_3P3 

P8 

0.1uF 0.1uF 

DVDD_3P3 

DVDD_3P3 

AD10 

0.1uF 

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 

P9 

DVDD_3P3 

DVDD_3P3 

AD11 


P10 

D DVDD_3P3 

DVDD_3P3 

AD27 

D 

P11 

DVDD_3P3 

DVDD_3P3 

AD28 

P27 

DVDD_3P3 

DVDD_3P3 

AD29 

P28 

EVM_3V3 

DVDD_3P3 

DVDD_3P3 

AE27 

EVM_3V3 

EVM_3V3 

P29 

EVM_3V3 

DVDD_3P3 

DVDD_3P3 

AE28 

P30 

DVDD_3P3 

DVDD_3P3 

AE29 

C560 C545 C79 C544 C553 C536 C56 C73 C71 C80 

R9 

C592 

DVDD_3P3 

DVDD_3P3 

AG14 

R10 

C125 

DVDD_3P3 

DVDD_3P3 

AG15 

C133 C615 C652 

C644 C570 C121 C129 C83 

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 

R11 

0.1uF 

0.1uF 

DVDD_3P3 

DVDD_3P3 

AG16 

0.1uF 0.1uF 0.1uF 

.1uF .1uF .1uF .1uF .1uF 

R27 

DVDD_3P3 

DVDD_3P3 

AG17 

R28 

DVDD_3P3 

DVDD_3P3 

AG33 

T9 

DVDD_3P3 

DVDD_3P3 

AH14 

T10 

DVDD_3P3 

DVDD_3P3 

AH15 

T11 

EVM_3V3 

DVDD_3P3 

DVDD_3P3 

AH16 

EVM_3V3 

EVM_3V3 

U9 

EVM_3V3 

DVDD_3P3 

DVDD_3P3 

AH17 

U10 

DVDD_3P3 

DVDD_3P3 

AJ14 

C547 C650 C649 C651 

C543 C68 C531 C144 C145 

U11 

C613 

DVDD_3P3 

DVDD_3P3 

AJ15 

C636 C638 C134 C114 C105 C122 C593 C614 C135 

Y9 

0.1uF 

DVDD_3P3 

DVDD_3P3 

AJ16 

0.1uF 0.1uF 0.1uF 0.1uF 

0.1uF 0.1uF 0.1uF 0.1uF 

AA1 

0.1uF 

DVDD_3P3 

DVDD_3P3 

AJ17 


AA9 

DVDD_3P3 

C AA10 

DVDD_3P3 

DVDD_3P3 

AN1 

C 

AA11 

DVDD_3P3 

DVDD_3P3 

AN11 

AB9 

DVDD_3P3 

DVDD_3P3 

AN27 

AB10 

EVM_3V3 DVDD_3P3 

DVDD_3P3 

AN37 

EVM_3V3 

EVM_3V3 

AB11 

EVM_3V3 

DVDD_3P3 

DVDD_3P3 

AU2 

AC9 

DVDD_3P3 

DVDD_3P3 

AU11 

+ C51 

C93 C81 C82 C558 

AC10 

C147 

DVDD_3P3 

DVDD_3P3 

AU29 

C643 C590 

C130 

+ C140 + C53 

33uF + C131 

AC11 

33uF 

33uF 

33uF 

0.1uF 0.1uF 0.1uF 0.1uF 

DVDD_3P3 

0.1uF 0.1uF 0.1uF 0.1uF 

EVM_3V3 

EVM_3V3 2,3,5,6,11,13,14,15,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,38,39,41,43,44,45,46,48,49,50,51 

NETRA_3 

CORE AVS SUPPLY 1.0 VOLT 

U31-16 

EVM_1V0_AVS SMALLEST BODY USED 

EVM_1V0_AVS 

B SMALLEST BODY USED 

B 

EVM_1V0_AVS 

P16 

EVM_1V0_AVS 

CVDD 

CVDD AD16 

P17 

CVDD 

CVDD AD17 

C645 C597 C600 C601 C594 C598 C620 C599 C137 C619 

P18 

C596 

CVDD 

CVDD AD18 

C622 C629 C627 C630 C621 C602 C595 C624 

C631 

P19 

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 

CVDD 

CVDD AD19 

P20 

0.1uF 

CVDD 

CVDD AD20 

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 

0.1uF 

P21 

CVDD 

CVDD AD21 

P22 

EVM_1V0_AVS 

CVDD 

CVDD AD22 

EVM_1V0_AVS 

C164 

33uF 

C141 

33uF 

EVM_1V0_AVS 

R16 

EVM_1V0_AVS 

CVDD 

CVDD AC16 

R17 

CVDD 

CVDD AC17 

C604 C605 C606 C603 

R18 

CVDD 

CVDD AC18 

C628 C626 C623 C625 

+ C123 + C165 

R19 

0.1uF 

0.1uF 

CVDD 

CVDD AC19 

33uF 

33uF 

0.1uF 

0.1uF 

R20 

CVDD 

CVDD AC20 

0.1uF 0.1uF 0.1uF 0.1uF 

R21 

CVDD 

CVDD AC21 

R22 

CVDD 

CVDD AC22 

T14 

CVDD 

CVDD AB14 

T15 

CVDD 

CVDD AB15 

T16 

CVDD 

CVDD AB16 

T17 

CVDD 

CVDD AB17 

T18 

CVDD 

CVDD AB18 

A T19 


A 

CVDD 

CVDD AB19 

T20 

EVM_1V0_AVS 

CVDD 

CVDD AB20 

T21 

CVDD 

CVDD AB21 

Title: 


T22 

CVDD 

CVDD AB22 

EVM_1V0_AVS 20,44,49 

T23 

CVDD 

CVDD AB23 

T24 

Page Contents: NETRA POWER PINS III 

CVDD 

CVDD AB24 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

NETRA_3 

Date: Sheet o f Wednesday, November 03, 2010 18 52 

+ 

+ 

A-19

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


VSS W20 

VSS W21 

VSS W22 

VSS W23 

VSS W24 

VSS Y4 

VSS Y5 

VSS Y6 

VSS Y7 

VSS Y8 

VSS Y13 

VSS Y14 

VSS Y15 

VSS Y16 

VSS Y17 

VSS Y18 

VSS Y19 

VSS Y20 

VSS Y21 

VSS Y22 

VSS Y23 

VSS Y24 

VSS Y31 

VSS Y32 

VSS Y36 

VSS Y37 

VSS AA5 

VSS AA6 

VSS AA7 

VSS AA8 

VSS AA13 

VSS AA14 

VSS AA15 

VSS AA16 

VSS AA17 

VSS AA18 

VSS AA19 

VSS AA20 

VSS AA21 

VSS AA22 

VSS AA23 

VSS AA24 

VSS AB1 

VSS AB6 

VSS AB7 

VSS AB8 

VSS AB35 

VSS AB37 

VSS AC3 

VSS AC4 

VSS AC6 

VSS AC7 

VSS AC8 

U31-1 

D D 

A1 

VSS 

VSS AC30 

A10 

VSS 

VSS AC31 

A28 

VSS 

VSS AC33 

A37 

VSS 

VSS AC32 

C15 

VSS 

VSS AC34 

C17 

VSS 

VSS AD5 

C21 

VSS 

VSS AD6 

C23 

VSS 

VSS AD7 

D1 

VSS 

VSS AD30 

E14 

VSS 

VSS AD31 

E24 

VSS 

VSS AD32 

E37 

VSS 

VSS AD33 

F7 

VSS 

VSS AD34 

F14 

VSS 

VSS AE17 

F15 

VSS 

VSS AE18 

F16 

VSS 

VSS AE19 

F17 

VSS 

VSS AE20 

F21 

VSS 

VSS AF11 

F22 

VSS 

VSS AF27 

F23 

VSS 

VSS AG5 

F31 

VSS 

VSS AG8 

F24 

VSS 

VSS AG12 

G6 

VSS 

VSS AG26 

C G7 

VSS 

VSS AG30 

C 

G14 

VSS 

VSS AJ18 

G15 

VSS 

VSS AJ25 

G16 

VSS 

VSS AK11 

G17 

VSS 

VSS AK15 

G18 

VSS 

VSS AK16 

G20 

VSS 

VSS AK17 

G21 

VSS 

VSS AK18 

G22 

VSS 

VSS AK19 

G23 

VSS 

VSS AK23 

G24 

VSS 

VSS AK24 

G31 

VSS 

VSS AK27 

G32 

VSS 

VSS AL6 

H11 

VSS 

VSS AL7 

H14 

VSS 

VSS AL15 

H15 

VSS 

VSS AL16 

H16 

VSS 

VSS AL17 

H17 

VSS 

VSS AL18 

H18 

VSS 

VSS AL19 

H19 

VSS 

VSS AL23 

H20 

VSS 

VSS AL24 

H21 

VSS 

VSS AL31 

H22 

VSS 

VSS AL32 

H23 

VSS 

VSS AM1 

B H24 

B 

VSS 

VSS AM7 

H27 

VSS 

VSS AM15 

K1 

VSS 

VSS AM16 

K37 

VSS 

VSS AM17 

L8 

VSS 

VSS AM18 

L12 

VSS 

VSS AM19 

L26 

VSS 

VSS AM23 

L33 

VSS 

VSS AM24 

M11 

VSS 

VSS AM25 

M27 

VSS 

VSS AM31 

N18 

VSS 

VSS AN14 

P4 

VSS 

VSS AN15 

P5 

VSS 

VSS AP15 

P6 

VSS 

VSS AP37 

P7 

VSS 

VSS AR15 

P31 

VSS 

VSS AR23 

R3 

VSS 

VSS AR24 

R4 

VSS 

VSS AR25 

R6 

VSS 

VSS AT23 

R7 

VSS 

VSS AU1 

R8 

VSS 

VSS AU12 

R31 

VSS 

VSS AU23 

VSS AU28 


A 

Title: 


VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

NETRA_3 


NETRA GROUND PINS 

R32 

R33 

T6 

T7 

T8 

T33 

T34 

T35 

U5 

U6 

U7 

U8 

U13 

U14 

U15 

U16 

U17 

U18 

U20 

U21 

U22 

U23 

U24 

V4 

V5 

V6 

V7 

V8 

V9 

V13 

V14 

V15 

V16 

V17 

V18 

V19 

V20 

V21 

V22 

V23 

V24 

V27 

V28 

W6 

W7 

W8 

W9 

W13 

W14 

W15 

W16 

W17 

W18 

W19 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 



5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


EVM_1V0_AVS 

EVM_1V0_AVS 

EVM_1V0_AVS 

EVM_1V0_AVS 18,44,49 

C440 

C433 

C392 

C441 

C434 

C414 

C407 

C421 

C391 

C398 

C405 

C412 

C419 

C399 

C426 

C442 



D D 

EVM_1V0_AVS 

C428 

C435 

C427 

C406 

C413 

C420 

C400 

C393 


EVM_1V0_CON 

EVM_1V0_CON 9,11,15,16,17,44,46,50 

C C 

EVM_1V0_CON EVM_1V0_CON 

C390 

0.01uF 

C397 

0.01uF 

C389 

0.01uF 

C432 

0.01uF 

C439 

0.01uF 

C431 

0.01uF 

C438 

0.01uF 

C396 

0.01uF 

EVM_1V5 

EVM_1V5 

C192 C673 C691 C163 C664 C156 C669 C656 C672 

C191 C193 C686 C665 C667 C702 C677 C697 C690 



B B 

EVM_1V5 

EVM_1V5 

C670 C678 C687 C699 C696 C684 C685 C675 C167 

C698 C170 C194 C668 C168 C688 C158 C157 C662 



EVM_1V5 

EVM_1V5 

C175 C155 C671 C689 C190 

C695 C701 C676 C663 C655 C654 C703 C166 C169 

0.001uF 0.001uF 0.001uF 0.001uF 0.001uF 



A 

Title: 



NETRA POWER CAPS 

EVM_1V5 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

EVM_1V5 7,8,17,21,22,44,47,48,50,51 


A-21

5 

5 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

7 

4 

4 

3 

3 

2 

2 

1 

1 


J21A 

DDR0_RST 

1 

A1 A121 

121 

2 

DDR0_D3 

DDR0_D1 

A2 A122 

122 

DDR0_D3 7 


7 DDR0_D1 

3 

DDR0_D6 

DDR0_D4 

A3 A123 

123 

DDR0_D6 7 

DDR0_D4 

4 

DDR0_DQSN0 

A4 A124 

124 

DDR0_DQSN0 

5 

DDR0_DQM0 

DDR0_DQS0 

A5 A125 

125 

DDR0_DQM0 7 

D DDR0_DQS0 

6 

A6 A126 

126 

D 

7 

DDR0_D2 

A7 A127 

127 

DDR0_D2 7 

8 

DDR0_D7 

DDR0_D0 

A8 A128 

128 

DDR0_D7 7 

DDR0_D0 

9 

DDR0_D8 

DDR0_D5 

A9 A129 

129 

DDR0_D8 7 

DDR0_D5 

10 

DDR0_D10 

DDR0_D15 

A10 A130 

130 

DDR0_D10 7 

DDR0_D15 

11 

DDR0_D14 

A11 A131 

131 

DDR0_D14 

12 

DDR0_DQM1 

A12 A132 

132 

DDR0_DQM1 7 

13 

DDR0_DQSN1 

A13 A133 

133 

DDR0_DQSN1 

14 

DDR0_D11 

DDR0_DQS1 

A14 A134 

134 

DDR0_D11 7 

DDR0_DQS1 

15 

DDR0_D9 

DDR0_D12 

A15 A135 

135 

DDR0_D9 7 

DDR0_D12 

16 

DDR0_D13 

A16 A136 

136 

DDR0_D13 

17 

A17 A137 

137 

18 

DDR0_D23 

A18 A138 

138 

DDR0_D23 7 

19 

DDR0_D22 

DDR0_D19 

A19 A139 

139 

DDR0_D22 7 

DDR0_D19 

20 

DDR0_D17 

A20 A140 

140 

DDR0_D17 

21 

DDR0_DQM2 

DDR0_DQSN2 

DDR0_DQSN2 

A21 A141 

141 

DDR0_DQM2 7 

22 

DDR0_DQS2 

DDR0_DQS2 

A22 A142 

142 

23 

A23 A143 

143 

24 

DDR0_D21 

A24 A144 

144 

DDR0_D21 7 

25 

DDR0_D20 

DDR0_D16 

A25 A145 

145 

DDR0_D20 7 

DDR0_D16 

26 

DDR0_D24 

DDR0_D18 

A26 A146 

146 

DDR0_D24 7 

DDR0_D18 

27 

DDR0_D27 

DDR0_D28 

A27 A147 

147 

DDR0_D27 7 

DDR0_D28 

28 

DDR0_D30 

A28 A148 

148 

DDR0_D30 

29 

DDR0_DQM3 

A29 A149 

149 

DDR0_DQM3 7 

C 30 

C 

DDR0_DQSN3 

DDR0_DQSN3 

A30 A150 

150 

31 

DDR0_D31 

DDR0_D31 7 

DDR0_DQS3 

DDR0_DQS3 

A31 A151 

151 

32 

DDR0_D29 

DDR0_D29 7 

DDR0_D26 

DDR0_D26 

A32 A152 

152 

33 

DDR0_D25 

DDR0_D25 

A33 A153 

153 

34 

DDR0_ CLK0 

DDR0_CLK0 7 

EVM_1V5 

A34 A154 

154 

35 

DDR0_ CLK0N 

DDR0_CLK0N 7 

DDR0_A6 

DDR0_A6 

A35 A155 

155 

36 

EVM_1V5 

DDR0_A5 

DDR0_A5 

A36 A156 

156 

37 

DDR0_A9 

DDR0_A9 7 

EVM_1V5 

A37 A157 

157 

38 

DDR0_BA0 

DDR0_BA0 7 

DDR0_A4 

DDR0_A4 

A38 A158 

158 

39 

EVM_1V5 

7 DDR0_A3 

DDR0_A3 

A39 A159 

159 

40 

DDR0_RASN 

DDR0_RASN 7 

EVM_1V5 

A40 A160 

160 

41 

DDR0_A11 

DDR0_A11 7 

DDR0_WEN 

DDR0_WEN 

A41 A161 

161 

42 

EVM_1V5 

DDR0_CASN 

DDR0_CASN 

A42 A162 

162 

43 

DDR0_A8 

DDR0_A8 7 

EVM_1V5 

A43 A163 

163 

44 

DDR0_BA1 

DDR0_BA1 7 

DDR0_A0 

DDR0_A0 

A44 A164 

164 

45 

EVM_1V5 

DDR0_A10 

DDR0_A10 

A45 A165 

165 

46 

DDR0_CLK1N 

DDR0_CLK1N 7 

EVM_1V5 

A46 A166 

166 

47 

DDR0_CLK1 

DDR0_CLK1 7 

EVM_1V5 

A47 A167 

167 

48 

EVM_1V5 

EVM_1V5 

A48 A168 

168 

49 

EVM_1V5 

7 DDR0_A7 

DDR0_A7 

A49 A169 

169 

50 

DDR0_BA2 

DDR0_BA2 7 

DDR0_A2 

DDR0_A2 

A50 A170 

170 

51 

DDR0_A12 

DDR0_A12 7 

EVM_1V5 

A51 A171 

171 

52 

EVM_1V5 

DDR0_A1 

DDR0_A1 

A52 A172 

172 

53 

RA15 

B DDR0_A13 

DDR0_A13 

A53 A173 

173 

54 

DDR0_A14 

DDR0_A14 7 

B 

EVM_1V5 

A54 A174 

174 

55 

EVM_1V5 

DDR0_CSN1 

DDR0_CSN1 

A55 A175 

175 

56 

DDR0_CSN0 

DDR0_CSN0 7 

DDR0_ODT1 

DDR0_ODT1 

A56 A176 

176 

57 

DDR0_ODT0 

DDR0_ODT0 7 

EVM_1V5 

A57 A177 

177 

58 

EVM_1V5 

DDR0_CKE 

DDR0_CKE 

A58 A178 

178 

59 



A59 A179 

179 

60 

A60 A180 

180 

EVM_3V3 

molex-87966 

A EVM_3V3 


A 

EVM_3V3 2,3,5,6,11,13,14,15,18,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,38,39,41,43,44,45,46,48,49,50,51 

Title: 


EVM_1V5 

Page Contents: EMIF A - DDR DUAL DIMM INTERFACE 

EVM_1V5 

EVM_1V5 7,8,17,20,22,44,47,48,50,51 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: Wednesday, November 03, 2010 Sheet 21 o f 52 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


EVM_3V3 


J21B 

D D 

61 


A61 A181 

181 


62 

DDR1_CKE 

EVM_1V5 

A62 A182 

182 

DDR1_CKE 8 

63 

EVM_1V5 

DDR1_ODT0 

A63 A183 

183 

DDR1_ODT0 

64 

DDR1_ODT1 

DDR1_CSN0 

A64 A184 

184 

DDR1_ODT1 8 

DDR1_CSN0 

65 

DDR1_CSN1 

EVM_1V5 

A65 A185 

185 

DDR1_CSN1 8 

66 

EVM_1V5 

DDR1_A14 

A66 A186 

186 

DDR1_A14 

67 

DDR1_A13 

A67 A187 

187 

DDR1_A13 8 

68 

DDR1_A1 

EVM_1V5 

A68 A188 

188 

DDR1_A1 8 

69 

EVM_1V5 

DDR1_A12 

A69 A189 

189 

DDR1_A12 

70 

DDR1_A2 

DDR1_BA2 

A70 A190 

190 

DDR1_A2 8 

DDR1_BA2 

71 

DDR1_A7 

EVM_1V5 

A71 A191 

191 

DDR1_A7 8 

72 

EVM_1V5 

EVM_1V5 

A72 A192 

192 

73 

EVM_1V5 

DDR1_CLK1 

A73 A193 

193 

DDR1_CLK1 

74 

EVM_1V5 

DDR1_CLK1N 

DDR1_CLK1N 

A74 A194 

194 

75 

DDR1_A10 

EVM_1V5 

A75 A195 

195 

DDR1_A10 8 

76 

DDR1_A0 

DDR1_BA1 

DDR1_BA1 

A76 A196 

196 

DDR1_A0 8 

77 

EVM_1V5 

DDR1_A8 

DDR1_A8 

A77 A197 

197 

78 

DDR1_CASN 

EVM_1V5 

A78 A198 

198 

DDR1_CASN 8 

79 

DDR1_WEN 

DDR1_A11 

DDR1_A11 

A79 A199 

199 

DDR1_WEN 8 

80 

EVM_1V5 

DDR1_RASN 

DDR1_RASN 

A80 A200 

200 

81 

DDR1_A3 

DDR1_A3 8 

EVM_1V5 

A81 A201 

201 

82 

DDR1_A4 

DDR1_A4 8 

DDR1_BA0 

DDR1_BA0 

A82 A202 

202 

83 

EVM_1V5 

DDR1_A9 

A83 A203 

203 

DDR1_A5 

C DDR1_A9 

84 

DDR1_A5 8 

C 

EVM_1V5 

A84 A204 

204 

85 

DDR1_A6 

DDR1_A6 8 

DDR1_CLK0N 

DDR1_CLK0N 

A85 A205 

205 

86 

EVM_1V5 

DDR1_CLK0 

DDR1_CLK0 

A86 A206 

206 

87 

DDR1_D29 

A87 A207 

207 

DDR1_D29 8 

88 

DDR1_D31 

DDR1_D31 8 

DDR1_D25 

A88 A208 

208 

DDR1_DQS3 

DDR1_D25 

89 

DDR1_DQS3 8 

DDR1_D26 

A89 A209 

209 

DDR1_DQSN3 

DDR1_D26 

90 

A90 A210 

210 

DDR1_DQSN3 8 

91 

DDR1_DQM3 

DDR1_DQM3 

A91 A211 

211 

92 

DDR1_D24 

A92 A212 

212 

DDR1_D24 8 

93 

DDR1_D28 

DDR1_D28 8 

DDR1_D27 

A93 A213 

213 

DDR1_D18 

DDR1_D27 

94 

DDR1_D18 8 

DDR1_D30 

A94 A214 

214 

DDR1_D22 

DDR1_D30 

95 

DDR1_D22 8 

DDR1_D16 

A95 A215 

215 

DDR1_D16 

96 

DDR1_D17 

A96 A216 

216 

DDR1_D17 

97 

A97 A217 

217 

98 

DDR1_DQS2 

A98 A218 

218 

DDR1_DQS2 8 

99 

DDR1_DQSN2 

DDR1_DQSN2 8 

DDR1_DQM2 

DDR1_DQM2 

A99 A219 

219 

100 

DDR1_D23 

A100 A220 

220 

DDR1_D23 8 

101 

DDR1_D21 

DDR1_D21 8 

DDR1_D19 

A101 A221 

221 

DDR1_D19 

102 

DDR1_D20 

A102 A222 

222 

DDR1_D20 

103 

A103 A223 

223 

104 

DDR1_D9 

A104 A224 

224 

DDR1_D9 8 

105 

DDR1_D8 

DDR1_D8 8 

DDR1_D13 

A105 A225 

225 

DDR1_DQS1 

DDR1_D13 

106 

DDR1_DQS1 8 

DDR1_D12 

A106 A226 

226 

DDR1_DQSN1 

DDR1_D12 

107 

A107 A227 

227 

DDR1_DQSN1 8 

B 108 

B 

DDR1_DQM1 

DDR1_DQM1 

A108 A228 

228 

109 

DDR1_D10 

A109 A229 

229 

DDR1_D10 8 

110 

DDR1_D11 

DDR1_D11 8 

DDR1_D14 

A110 A230 

230 

DDR1_D6 

DDR1_D14 

111 

DDR1_D6 8 

DDR1_D15 

A111 A231 

231 

DDR1_D3 

DDR1_D15 

112 

DDR1_D3 8 

DDR1_D5 

A112 A232 

232 

DDR1_D5 

113 

DDR1_D0 

A113 A233 

233 

DDR1_D0 

114 

A114 A234 

234 

115 

DDR1_DQS0 

DDR1_DQS0 8 

DDR1_DQM0 

DDR1_DQM0 

A115 A235 

235 

116 

DDR1_DQSN0 

A116 A236 

236 

DDR1_DQSN0 8 

117 

DDR1_D2 

DDR1_D2 8 

DDR1_D7 

A117 A237 

237 

DDR1_D1 

DDR1_D7 

118 

DDR1_D1 8 

DDR1_D4 

A118 A238 

238 

DDR1_D4 

119 

A119 A239 

239 

120 

A120 A240 

240 

DDR1_RST 8 

molex-87966 

EVM_3V3 

EVM_3V3 2,3,5,6,11,13,14,15,18,21,23,24,26,27,28,29,30,31,32,33,34,35,36,37,38,39,41,43,44,45,46,48,49,50,51 

A EVM_1V5 


A 

EVM_1V5 

EVM_1V5 7,8,17,20,21,44,47,48,50,51 

Title: 



EMIF B - DDR DUAL DIMM INTERFACE 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

8 

A-23

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


EVM_5V0 

EVM_3V3 

EVM_3V3 EVM_3V3 EVM_3V3 

C710 

C707 

EVM_12V 

C752 

0.1uF 

.1uF 

R201 

R220 

U46 

10K 

0.1uF 

10K 

U44 

R222 10K 

5 

SENSE1 VDD 6 27 PCI_SW_RESETn 

1 

4 

2 

4 

R221 

4 

CT RESET 

1 

2 

1K 1% 

U43 

D C758 

D 

3 

MR GND 2 


74CBTLV1G125CRG4 

0.1uF 

TPS3808G09DBVRG4 

EVM_3V3 

Reset Threhold 0.84 Volts 

EVM_5V0 

EVM_3V3 

R195 R197 

10K 10K 

PCI_3V3 

C725 

SW5 

R217 

U45 

0.1uF 

10K 

1 

4 

OPT_SW1 

R218 10K 

5 

2 

3 

OPT_SW2 

SENSE1 VDD 6 OPT_SW2 14 

3 

1 

3 

5 

5 

R219 

1K 1% 

C739 

0.1uF 

4 

3 

CT 

MR 

RESET 


1 

GND 2 

SW DIP-2 

OPT_SW1 PCI RESET MODE IN OR OUT 

OPT_SW2 WDOG RESET ENABLED 

C C 


EVM_3V3 

PCI_3V3 

EVM_12V 

P8 

EVM_12V 

EVM_3V3 

R200 

10K 

C694 

0.1uF 

R456 

2 

4 

PCI_PORz 14 

B1 

PRSNT1 

A1 

10K 

+12V.1 

B2 

+12V.4 

A2 

R451 R443 

U41 

+12V.2 

B3 

PCI_3V3 

+12V.5 

A3 

10K 

10K 

74LV1G126CRG4 

+12V.3 

B4 

GND.1 

GND.12 

A4 

B5 

SMCLK 

TCK A5 

B6 

SMDAT 

TDI 

A6 

B7 

GND.2 

TDO A7 

B8 

+3.3V.1 

TMS A8 

B9 

TRSTn 

+3.3V.2 

A9 

B10 

PCI_3V3 

+3.3V.3 

A10 

B R440 

3.3VAUX 

B11 

B 

PERSTn 

A11 

10K 

WAKEn 

R203 

.1uF C210 PCI_CONN_REFP 

KEY 

PCI_CONN_REFP 13 

NO-POP 

B12 

PCI_CONN_REFN 

GND.13 

A12 

.1uF C209 

RSVD.1 

REFCLKp 

PCI_CONN_REFN 13 

B13 

CON.PCIE_TXP0 

GND.3 REFCLK+ 

A13 

REFCLKn 

12 CON.PCIE_TXP0 

B14 

CON.PCIE_TXN0 

PETp0 REFCLK- 

A14 

12 CON.PCIE_TXN0 

B15 

PETn0 

GND.14 

A15 

B16 

CON.PCIE_RXP0 

GND.4 

PERp0 

A16 


B17 

CON.PCIE_RXN0 

PRSNT2 PERn0 

A17 


B18 

CON.PCIE_TXP1 

GND.5 

GND.15 

A18 

12 CON.PCIE_TXP1 

B19 

CON.PCIE_TXN1 

PETp1 

RSVD.3 

A19 

12 CON.PCIE_TXN1 

B20 

PETn1 

GND.16 

A20 

B21 

CON.PCIE_RXP1 

GND.6 

PERp1 

A21 


B22 

CON.PCIE_RXN1 

GND.7 

PERn1 

A22 


B23 

PETp2 

GND.17 

A23 

B24 

PETn2 

GND.18 

A24 

B25 

GND.8 

PERp2 

A25 

B26 

GND.9 

PERn2 

A26 

B27 

PCI_3V3 

PETp3 

GND.19 

A27 

B28 

PETn3 

GND.20 

A28 

B29 

GND.10 

PERp3 

A29 

B30 

RSVD.2 

PERn3 

A30 

PCI_3V3 24 

B31 

PRSNT2.2 GND.21 

A31 

B32 

GND.11 RSVD.4 

A32 


A 

EVM_5V0 

1 

3 

5 

EVM_3V3 

PCIe 4X Connector 

Connector must be less than 2.25 inches 

to board edge from key to board edge 

EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,24,26,27,28,29,30,31,32,33,34,35,36,37,38,39,41,43,44,45,46,48,49,50,51 

EVM_12V 

EVM_5V0 11,25,39,41,43,44,46,49,50,51 

Title: 


Size: B 


PCIe INTERFACE 

DWG NO 

513832-0001 

Revision: 

A 

EVM_12V 24,39,41,43,46,47,51 



5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


D D 

EVM_3V3 

EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,26,27,28,29,30,31,32,33,34,35,36,37,38,39,41,43,44,45,46,48,49,50,51 

L15 

PCI_3V3 

1 2 

R231 0.025 

PCMB104T-3R3MS-(3.3uH) 

1206 

C U56 

C 

R239 100K 1 

C369 

C355 

RT/CLK PWRGD 14 

100uF 

NO-POP 

2 

C376 0.1uF 

EVM_12V 

GND.1 

BOOT 

13 

3 

GND.2 

PH.2 

12 

R233 

4 

PVIN.1 

PH.1 

11 

10.0K 

5 

C377 C378 C353 

PVIN.2 

10uF 10uF 10uF 

6 

VIN 

EN 10 

TP22 

SS/TR 9 

1 

7 

R234 

C352 

VSENSE COMP 8 TEST POINT 

3.16K 

4.7uF 

TPS54620 

R236 

1.78K 

C342 

0.018uF 

C343 

820pF 

C339 

B 0.022uF 

TP21 

B 

EVM_3V3 

R476 0 

EVM_12V 

EVM_12V 23,39,41,43,46,47,51 


A 

PCI_3V3 

Title: 


PCI_3V3 23 


POWER SUPPLY PCI3V3 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


+ 

15 

PWRPAD 

1 

TEST POINT 

A-25

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


USB0_VBUS 

USB0_VBUS 

EVM_5V0 

U28 

1 

C60 

100uF 

TPS2065D 

2 

3 

IN1 OUT1 

IN2 OUT2 

OUT3 

GND 

L18 

8 

USB0_VBUS 

7 

6 

BLM21PG221SN1 

R412 

100K 

D D 



R360 

10K 



IMPEDANCE 


POSSIBLE, 


C110 

100uF 

HOST CONNECTOR 

SHIELD_USB0 

3 

IO1 IO2 

5 

L19 

SHIELD_USB0 

C C 

2 

NC.2 

BLM21PG221SN1 

U65 

C616 

0.1uF 

TPD2E001DRL 

USB1_VBUS 

USB1_VBUS 

EVM_5V0 

U40 

B USBB1_DRV_VBUS 


C218 

B 

100uF 

USB1_DM 

USB1_DP 

USB1_DM 

USB1_DP 

R433 

10K 



IMPEDANCE 


POSSIBLE, 


HOST CONNECTOR 

SHIELD_USB1 


USB1_DM 

USB1_DP 

U64 

USB-A connector 

L20 

SHIELD_USB1 

5 

BLM21PG221SN1 


A 

EVM_5V0 

Title: 

TPD2E001DRL 



USB INTERFACE CONNECTORS 

EVM_5V0 11,23,39,41,43,44,46,49,50,51 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


5 

5 

5 

5 

5 

5 

5 

5 

4 

GND 

VCC 1 

C152 

100uF 

MH3 

B1 

B2 

B3 

B4 

J13-2 

MHX1 

VBUS 

D- 

D+ 

GND 

MH4 

MHX2 

3 

2 

IO1 

IO2 

+ 

+ 

+ 

4 

GND 

VCC 1 

NC.2 

+ 

4 

5 

EN 

OCn 

MH1 

J13-1 

MHX1 

USB0_VBUS_CONN A1 

USB0_DM 

USB0_DM 

VBUS 

USB0_DM 

A2 

USB0_DP 

USB0_DP 

USB0_DP 

D- 

A3 

D+ 

A4 

GND 

MH2 

MHX2 

USB-A connector 

2 

3 

1 

TPS2065D 

IN1 OUT1 

IN2 OUT2 

OUT3 

GND 

L21 

8 

USB1_VBUS 

7 

6 

BLM21PG221SN1 

R437 

100K 

4 

5 

EN 

OCn 

C588 

0.1uF 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


D D 

EVM_3V3 

EVM_3V3 

C469 

R59 R58 R57 

.1uF 

NO-POP NO-POP NO-POP 

U12 

8 

VCC A0 

1 

7 

3,27,36,43,45 IIC0_SCL 

I2C0_SCL 

WP A1 

2 

6 

3,27,36,43,45 IIC0_SDA 

I2C0_SDA 

SCL A2 

3 

5 

SDA VSS 4 

C C 

CAT24C256WI-G 

R291 R292 R293 

B B 

EVM_3V3 

EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,27,28,29,30,31,32,33,34,35,36,37,38,39,41,43,44,45,46,48,49,50,51 


A 

Title: 



I2C EEPROMS 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


0 

0 

0 

A-27

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


EVM_3V3 

EVM_3V3 

EVM_3V3 

C470 

.1uF 

R49 

R60 

R61 

U13 


VDD 24 

D D 

1 

A0 

21 

RN2 

INT 

A1 

2 

RPACK4-10K 

A2 

3 

3,26,36,43,45 IIC0_SDA 

23 

SDA 

3,26,36,43,45 IIC0_SCL 

22 

SCL 

USER_SW1 

R290 

R295 

R294 

P0 

4 

USER_SW2 

10K 

28 UART2_OFF 

20 

10K 10K 

SW2 

P17 

P1 

5 

RN1 

USER_SW3 

29 IR_REMOTE_OFF 

19 

P16 

P2 

6 

USER_SW4 

USER_SW1 

AIC_EXPANSION 

18 

P15 

P3 

7 

1 

8 

5 

4 

USER_LED1 

USER_SW2 

23 PCI_SW_RESETn 

17 

P14 

P4 

8 

2 

7 

6 

3 

16 

USER_LED2 

USER_SW3 

P13 

P5 

9 

3 

6 

7 

2 

15 

USER_LED3 

USER_SW4 

P12 

P6 

10 

4 

5 

8 

1 

14 

USER_LED4 

P11 

P7 

11 

13 

LOW PROFILE DIP-4 

P10 GND 12 

SILKSCREEN: 

RPACK4-1K 

PCF8575 

USER SWITCHES 

EVM_3V3 

C C 

R299 

330 

USER_LED1 

USER_LED2 

USER_LED3 

USER_LED4 

EVM_3V3 

EVM_3V3 

B B 

VDD 24 

1 

INT 

A0 

21 

A1 

2 

A2 

3 

3,43 IIC1_SDA 

23 

SDA 

3,43 IIC1_SCL 

22 

SCL 

R282 

R281 

R280 

P0 

4 

20 

10K 

10K 

10K 

P17 

P1 

5 

19 

P16 

P2 

6 

18 

P15 

P3 

7 

17 

P14 

P4 

8 

16 

P13 

P5 

9 

15 

P12 

P6 

10 

38 THS7375_DISABLE 

14 

P11 

P7 

11 

38 THS7375_BYPASS 

13 

P10 GND 12 

THS7360_FILTER2 37 

PCF8575 

THS7360_FILTER1 37 

THS7360_BYP_SD 37 

THS7360_BYP_SF 37 

THS7360_DIS_SF 37 


A 

THS7360_DIS_SD 37 

Title: 


Page Contents: I2C EXPANDER 

EVM_3V3 

Revision: 

EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,26,28,29,30,31,32,33,34,35,36,37,38,39,41,43,44,45,46,48,49,50,51 

Size: B 

DWG NO 513832-0001 

A 

Date: 


2 

5 

6 

7 

8 

1 

2 

3 

4 

R298 

330 

R297 

330 

R296 

330 

DS2 

DS3 

DS4 

DS5 

LED_GRN LED_GRN LED_GRN LED_GRN 

C468 

.1uF 

R278 

R277 

R276 

U9 



5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


EVM_3V3 

EVM_3V3 

EVM_3V3 

C792 

+ C367 

R238 

R240 

1uF 

10uF 

10K 

10K 

D D 

U57 

15 

VCC FORCEOFF 

16 

DB9M 

FORCEON 12 

11 

10 

5 

UART2_TXD 

3,42 UART2_TXD 

11 

T_IN T_OUT 

13 

9 

4 

8 

3 

7 

UART2_RXD 

3,41 UART2_RXD 

9 

R_OUT R_IN 8 

2 

6 

1 

P10 

27 UART2_OFF 

1 

EN INVALID 10 

R460 

10K 

C C 

2 

C1+ 

C2+ 

5 

C379 

C373 

1uF 

1uF 

4 

C1- 

C2- 

6 

V+ 

3 

14 

GND 

V- 

7 

C794 

C793 

MAX3221CPWRG4 

1uF 

1uF 

B B 

EVM_3V3 

EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,26,27,29,30,31,32,33,34,35,36,37,38,39,41,43,44,45,46,48,49,50,51 


A 

Title: 



RS232 INTERFACE 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


A-29

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


D D 

EVM_3V3 

EVM_3V3 

C796 

0.1uF 

R474 

R473 

10K 100 

U61 

3 

3,41 UART1_RXD 

4 

2 

1 

2 

SN74LVC1G125 

C C 

U60 

C386 

10uF 6.3V 

TSOP34840 

IR_REMOTE_OFF 27 

R245 

10K 

B B 

EVM_3V3 

EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,26,27,28,30,31,32,33,34,35,36,37,38,39,41,43,44,45,46,48,49,50,51 


A 

Title: 



INFRA-RED RECIEVER 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


+ 

3 

1 

5 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


EVM_3V3 

C790 

NO-POP 

U66 

D D 

4 

VIN VOUT2 

3 

MMC_POW 

5 

ON_OFF VOUT1 

2 

R459 51K 

6 

R1_C1 R2 

1 

R458 

FDC6331L 

51K 

R457 

R466 

R462 

51K 

R464 

51K 

R467 

51K 

R469 

51K 

R470 

51K 

R461 

51K 

+ C787 

10UF 

C791 

0.1uF 

SD/MMC Connector 6 in 1 

MMC+, MMCMobile, SD, 

MMC, miniSD, RS-MMC 

P9 MHC-W21-601 

C C 

MMC_DAT3 

MMC_DAT3 

1 

MMC_CMD 

#1_MMC+/MMCM/RSMMC/MMC/SD 

MMC_CMD 

2 


3 


4 

MMC_CLK 


MMC_CLK 

5 


6 

MMC_DAT0 


MMC_DAT0 

7 

MMC_DAT1 


MMC_DAT1 

8 

MMC_DAT2 

#8_MMC+/MMCM/SD 

MMC_DAT2 

9 

#9_MMC+/MMCM/SD 

10 

#10_MMC+/MMCM 

11 

#11_MMC+/MMCM 

12 

#12_MMC+/MMCM 

13 

#13_MMC+/MMCM 

16 

R463 R465 R468 

#1_miniSD 

17 


EVM_3V3 

#2_miniSD 

18 

#3_miniSD 

19 

#4_miniSD 

20 

#5_miniSD 

21 

#6_miniSD 

22 

#7_miniSD 

23 

#8_miniSD 

B 24 

B 

R471 R472 

#9_miniSD 

25 

10K 10K 

#10_miniSD 

26 

#11_miniSD 

27 

GND1 

28 

GND2 

MMC_SD_WP 

MMC_SD_WP 

14 

MMC_SD_CD 

SD_WP 

MMC_SD_CD 

15 

CD 

EVM_3V3 

EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,26,27,28,29,31,32,33,34,35,36,37,38,39,41,43,44,45,46,48,49,50,51 


A 

Title: 



SD/MMC INTERFACE 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


3 

3 

3 

3 

3 

3 

3 

0 

3 

3 

0 

A-31

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


D D 

EVM_3V3 

R345 

10K 

EVM_3V3 

C509 

U20 

0.1uF 

1 

SPI_SCLK 

EVM_3V3 

EVM_3V3 

HOLD SCLK 16 

SPI_SCLK 3,41 

2 

SPI_MOSI 

VCC DIO 15 

SPI_MOSI 3,41 

EVM_3V3 

3 

R348 

NC.3 NC.14 

14 

R344 

C 10K 

10K 

4 

C 

C511 

NC.4 NC.13 

13 

.1uF 

5 

NC.5 NC.12 

12 

6 

NC.6 NC.11 

11 

SPI_CS0 

3,41 SPI_CS0 

2 

4 

7 

CS GND 10 


SPI_BOOTn 

SPI_BOOTn 

EVM_3V3 

B B 

EVM_3V3 

EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,26,27,28,29,30,32,33,34,35,36,37,38,39,41,43,44,45,46,48,49,50,51 


A 

Title: 



SPI EEPROM 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


6 

1 

3 

5 

U21 

SPI_MISO 

3,41 SPI_MISO 

8 

DO WP 9 

R307 

NO-POP 

W25X32VSFIG 

R306 

10K 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


EVM_3V3 

D D 

EVM_3V3 

EVM_3V3 

EVM_3V3 

R359 

1 

R358 

NC-1 

GND4 

48 

10K 

2 

GPMC_D15 

EVM_3V3 

NC-2 

I/O15 

47 

GPMC_D15 6,41 

10K 

3 

GPMC_D14 

NC-3 

I/O14 

46 

GPMC_D14 6,41 

4 

GPMC_D13 

GPMC_D13 6,41 

C528 

NC-4 

I/O13 

45 

5 

GPMC_D7 

GPMC_D7 6,41 

.1uF 

NC-5 

I/O7 

44 

6 

GPMC_D6 

GPMC_D6 6,41 

GPMC_WAIT 

NC-6 

I/O6 

43 


7 

GPMC_D5 

GPMC_D5 6,41 

GPMC_OEN_REN 

R/B 

I/O5 

42 

GPMC_D4 

6,41 GPMC_OEN_REN 

8 

GPMC_D4 6,41 

GPMC_ CS0 

RE 

I/O4 

41 

GPMC_D12 

6,41 GPMC_ CS0 

2 

4 

9 

CE 

I/O12 

40 

GPMC_D12 6,41 

C 10 

NC-7 

VCC4 

39 

C 

U25 

11 


NC-8 

23-NC 38 

12 

VCC 

VCC3 

37 

13 

GND1 

GND3 

36 

14 

NC-9 

22-NC 35 

15 

GPMC_BE0N_CLE 

NC-10 

VCC2 

34 

GPMC_D11 

6,41 GPMC_BE0N_CLE 

16 

GPMC_D11 6,41 

GPMC_ADVN_ALE 

CLE 

I/O11 

33 

GPMC_D3 

6,41 GPMC_ADVN_ALE 

17 

GPMC_D3 6,41 

GPMC_WEN 

ALE 

I/O3 

32 

GPMC_D2 

6,41 GPMC_WEN 

18 

GPMC_D2 6,41 

GPMC_WPN 

WE 

I/O2 

31 

GPMC_D1 

6,41 GPMC_WPN 

19 

GPMC_D1 6,41 

NAND_BOOTn 

WP 

I/O1 

30 

GPMC_D0 

NAND_BOOTn 

20 

NC-11 

I/O0 

29 

GPMC_D0 6,41 

21 

GPMC_D10 

NC-12 

I/O10 

28 

GPMC_D10 6,41 

22 

GPMC_D9 

NC-13 

I/O9 

27 

GPMC_D9 6,41 

23 

GPMC_D8 

NC-14 

I/O8 

26 

GPMC_D8 6,41 

24 

NC-15 

GND2 

25 

U24 

ONFI 

Micron NAND 

B B 

EVM IS SUPPORTED WITH MICRON MT29F2G16AADWP:D 

EVM_3V3 

EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,26,27,28,29,30,31,33,34,35,36,37,38,39,41,43,44,45,46,48,49,50,51 


A 

Title: 



NAND FLASH 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


6 

MH2 

MH1 

MH2 

MH1 

C517 0.01 

C522 

0.01 

1 

3 

5 

C527 0.01 

A-33

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


U19A 

C476 18 pF 

GMII0_TCLK 

PHY.MTCLK 

CLK_IN/XTAL1 

22 

Y1 

GMII0_TCLK 

R319 22 

75 

GMII0_GMTCLK 

GMII0_GMTCLK 

R314 0 

PHY.GMTCLK 

TXCLK 

77 

25MHz 

GMII0_TXEN 

GTX_CLK/PMA_TX_CLK/TXC 

GMII0_TXEN 

79 

TX_EN/TXD[8]/TX_CTL/TXD[4] 

XTAL2 

23 

C477 18 pF 

R313 10K 78 

TX_ER/TXD[9] 

TRD[0]P 25 

TRD[0]P 35 

57 

SYS_CLK 

TRD[0]N 26 

TRD[0]N 35 

D TRD[1]P 35 

GMII0_TXD7 

TRD[1]P 28 

D 

GMII0_TXD7 

3 

TRD[1]N 35 

GMII0_TXD6 

GMII0_TXD6 

TXD[7] 

TRD[1]N 29 

2 

TRD[2]P 35 

GMII0_TXD5 

GMII0_TXD5 

TXD[6] 

TRD[2]P 34 

1 

TRD[2]N 35 

GMII0_TXD4 

GMII0_TXD4 

TXD[5] 

TRD[2]N 35 

84 

TRD[3]P 35 

GMII0_TXD3 

GMII0_TXD3 

TXD[4] INPUTS 

TRD[3]P 37 

83 

TRD[3]N 35 

GMII0_TXD2 

GMII0_TXD2 

TXD[3] 

TRD[3]N 38 

82 

GMII0_TXD1 

GMII0_TXD1 

TXD[2] 

81 

GMII0_TXD0 

GMII0_TXD0 

TXD[1] 

80 

TXD[0] 

GMII0_RCLK 

GMII0_RCLK 

R324 22 

PHY.MRCLK 

72 

GMII0_RXDV 

GMII0_RXDV 

R338 22 

PHY.MRXDV 

RXCLK/PMA_RX_CLK[0]/RXC 

69 

GMII0_RXER 

GMII0_RXER 

R333 22 

PHY.MRXER 

RX_DV/RXD[8]/RX_CTL/RXD[4] 

70 

RX_ER/RX[9] 

RN11 RPACK8-22 

GMII0_RXD7 

GMII0_RXD7 

16 1 

PHY.MRXD7 

59 

GMII0_RXD6 

PHY.MRXD6 

RXD[7] 

GMII0_RXD6 

15 2 

60 

GMII0_RXD5 

PHY.MRXD5 

RXD[6] 

GMII0_RXD5 

14 3 

61 

GMII0_RXD4 

PHY.MRXD4 

RXD[5] 

LED_1000/SPEED_1000 

49 

GMII0_RXD4 

13 4 

62 

GMII0_RXD3 

GMII0_RXD3 

PHY.MRXD3 

RXD[4] 

12 5 

65 

ENET_LED_LINK 35 

GMII0_RXD2 

GMII0_RXD2 

PHY.MRXD2 

RXD[3] OUTPUTS 

LED_LNK/PAUSE 50 

11 6 

66 

GMII0_RXD1 

PHY.MRXD1 

RXD[2] 

C GMII0_RXD1 

10 7 

67 

C 

GMII0_RXD0 

GMII0_RXD0 

PHY.MRXD0 

RXD[1] 

PRES 51 R334 

9 8 

68 

RXD[0] 

1K 1% 

GMII0_CRS 

GMII0_CRS 

R325 22 

PHY.MCRS 

74 

GMII0_COL 

GMII0_COL 

R329 22 

PHY.MCOL 

CRS/COMMA 

73 

COL/PMA_RX_CLK[1] 

R354 22 

PHY.MDCLK 

4,43 MDIO_MDCLK 

55 

R355 22 

PHY.MDIO 

MDC 

4,43 MDIO_MDIO 

54 

MDIO 

R318 

14 ENET_INTn 

53 

MDINTn 

RSET 

32 

13,14,36,42 RSTOUTn 

24 

RESETn 

6.34K 1% 

MAC_IF_SEL[2] 

18 

R478 

MAC_IF_SEL[1] 

17 

R477 

R479 

10K 

MAC_IF_SEL[0] 

16 

10K 

10K 

40 

EVM_3V3 

PHYA[4] 

41 

EVM_3V3 

R301 R302 R303 

PHYA[3] 

42 

PHYA[2] 

43 

PHYAD[1]/LED_100 

44 

PHYAD[0]/LED_TXRX 

TMS/SYS_CLK_ENn 

13 

B B 

TCK 5 

R310 

TDO 15 

10K 

TDI/LPED_ENn 

14 

TRSTz 

12 

EVM_3V3 

ET1011C 

R342 10K 

R315 

NO-POP 

R343 NO-POP 

ENET_LED_RX 35 


A 

EVM_3V3 

Title: 


EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,26,27,28,29,30,31,32,34,35,36,37,38,39,41,43,44,45,46,48,49,50,51 


ETHERNET INTERFACE 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


4 

4 

4 

4 

4 

4 

4 

4 

4 

4 

4 

4 

4 

4 

4 

4 

4 

4 

4 

4 

4 

4 

4 

4 

0 

0 

0 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


EVM_3V3 

PHY_VDD_1V0 

U19B 

6 

VDD.1 

DVDDIO.1 

4 

C501 C507 C498 C506 C493 C483 

19 

VDD.2 

DVDDIO.2 

52 

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 

48 

D VDD.3 

DVDDIO.3 

58 

D 

56 

VDD.4 

DVDDIO.4 

64 

63 

EVM_3V3 

VDD.5 

DVDDIO.5 

71 

C485 C484 C500 C502 C508 

EVM_3V3 

DVDDIO.6 

76 

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 

7 

NC.7 

VDD_REG 45 

8 

NC.8 

9 

NC.9 

10 

NC.10 

CTRL_1V0 

47 

1 

B 

E 3 

11 

NC.11 

PHY_AVDD_1V0 

CTRL_2V5 

46 

C519 C524 

0.1uF 33uF 

U27 

BCP69T1 

20 

PHY_VDD_2V5 

AVDDL.1 

27 

PHY_1V0 PHY_AVDD_1V0 

AVDDL.2 

30 

AVDDL.3 

AVDDH.1 

21 

33 

AVDDL.4 

AVDDH.2 

31 

L9 

36 

AVDDL.5 

39 

C490 C499 C504 C482 C492 

AVDDL.6 

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 

ET1011C 

BLM41P750SPT 

C518 

C523 

C513 C512 

C C 

C494 C487 

0.1uF 

33uF 

0.1uF 33uF 

0.1uF 0.1uF 

PHY_VDD_1V0 

L10 

BLM41P750SPT 

C479 C36 

0.1uF 33uF 

EVM_3V3 

B C521 C526 

B 

0.1uF 33uF 

1 

B 

PHY_VDD_2V5 

E 3 

PHY_2V5 

PHY_VDD_2V5 

2 

4 

C 

TAB 

85 

POWER_PAD 

2 

4 

C 

TAB 

PHY_VDD_2V5 35 

U26 

BCP69T1 

L11 

EVM_3V3 

BLM41P750SPT 

EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,26,27,28,29,30,31,32,33,35,36,37,38,39,41,43,44,45,46,48,49,50,51 

C520 

C525 

C475 C32 

0.1uF 

33uF 

0.1uF 33uF 


A 

Title: 



ETHERNET - POWER 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


A-35

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


PHY_VDD_2V5 

PHY_VDD_2V5 34 

EVM_3V3 

D EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,26,27,28,29,30,31,32,33,34,36,37,38,39,41,43,44,45,46,48,49,50,51 

D 

PHY_VDD_2V5 

J10 

L16 BLM18AG601SN1 

2 

VCC 

TRD[0]P 

33 TRD[0]P 

9 

T0+ 

33 

TRD[0]N 

TRD[0]N 

33 

TRD[2]N 

TRD[2]N 

10 

TRD[1]P 

T0- 

33 TRD[1]P 

7 

T1+ 

TRD[1]N 

33 TRD[1]N 

8 

T1- 

TRD[2]P 

33 TRD[2]P 

5 

T2+ 

C 6 

C 

TRD[3]P 

T2- 

33 TRD[3]P 

3 

T3+ 

TRD[3]N 

33 TRD[3]N 

4 

T3- 

D1 

LED1-A 

D2 

LED1-K 

75 75 75 75 

R351 

49.9 1% 

R356 

49.9 1% 



IMPEDANCE 


POSSIBLE, 


D3 

D4 

LED2-AK 

LED2-KA 

6605814_6 

B C510 

C505 

C503 

C496 

B 

0.01uF 

0.01uF 

0.01uF 

0.01uF 

EVM_3V3 

33 

ENET_LED_LINK 

EVM_3V3 

U68 

33 ENET_LED_RX 

1 

4 

2 


A 

74LVC1G08 

Title: 



ETHERNET - OUTPUT CONNECTOR 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


1 

2 

3 

6 

4 

5 

7 

8 

11 

12 

SHLD1 

SHLD2 

R339 

49.9 1% 

R346 

49.9 1% 

R330 

49.9 1% 

R335 

49.9 1% 

R320 

49.9 1% 

R326 

49.9 1% 

1 

GND 

R357 0ohm 1/4W 

R64 

NO-POP 

R73 

R321 221 

C801 

0.1uF 

3 

5 

R347 221 

0 



C449 

NO-POP 

EVM_3V3 

GND_AIC 

GND_AIC 

R255 

NO-POP 

C452 

.1uF R258 

2.2K 

GND_AIC 

GND_AIC 

13,14,33,42 

RSTOUTn 

B_AIC_BCLK 

B_AIC_WCLK 

B_AIC_DIN 

B_AIC_DOUT 

3,26,27,43,45 IIC0_SDA 

3,26,27,43,45 IIC0_SCL 

C12 C13 

.1uF 10uF 

C455 

.1uF 

B_AIC_BCLK 

B_AIC_WCLK 

B_AIC_DIN 

B_AIC_DOUT 

B_AIC_MCLK 

EVM_3V3 

C443 .1uF 

R22 10 AIC_BCLK 

R23 10 AIC_WCLK 

R24 10 AIC_DIN 

R25 10 AIC_DOUT 

EVM_3V3 

EVM_3V3 

EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,26,27,28,29,30,31,32,33,34,35,37,38,39,41,43,44,45,46,48,49,50,51 

EVM_3V3 

C10 

.1uF 

C457 

.1uF 

C456 

.1uF 

GND_AIC 

EVM_3V3 

L2 BLM21PG221SN1D 

C8 

C6 C7 

C5 

.1uF 10uF .1uF 

.1uF 

U2 TLV320AIC3106 

DRVDD.1 

16 

GND_AIC 

DRVDD.2 

17 

36 

DVDD.1 

DRVDD.3 

24 

42 

44 

3 

4 

DVSS 

IOVDD 

LINE1L+ 

DRVSS.1 

DRVSS.2 

20 

21 

AVDD_DAC 25 

AVSS_DAC 26 

AVSS_ADC 15 

GND_AIC 

GND_AIC 

GND_AIC 

HPLOUT 

18 

HPLCOM 19 

GND_AIC GND_AIC 

8 

9 

10 

14 

11 

12 

13 

33 

38 

39 

40 

41 

2 

1 

LINE2R+ 

MONO_LO+ 

MONO_LO- 

LINE2R- 

MIC3R 

MIC3L 

MICDET 

MICBIAS 

RESET 

BCLK 

WCLK 

DIN 

DOUT 

SDA 

SCL 

HPROUT 

23 

HPRCOM 22 

RIGHT_LO- 

LEFT_LO+ 

RIGHT_LO+ 

LINE1L- 

LEFT_LO- 

5 

LINE1R+ 

6 

LINE1R- 

7 

LINE2L+ 

LINE2L- 

GPIO1 

GPIO2 

MFP0 

MFP1 

MFP2 

MFP3 

27 

28 

29 

30 

31 

32 

35 

34 

45 

46 

47 

48 

1 

TP3 

TEST POINT 

TP4 

TEST POINT 

R256 100 

C448 .047uF 

EVM_3V3 

GND_AIC 

GND_AIC 

GND_AIC 

SCART_AUDIO_OUT_R 38 

SCART_AUDIO_OUT_L 38 

1 

2 

4 

3 

P3 

Line Out 

MCLK 37 

EVM_3V3 


AIC3106 AUDIO INTERFACE 

R29 22 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

GND_AIC 


2 

2 

2 

2 

2 

+ 

+ 

49 

TPAD 

5 

6 

Line In 

3 

4 

2 

1 

P4 

Mic In 

3 

4 

2 

1 

P5 

R257 

330 

R259 

C450 .1uF 

R26 

NO-POP 

U3 

IN 

TPS77018DBVT 

C11 

4.7uF 

C3 

.1uF 

C2 

10uF 

L1 BLM21PG221SN1D 

C451 33uF,6.3V 

R254 

20K 

P2 Headphone Out 

1 

2 

4 

3 

R247 

20K 

1 

R248 100 

R246 

20K 

R253 

20K 

43 

SELECT 

R265 

NO-POP 

R266 

NO-POP 

R267 

NO-POP 

R16 

NO-POP 

R271 

20K 

R270 

20K 

R18 

NO-POP 

R268 

2K 

C14 

U6 

.1uF 

1 

EN VCC 4 

ISOLATE GROUNDS 


2 

R21 22 

AND CONNECT AT 

GND OUT 

3 

SINGLE LOCATION 

24.576 MHz 

IN THE GROUND PLANE 

Title: 


0 

+ 

5 

6 

5 

6 

5 

6 

+ 

R269 

2K 

1 

2 

3 

GND 

OUT 

5 

ENn 

NC/FB 4 

C445 33uF,6.3V 

+ 

L3 

BLM21PG221SN1D 

C15 

.1uF 

C9 

1uF 

C458 

.1uF 

C444 .047uF 

R19 

NO-POP 

R17 

2K 

A-37

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


RFOUT 

IOUTD 

ALT_IOUTD 38 

R6 75 

1 

J3 

F TYPE 

5-1814400-1 

101515-0001R 

R264 0 

SCART_COMPOSITE 38 

D R288 

S-VIDEO_LUMA 

D 

3 4 

COMPOSITE 

IOUTE 

ALT_IOUTE 38 

EVM_3V3 

R287 

37.4 

S-VIDEO Y 

C459 

C460 

C461 

J2 

0.1uF 0.01uF 

1uF 

R 

1 

R 

11 

NC.11 

6 

G 

Gnd.6 

2 

G 

R273 0 

U4 

12 

NC.12 

ALT_IOUTF 38 

7 

R7 75 

Gnd.7 

C 1 

C 

R43 0 

SD1_IN SD1_OUT 

20 

3 

B 

IOUTF 

B 

13 

H_Sync 

8 

2 

R8 75 

Gnd.8 

R286 


19 

4 

NC.4 

14 

V_Sync 

37.4 

9 

S-VIDEO C 

NC.9 

3 


18 R9 75 

5 

Gnd.5 

15 

NC.15 

10 

27 THS7360_FILTER2 

4 

FILTER2 DIS_SD 17 

Gnd.10 

HD15 

IOUTA 

G/Y 

27 

THS7360_FILTER1 

B 9 

B 

SF3_IN SF3_OUT 

12 

R11 75 

IOUOTB 

B/Pb 

IOUTC 

R/Pr 

R283 

37.4 

JACK ORDER MUST BE RED,BLUE, GREEN FOR COMPONENT CABLING 


A 

27 THS7360_BYP_SD 

Title: 


27 THS7360_BYP_SF 

Page Contents: ANALOG VIDEO OUT 

27 THS7360_DIS_SF 

EVM_3V3 

Revision: 

27 THS7360_DIS_SD 

Size: B 

DWG NO 513832-0001 

A 

EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,38,39,41,43,44,45,46,48,49,50,51 


9 

9 

9 

9 

9 

9 

9 

2 

3 

4 

5 

R275 0 

J4 RCA JACK 

2 

COMPOSITE 

749181-1 

P1 

37.4 

1 

2 

5 7 6 

5 

VS+ 

GND 16 

R10 75 

R44 0 

6 

7 

8 

FILTER1 

SF1_IN 

SF2_IN 

DIS_SF 

SF1_OUT 

SF2_OUT 

15 

14 

13 

R263 75 

J5 

RCA JACK(GREEN) 

2 

R45 0 

10 

BYP_SD 

R262 75 

J6 

RCA JACK(BLUE) 

2 

R12 75 

J7 

RCA JACK(RED) 

R261 75 

2 

4 

1 

3 

4 

1 

3 

4 

1 

3 

4 

1 

3 

+ 

R41 0 

C1 330uF 

R42 0 

R274 0 

R285 

37.4 

R284 

37.4 

THS7360 

BYP_SF 

11 

R46 0 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


J9 

36 SCART_AUDIO_OUT_R 

1 

AUDIO_OUT(R) 

D AUDIO_IN(R) 

2 

D 

36 SCART_AUDIO_OUT_L 

3 

AUDIO_OUT(L/MONO) 

AUDIO_GND 4 

U8 

5 

ALT_IOUTD SCART_GRN 

37 ALT_IOUTD 

1 

CH1_IN CH1_OUT 

14 

R39 75 

BLUE_GND 

AUDIO_IN(L/MONO) 

6 

ALT_IOUTE SCART_BLUE 

37 ALT_IOUTE 

2 


13 

R33 75 

7 

BLUE_UP 

ALT_IOUTF SCART_RED/SVIDEO_C 

STATUS 8 

37 ALT_IOUTF 

3 


12 

R31 75 

9 

GRN_GND 

IOUTG R38 0 

R28 75 

IOUTG 

4 


11 

CLK/DATA 10 

11 

R272 

EVM_3V3 

GRN_UP 

5 

GND 

VS+ 

10 

37.4 

RESV 12 

6 

DISABLE BYPASS 9 

13 

RED_GND 

C C 

7 

NC.7 

NC.8 

8 

C465 

GND_12_16 

14 

C464 

C463 

0.1uF 0.01uF 

1uF 

15 

RED_UP 

THS7375 

SEL_RGB_COMPOSITE 16 

17 

CV_GND_19_20 

BLNK_GND_16 

18 

37 SCART_COMPOSITE 

19 

COMPOSITE_VIDEO_OUT 

21 

COMPOSITE_VIDEO_IN 20 

GND_8_10 

SCART21 

B 27 THS7375_DISABLE 

B 

27 

THS7375_BYPASS 

EVM_3V3 

EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,39,41,43,44,45,46,48,49,50,51 


A 

Title: 



ANALOG VIDEO OUT SCART 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


9 

A-39

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


J17 

10 VIN0_D0 

VIN0_D0 

2 

2 1 

1 

4 

VIN0_D2 

4 3 

3 

10 VIN0_D2 

6 

VIN0_D9 

6 5 

5 

10 VIN0_D9 

8 

VIN0_CLK1 

8 7 

7 

VIN0_CLK1 10 

10 

VOUT0_G_Y_YC2 

10 9 

9 

VIN0_D1 

D 10 VOUT_YC2 

12 

VOUT0_G_Y_YC6 

12 11 

11 

VIN0_D1 10 

VIN0_D4 

D 

10 VOUT_YC6 

14 

14 13 

13 

VIN0_D4 10 

16 

10 VOUT_CR4 

VOUT0_R_CR4 

16 15 

15 

18 

VIN0_D11 

VIN0_D6 

18 17 

17 

VIN0_D11 10 

10 VIN0_D6 

20 

VIN0_D5 

20 19 

19 

VIN0_D5 10 

22 

10 VIN0_D8 

VIN0_D8 

22 21 

21 

24 

VIN0_D12 

VIN0_D12 10 

VIN0_D3 

24 23 

23 

10 VIN0_D3 

26 

VIN0_D10 

26 25 

25 

VIN0_D10 10 

28 

10 VIN0_D7 

VIN0_D7 

28 27 

27 

30 

VIN0_D14 

VIN0_D14 10 

10 VOUT_YC4 

VOUT0_G_Y_YC4 

30 29 

29 

32 

VIN0_D13 

32 31 

31 

VIN0_D13 10 

34 

10 VOUT_C8 

VOUT0_B_CB_C8 

34 33 

33 

36 

VIN0_D15 

VIN0_D15 10 

10 VOUT_YC5 

VOUT0_G_Y_YC5 

36 35 

35 

38 

VOUT0_CLK 

38 37 

37 

VOUT0_CLK 10 

40 

VOUT0_B_CB_C6 

40 39 

39 

VOUT0_G_Y_YC8 

EVM_12V 

10 VOUT_C6 

42 

VOUT_YC8 10 

VOUT0_B_CB_C5 

42 41 

41 

VOUT0_G_Y_YC7 

EVM_3V3 

10 VOUT_C5 

44 

44 43 

43 

VOUT_YC7 10 

46 

46 45 

45 

48 

EVM_5V0 

48 47 

47 

50 

50 49 

49 

52 

52 51 

51 

54 

54 53 

53 

56 

56 55 

55 

58 

VOUT0_B_CB_C3 

58 57 

57 

VOUT0_B_CB_C9 

C 10 VOUT_C3 

60 

60 59 

59 

VOUT_C9 10 

C 

10 VOUT_C7 

VOUT0_B_CB_C7 

62 

VOUT0_R_CR2 

62 61 

61 

VOUT_CR2 10 

64 

VOUT0_G_Y_YC3 

64 63 

63 

10 VOUT_YC3 

66 

VOUT0_R_CR6 

VOUT0_G_Y_YC9 

66 65 

65 

VOUT_CR6 10 

10 VOUT_YC9 

68 

VOUT0_R_CR5 

68 67 

67 

VOUT_CR5 10 

70 

VIN0_CLK0 

70 69 

69 

10 VIN0_CLK0 

72 

VOUT0_R_CR9 

VOUT0_B_CB_C4 

72 71 

71 

VOUT_CR9 10 

10 VOUT_C4 

74 

TSI5_BYTSTRT 

74 73 

73 


76 

VOUT0_B_CB_C2 

76 75 

75 

10 VOUT_C2 

78 

TSI5_PACERR 

VOUT0_R_CR3 

78 77 

77 


10 VOUT_CR3 

80 

TSI7_PACERR 

80 79 

79 


82 

10 TSI5_DATA 

TSI5_DATA 

82 81 

81 

84 

TSO1_DATA 

TSO1_DATA 10 

TSI5_PACVAL 

84 83 

83 

10 TSI5_PACVAL 

86 

TSI7_PACVAL 

86 85 

85 


88 


TSI1_PACVAL 

88 87 

87 

90 

TSO1_PACVAL 

TSO1_PACVAL 10 

10 TSI7_DATA 

TSI7_DATA 

90 89 

89 

92 

TSO1_DCLK 

92 91 

91 

TSO1_DCLK 10 

94 

10 TSI5_DCLK 

TSI5_DCLK 

94 93 

93 

96 

TSI6_DATA 

TSI6_DATA 10 

10 VOUT_CR7 

VOUT0_R_CR7 

96 95 

95 

98 

TSI3_BYTSTRT 

98 97 

97 


100 

10 VOUT_CR8 

VOUT0_R_CR8 

100 99 

99 

102 

TSI2_BYTSTRT 


B 10 TSI7_BYTSTRT 

TSI7_BYTSTRT 

102 101 

101 

104 

TSI4_DATA 

TSI4_DATA 10 

B 

104 103 

103 

106 

10 TSI1_BYTSTRT 

TSI1_BYTSTRT 

106 105 

105 

108 

TSI0_DATA 

TSI0_DATA 10 

10 TSI7_DCLK 

TSI7_DCLK 

108 107 

107 

110 

TSI6_DCLK 

110 109 

109 

TSI6_DCLK 10 

112 

10 TSI1_DCLK 

TSI1_DCLK 

112 111 

111 

114 

MSP430_SCL 

PM_I2C_SCL 41,43,44,45 

10 TSI1_DATA 

TSI1_DATA 

114 113 

113 

116 

MSP430_SDA 

116 115 

115 

PM_I2C_SDA 41,43,44,45 

118 


TSO1_BYTSTRT 

118 117 

117 

120 

120 119 

119 

122 

G2 G1 

121 

124 

G4 G3 

123 

126 

G6 G5 

125 

128 

G8 G7 

127 

QSH-060-01-x-D-A 

EVM_5V0 

EVM_5V0 11,23,25,41,43,44,46,49,50,51 


A 

EVM_3V3 

Title: 


EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,38,41,43,44,45,46,48,49,50,51 

EVM_12V 

Page Contents: VIDEO/TRANSPORT STREAMS 

EVM_12V 23,24,41,43,46,47,51 

Revision: 

Size: B 

DWG NO 512862-0001 

A 

Date: 



5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


D D 

J16 


TSI3_PACVAL 

2 

TSI6_PACERR 

2 1 

1 


4 

TSI4_DCLK 

4 3 

3 

10 TSI4_DCLK 

6 

TSI2_PACERR 

TSI3_DATA 

6 5 

5 


10 TSI3_DATA 

8 

TSI0_PACVAL 

8 7 

7 


10 

TSI2_DCLK 

10 9 

9 

10 TSI2_DCLK 

12 

TSI2_PACVAL 

TSI2_DATA 

12 11 

11 


10 TSI2_DATA 

14 

TSI0_PACERR 

14 13 

13 


16 

TSI6_BYTSTRT 

16 15 

15 


18 

TSI0_DCLK 

TSI6_PACVAL 

18 17 

17 

TSI0_DCLK 10 


20 

TSO0_DCLK 

20 19 

19 

TSO0_DCLK 10 

22 

10 TSI4_PACERR 

TSI4_PACERR 

22 21 

21 

24 

TSI0_BYTSTRT 



TSI4_BYTSTRT 

24 23 

23 

26 

TSO0_DATA 

26 25 

25 

TSO0_DATA 10 

28 

10 TSI3_PACERR 

TSI3_PACERR 

28 27 

27 

30 

TSO0_BYTSTRT 

TSO0_BYTSTRT 10 

VLYNQ_RXD1 

30 29 

29 

TSO0_PACERR 

VLYNQ_RXD1 

32 

32 31 

31 

TSO0_PACERR 10 

34 

VLYNQ_TXD1 

34 33 

33 

VLYNQ_SCRUN 

C VLYNQ_TXD1 

36 

VLYNQ_SCRUN 6 

C 


TSO1_PACERR 

36 35 

35 

38 

TSO0_PACVAL 

38 37 

37 

TSO0_PACVAL 10 

40 

VLYNQ_TXD3 

40 39 

39 

VLYNQ_TXD2 

VLYNQ_TXD3 

42 

VLYNQ_TXD2 6 

VLYNQ_RXD2 

42 41 

41 

VLYNQ_CLOCK 

VLYNQ_RXD2 

44 

44 43 

43 

VLYNQ_CLOCK 6 

46 


TSI4_PACVAL 

46 45 

45 

48 

TSI1_PACERR 


VLYNQ_RXD3 

48 47 

47 

TSI3_DCLK 

VLYNQ_RXD3 

50 

50 49 

49 

TSI3_DCLK 10 

52 

VLYNQ_TXD0 

52 51 

51 

VLYNQ_RXD0 

VLYNQ_TXD0 

54 

54 53 

53 

VLYNQ_RXD0 6 

56 

56 55 

55 

58 

58 57 

57 

60 

60 59 

59 

62 

G2 G1 

61 

64 

G4 G3 

63 

QSH-030-01-x-D-A 

B B 


A 

Title: 



VLYNQ/TRANSPORT STREAMS 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


6 

6 

6 

6 

6 

6 

A-41

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


J18 

39,43,44,45 PM_I2C_SCL 

MSP430_SCL 

2 

2 1 

1 

4 

MSP430_SDA 

4 3 

3 

39,43,44,45 PM_I2C_SDA 

6 

GPMC_CS3 

6 5 

5 

GPMC_ CS3 6 

8 

GPMC_CS0 

8 7 

7 

GPMC_ CS0 6,32 

10 

D 10 9 

9 

GPMC_CS2 

D 

12 

12 11 

11 

GPMC_ CS2 6 

14 

GPMC_ CS1 

14 13 

13 

GPMC_ CS1 6 

16 

GPMC_CS4 

16 15 

15 

GPMC_WEN 

GPMC_ CS4 

18 

GPMC_WEN 6,32 

GPMC_A8 

18 17 

17 

GPMC_CS5 

GPMC_A8 

20 

20 19 

19 

GPMC_ CS5 6 

22 

GPMC_A7 

22 21 

21 

GPMC_OEN_REN 

GPMC_A7 

24 

GPMC_OEN_REN 6,32 

GPMC_A3 

24 23 

23 

GPMC_BE1N 

GPMC_A3 

26 

26 25 

25 

GPMC_BE1N 6 

28 

GPMC_A2 

28 27 

27 

GPMC_A5 

GPMC_A2 

30 

GPMC_A5 6 

GPMC_A1 

30 29 

29 

GPMC_A4 

GPMC_A1 

32 

32 31 

31 

GPMC_A4 6 

34 

GPMC_A0 

34 33 

33 

GPMC_A9 

GPMC_A0 

36 

GPMC_A9 6 

GPMC_DIR 

36 35 

35 

GPMC_A10 

GPMC_DIR 

38 

38 37 

37 

GPMC_A10 6 

40 


GPMC_WAIT 

40 39 

39 

42 

GPMC_A11 

GPMC_A11 6 

GPMC_WPN 

42 41 

41 

GPMC_D0 

EVM_12V 6,32 GPMC_WPN 

44 

44 43 

43 

GPMC_D0 6,32 

46 

EVM_3V3 

46 45 

45 

48 

48 47 

47 

50 

EVM_5V0 

50 49 

49 

52 

52 51 

51 

54 

54 53 

53 

56 

56 55 

55 

C 58 

C 

GPMC_A6 

58 57 

57 

GPMC_D2 

GPMC_A6 

60 

60 59 

59 

GPMC_D2 6,32 

GPMC_BE0N_CLE 

GPMC_D5 

6,32 GPMC_BE0N_CLE 

62 

62 61 

61 

GPMC_D5 6,32 

64 

GPMC_D4 

64 63 

63 

GPMC_D7 

6,32 GPMC_D4 

66 

GPMC_D3 

66 65 

65 

GPMC_D7 6,32 

GPMC_D9 

6,32 GPMC_D3 

68 

68 67 

67 

GPMC_D9 6,32 

70 

GPMC_D1 

70 69 

69 

GPMC_D12 

6,32 GPMC_D1 

72 

GPMC_A27 

72 71 

71 

GPMC_D12 6,32 

GPMC_D11 

GPMC_A27 

74 

74 73 

73 

GPMC_D11 6,32 

76 

GPMC_ADVN_ALE 

76 75 

75 

GPMC_D10 

6,32 GPMC_ADVN_ALE 

78 

GPMC_D10 6,32 

GPMC_D6 

78 77 

77 

GPMC_CLK 

6,32 GPMC_D6 

80 

80 79 

79 

GPMC_CLK 6 

82 

GPMC_D8 

82 81 

81 

GPMC_D15 

6,32 GPMC_D8 

84 

GPMC_D15 6,32 

GPMC_D13 

84 83 

83 

6,32 GPMC_D13 

86 

86 85 

85 

POWER_GOOD2 

88 

88 87 

87 

90 

90 89 

89 

92 

92 91 

91 

94 

94 93 

93 

96 

96 95 

95 

98 

98 97 

97 

100 

B GPMC_D14 

100 99 

99 

SPI_CS0 

6,32 GPMC_D14 

102 

SPI_CS0 3,31 

B 

102 101 

101 

104 

SPI_SCLK 

104 103 

103 

SPI_SCLK 3,31 

106 

106 105 

105 

SPI_CS3 

3,31 SPI_MOSI 

108 

108 107 

107 

SPI_CS3 3 

SPI_CS1 

3,31 SPI_MISO 

110 

110 109 

109 

SPI_CS1 3 

112 

UART0_RXD 

112 111 

111 

UART1_RXD 

UART0_RXD 

114 


UART0_RTSN 

114 113 

113 

UART1_TXD 

UART0_RTSN 

116 

116 115 

115 

UART1_TXD 3 

118 

UART0_TXD 

118 117 

117 

UART2_RXD 

UART0_TXD 

120 

120 119 

119 


122 

G2 G1 

121 

124 

G4 G3 

123 

126 

G6 G5 

125 

128 

G8 G7 

127 

QSH-060-01-x-D-A 

EVM_5V0 


A 

EVM_5V0 11,23,25,39,43,44,46,49,50,51 

EVM_3V3 

Title: 


EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,38,39,43,44,45,46,48,49,50,51 

Page Contents: GPMC EXPANSION CONNECTOR 

EVM_12V 

Revision: 

EVM_12V 23,24,39,43,46,47,51 

Size: B 

DWG NO 513832-0001 

A 

Date: 


6 

3 

3 

3 

6 

6 

6 

6 

6 

6 

6 

6 

6 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


D D 

J20 

UART0_CTSN 

UART1_RTSN 

UART0_CTSN 

2 

2 1 

1 

UART1_RTSN 3 

4 

UART0_DTRN 

4 3 

3 

UART2_TXD 

UART0_DTRN 

6 

UART0_DCDN 

6 5 

5 

UART2_TXD 3,28 

SC0_RST 

UART0_DCDN 

8 

8 7 

7 

SC0_RST 3 

10 

UART0_DSRN 

10 9 

9 

SC1_RST 

UART0_DSRN 

12 

UART0_RIN 

12 11 

11 

SC1_RST 3 

SC1_DET 

UART0_RIN 

14 

14 13 

13 

SC1_DET 3 

16 

SPI_SCS2 

16 15 

15 

TIM6_OUT 

SPI_CS2 

18 

TIM6_OUT 3 

UART1_CTSN 

18 17 

17 

SC1_VPPEN 

UART1_CTSN 

20 

20 19 

19 

SC1_VPPEN 3 

22 

SC0_VPPEN 

SC0_VPPEN 

22 21 

21 

24 

TIM7_OUT 

TIM7_OUT 3 

SC0_VCCEN 

SC0_VCCEN 

24 23 

23 

26 

SC1_VCCEN 

26 25 

25 

SC1_VCCEN 3 

28 

SC1_CLK 

SC1_CLK 

28 27 

27 

30 

CLKOUT 

CLKOUT 3 

SC0_C4 

SC0_C4 

30 29 

29 

32 

GP0_IO5 

32 31 

31 

GP0_IO5 14 

34 

UART2_RTSN 

34 33 

33 

TIM4_OUT 

UART2_RTSN 

36 

TIM4_OUT 3 

UART2_CTSN 

36 35 

35 

UART2_CTSN 

38 

38 37 

37 

C 40 

C 

SC0_DET 

SC0_DET 

40 39 

39 

42 

42 41 

41 

13,14,33,36 RSTOUTn 

44 

44 43 

43 

46 

SC0_CLK 

SC0_CLK 

46 45 

45 

48 

SC1_C4 

SC1_C4 

48 47 

47 

50 

GP0_IO7 

50 49 

49 

GP0_IO7 14 

52 

SC0_DATA 

SC0_DATA 

52 51 

51 

54 

GP0_IO4 

GP0_IO4 14 

SC1_DATA 

SC1_DATA 

54 53 

53 

56 

EXP_WARM_RESET 

56 55 

55 

EXP_WARM_RESET 14 

58 

14 GP0_IO6 

GP0_IO6 

58 57 

57 

60 

TIM5_OUT 

60 59 

59 

TIM5_OUT 3 

62 

G2 G1 

61 

64 

G4 G3 

63 

QSH-030-01-x-D-A 

B B 


A 

Title: 



SERIAL I/O EXPANSION CONNECTOR 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


3 

3 

3 

3 

3 

3 

3 

3 

3 

3 

3 

3 

3 

3 

3 

3 

3 

3 

A-43

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


J19 

D 3,27 IIC1_SDA 

IIC1_SDA 

2 

PM_I2C_SCL 

2 1 

1 

PM_I2C_SCL 39,41,44,45 

D 

4 

EVM_5V0 

IIC1_SCL 

4 3 

3 

3,27 IIC1_SCL 

6 

PM_I2C_SDA 

IIC0_SDA 

6 5 

5 

PM_I2C_SDA 39,41,44,45 

3,26,27,36,45 IIC0_SDA 

8 

EXP_MCA2_AXR0 

8 7 

7 


10 

IIC0_SCL 

10 9 

9 

EVM_5V0 11,23,25,39,41,44,46,49,50,51 

3,26,27,36,45 IIC0_SCL 

12 

EXP_MCA2_AMUTE 

12 11 

11 

EXP_MCA2_AMUTE 2 

14 

EXP_MCA2_AXR1 

14 13 

13 


16 

MCA0_AMUTE 

MCA0_AMUTE 

16 15 

15 

18 

EXP_MCA2_ACLKHX 

EXP_MCA2_ACLKHX 2 

MCA0_AXR3 

MCA0_AXR3 

18 17 

17 

20 

EXP_MCA2_ACLKX 

20 19 

19 

EXP_MCA2_ACLKX 2 

22 

MCA0_AXR2 

MCA0_AXR2 

22 21 

21 

24 

EXP_MCA2_AFSR 

EXP_MCA2_AFSR 2 

MCA1_AMUTE 

MCA1_AMUTE 

24 23 

23 

26 

EXP_MCA2_AFSX 

26 25 

25 

EXP_MCA2_AFSX 2 

28 

MCA0_AHCLKX 

MCA0_ACLKHX 

28 27 

27 

30 

EXP_MCA2_AHCLKR 

EXP_MCA2_AHCLKR 2 

MCA0_AFSR 

MCA0_AFSR 

30 29 

29 

32 

EXP_MCA2_ACLKR 

32 31 

31 

EXP_MCA2_ACLKR 2 

34 

EVM_12V 

MCA0_ACLKX 

MCA0_ACLKX 

34 33 

33 

36 

MCA1_AXR1 

MCA1_AXR1 2 

MCA0_AFSX 

MCA0_AFSX 

36 35 

35 

38 

MCA1_AXR0 

38 37 

37 

MCA1_AXR0 2 

EVM_12V 23,24,39,41,46,47,51 

40 

MCA1_AFSX 

40 39 

39 

MTSO_DATA1 

EVM_12V 

MCA1_AFSX 

42 

MTSO_DATA1 2 

MCA0_AXR1 

42 41 

41 

MTSI_DATA5 

EVM_3V3 

MCA0_AXR1 

44 

44 43 

43 

MTSI_DATA5 2 

46 

46 45 

45 

48 

EVM_5V0 

48 47 

47 

C 50 

50 49 

49 

C 

52 

52 51 

51 

54 

54 53 

53 

56 

56 55 

55 

58 

MTSI_DATA7 

MTSI_DATA7 

58 57 

57 

60 

MCA1_ACLKHX 

60 59 

59 

MCA1_AHCLKX 2 

MCA0_AXR5 

MCA0_AXR5 

62 

MDIO_MDIO 

62 61 

61 

MDIO_MDIO 4,33 

64 

MCA0_AXR4 

64 63 

63 

MCA0_AXR4 

66 

MDIO_MDCLK 

MCA0_AXR0 

66 65 

65 

MDIO_MDCLK 4,33 

MCA0_AXR0 

68 

MCA1_ACLKX 

68 67 

67 

MCA1_ACLKX 2 

70 

MCA1_ACLKR 

70 69 

69 

MCA1_ACLKR 

72 

MTSI_DCLK 

MCA1_AHCLKR 

72 71 

71 

MTSI_DCLK 2 

MCA1_AHCLKR 

74 

MTSI_DATA0 

74 73 

73 

MTSI_DATA0 2 

76 

MCA1_AFSR 

MCA1_AFSR 

76 75 

75 

78 

MTSI_DATA2 

MTSI_DATA2 2 

MTSO_DATA0 

78 77 

77 

MTSO_DATA0 

80 

MTSI_DATA1 

80 79 

79 

MTSI_DATA1 2 

82 

MTSO_DATA6 

82 81 

81 

MTSO_DATA6 

84 

MTSI_DATA4 

MTSI_DATA4 2 

MCTL_SDI 

MCTL_SDI 

84 83 

83 

86 

MTSI_DATA3 

86 85 

85 

MTSI_DATA3 2 

88 

MTSO_DATA7 

MTSO_DATA7 

88 87 

87 

90 

MTSI_DATA6 

MTSI_DATA6 2 

MCARD_MDET 

MCARD_MDET 

90 89 

89 

92 

MTSI_BYTSTRT 

92 91 

91 

MTSI_BYTSTRT 2 

B 94 

B 

MCTL_SCTL 

MCTL_SCTL 

94 93 

93 

96 

MTSO_DCLK 

MTSO_DCLK 2 

MCARD_CD2 

MCARD_CD2 

96 95 

95 

98 

MTSO_DATA2 

98 97 

97 

MTSO_DATA2 2 

100 

MCARD_CD1 

MCARD_CD1 

100 99 

99 

102 

MTSO_DATA3 

MTSO_DATA3 2 

MCA0_ACLKR 

MCA0_ACLKR 

102 101 

101 

104 

MTSO_DATA5 

104 103 

103 

MTSO_DATA5 2 

106 

MCA0_AHCLKR 

MCA0_AHCLKR 

106 105 

105 

108 

MTSO_DATA4 

MTSO_DATA4 2 

MCARD_VS1 

MCARD_VS1 

108 107 

107 

110 

MCTL_SCLK 

110 109 

109 

MCTL_SCLK 2 

112 

MCTL_SDO 

MCTL_SDO 

112 111 

111 

114 

MTSO_BYTSTRT 

MTSO_BYTSTRT 2 

MCARD_VCCEN 

MCARD_VCCEN 

114 113 

113 

116 

MCARD_VPPEN 

116 115 

115 

MCARD_VPPEN 2 

118 

MCARD_VS2 

MCARD_VS2 

118 117 

117 

120 

MCARD_RESET 

120 119 

119 

MCARD_RESET 2 

122 

G2 G1 

121 

124 

G4 G3 

123 

126 

G6 G5 

125 

128 

G8 G7 

127 

A QSH-060-01-x-D-A 


A 

EVM_3V3 

Title: 


EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,38,39,41,44,45,46,48,49,50,51 


MCASP/XXX EXPANSION 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


EVM_3V3 

EVM_3V3 

ADDRESS 1000000 


U18 

10 

VIN+ 

SCL 

5 

SDA 4 

9 

VIN- NC.3 

3 

A0 

2 

A1 

1 

8 

VBUS GND 7 

U14 

C471 

U22 

C514 

0.1uF 

0.1uF 

VS 6 

VS 6 

50 I_MON_0V9_HIGH 

10 

VIN+ 


10 

PM_I2C_SCL 

VIN+ 

PM_I2C_SCL 

SCL 

5 

PM_I2C_SDA 

SCL 

5 

PM_I2C_SDA 

EVM_0V9 

SDA 4 

EVM_3V3 

SDA 4 

D D 

9 

VIN- NC.3 

3 

9 

VIN- NC.3 

3 

EVM_3V3 

A0 

2 

A0 

2 

A1 

1 

A1 

1 

8 

VBUS 

GND 7 

INA220IDCN 


EVM_3V3 


8 

VBUS 

GND 7 

INA220IDCN 

EVM_3V3 

8 

VBUS 

GND 7 

INA220IDCN 


EVM_3V3 


8 

VBUS 

GND 7 

INA220IDCN 

EVM_3V3 

EVM_0V9 

EVM_0V9 5,50 

EVM_1V8_A 

EVM_1V8_A 9,50 

8 

VBUS 

GND 7 

INA220IDCN 

EVM_1V0_CON 

46 I_MON_1V0_CONN_HIGH 

EVM_1V0_CON 9,11,15,16,17,20,46,50 

EVM_1V0_CON 

EVM_1V0_AVS 

EVM_1V0_AVS 18,20,49 


EVM_3V3 

C495 

0.1uF 

PM_I2C_SCL 

PM_I2C_SCL 39,41,43,45 

PM_I2C_SDA 

PM_I2C_SDA 39,41,43,45 

EVM_1V8_D 

EVM_1V5 

INA220IDCN 


A 

8 

VBUS 

GND 7 

INA220IDCN 

U59 

C795 

U23 

C516 

0.1uF 

VS 6 

0.1uF 

VS 6 

48 I_MON_1V5_ALT_HIGH 

10 

VIN+ 

49 I_MON_1V0_AVS_HIGH 

10 

PM_I2C_SCL 

VIN+ 

PM_I2C_SCL 

SCL 

5 

PM_I2C_SDA 

SCL 

5 

PM_I2C_SDA 

EVM_ALT_1V5 

SDA 4 

EVM_1V0_AVS 

SDA 4 

B B 

9 

VIN- NC.3 

3 

9 

VIN- NC.3 

3 

EVM_3V3 

A0 

2 

A0 

2 

A1 

1 

A1 

1 

U11 

C467 

U17 

C480 

0.1uF 

I_MON_1V8DIGITAL_HIGH 

44 

10 

VS 6 VS 6 

0.1uF 

VIN+ 


10 

PM_I2C_SCL 

VIN+ 

PM_I2C_SCL 

SCL 

5 

PM_I2C_SDA 

PM_I2C_SDA 

EVM_1V8_D 

SDA 4 

SCL 

5 

EVM_5V0 

SDA 4 

9 

EVM_3V3 

VIN- NC.3 

3 

9 

VIN- NC.3 

3 

EVM_3V3 

A0 

2 

A0 

2 

A1 

1 

A1 

1 

8 

VBUS GND 7 

8 

VBUS GND 7 

EVM_3V3 

EVM_3V3 

INA220IDCN 

INA220IDCN 

C C 



U7 

C466 

U42 

C704 

0.1uF 

VS 6 0.1uF 

VS 6 

I_MON_1V8ANALOG_HIGH 

44 

10 

VIN+ 


10 

PM_I2C_SCL 

VIN+ 

PM_I2C_SCL 

SCL 

5 

PM_I2C_SDA 

SCL 

5 

PM_I2C_SDA 

EVM_1V8_A 

SDA 4 

EVM_1V5 

SDA 4 

9 

VIN- NC.3 

3 

9 

VIN- NC.3 

3 

EVM_3V3 

A0 

2 

A0 

2 

A1 

1 

A1 

1 

VS 6 

EVM_1V8_D 5,15,16,47,50 

EVM_1V5 7,8,17,20,21,22,47,48,50,51 

EVM_5V0 

Title: 


EVM_ALT_1V5 

EVM_5V0 11,23,25,39,41,43,46,49,50,51 

Page Contents: POWER MONITOR 

EVM_3V3 

EVM_ALT_1V5 16,48 

Revision: 

Size: B 

DWG NO 513832-0001 

C 

EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,38,39,41,43,45,46,48,49,50,51 


A-45

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


EVM_3V3 

EVM_3V3 

EVM_3V3 

R426 

47K 

EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,38,39,41,43,44,46,48,49,50,51 

HEADER 7X2 

430_TDO/TDI 

1 

TDO/TDI VCC_TOOL 

2 

3 

D TDI/VPP VCC_MSP 4 

D 

5 

TMS 

XOUT 

6 

7 

TCK TEST/VPP 8 

9 

EVM_3V3 

GND 

ACLK 10 

11 

R186 

RST/NMI ACLKEN 12 

13 

C607 330 

NC1 TCLKEN 14 R432 

10K 

EVM_3V3 

0.001uF 

J14 

14 MSP430_INT 

C653 C657 

1uF 0.1uF 

MSP430_TCK 

U38 

EVM_3V3 

1 

TEST/SBWTCK 

P1.7/TA0.2/TDO/TDI 

28 

2 

DVCC.1 

P1.6/TA0.1/TDI/TCLK 27 

R431 100K 

3 

P2.5/ROSC/CA5 

P1.5/TA0.0/TMS 26 

C C 


C162 

4 

DVSS.1 

P1.4/SMCLK/TCK 25 

5 

XOUT/P2.7/CA7 

P1.3/TA0.2 

24 

EVM_3V3 

R183 R184 

10K 

10pF 

6 

XIN/P2.6/CA6 

P1.2/TA0.1 

23 

10K 

Y3 

MSP430_TDO/TDI 

U39 

7 

RST/NMI/SBWTDIO 

P1.1/TA0.0/TA1.0 

22 

3 

C666 

+ C171 15 

VCC FORCEOFF 

16 

2 

8 

P1.0/TACLK/ADC10CLK/CAOUT 

21 

1uF 

10uF 

32.768KHz 

P2.0/ACLK/A0/CA2 

FORCEON 12 

DB9M 

C161 

9 

P2.1/TAINCLK/SMCLK/A1/CA3 P2.4/TA0.2/A4/VREF+/VEREF+/CA1 

20 

10 

P2.2/TA0.0/A2/CA4/CAOUT P2.3/TA0.1/A3/VREF-/VEFEF-/CA0 

19 

5 

11 

T_IN T_OUT 

13 

9 

10pF 

39,41,43,44 PM_I2C_SDA 

11 

P3.0/UCB0STE/UCA0CLK/A5 

P3.7/TA1.1/A7 

18 

4 

8 

3,26,27,36,43 IIC0_SDA 

12 

P3.1/UCB0SIMO/UCB0SDA 

P3.6/TA1.0/A6 

17 

3 

7 

3,26,27,36,43 IIC0_SCL 

13 

MSP430_RXD 

P3.2/UCB0SOMI/UCB0SCL 

P3.5/UCA0RXD/UCA0SOMI 

16 

9 

R_OUT R_IN 8 

2 

6 

39,41,43,44 PM_I2C_SCL 

14 

MSP430_TXD 

P3.3/UCB0CLK/UCA0STE 

P3.4/UCA0TXD/UCA0SIMO 15 

1 

B EVM_3V3 EVM_3V3 

1 

B 

EN INVALID 10 P7 

MSP430F2132IPWR 

R434 R436 

R435 

2K 

2K 

10K 

2 

C1+ 

C2+ 

5 

C213 

C212 

1uF 

1uF 

4 

C1- 

C2- 

6 

V+ 

3 

14 

GND 

V- 

7 

C692 

C693 

MAX3221CPWRG4 

1uF 

1uF 

11 

1 4 

10 


A 

Title: 



POWER MONITOR CPU 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 



5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


EVM_12V 

EVM_3V3 

EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,38,39,41,43,44,45,48,49,50,51 

C47 

100uF 

EVM_1V0_AVS 

C486 

C491 

C41 C39 

1uF 

1uF 

EVM_5V0 

EVM_1V0_AVS 18,20,44,49 

100uF 0.1uF 

EVM_12V 

D EVM_5V0 

D 

EVM_12V 23,24,39,41,43,47,51 

C488 

1uF 

EVM_5V0 

EVM_5V0 11,23,25,39,41,43,44,49,50,51 

Rbottom = VFBxRtop/(VOUT-VFB) 

Rbottom = 0.8xRtop/(2.5) 

R79 6.98K 

C43 100pF 

C40 

100uF 

C46 1000pF R76 20K 

U16 

1 

BG 

AGND.13 

48 

R80 22.1K 

2 

VINBQ 

AGND.12 

47 

EVM_1V0_CON 

C37 

0.1uF 

EVM_1V0_CON 9,11,15,16,17,20,44,50 

EVM_12V 

C48 1000pF 

3 

V6V 

AGND.11 

46 

EVM_12V 23,24,39,41,43,47,51 

4 

VIN 

AGND.10 

45 


EVM_3V3 

CURRENT MONITOR 

5 

FB2 

AGND.9 

44 

I_MON_1V0_CONN_HIGH 44 

6 

CMP2 

AGND.8 

43 


7 

EN_BCK2 

AGND.7 

42 

C EVM_3V3 

C 

C226 

8 

PGND2.1 

AGND.6 

41 

1000pF 

9 

PGND2.2 

BST3 

40 C481 0.1uF 

EVM_1V0_CON 9,11,15,16,17,20,44,50 

C49 

22uF 

L8 

10 

PH2.1 

VINB3.2 

39 

C50 

22uF 

R81 0.025 1 2 

11 

EVM_1V0_CON 

PH2.2 

VINB3.1 

38 

L7 

EVM_5V0 

C38 

47uF 

EVM_12V 

2.2uH-HCP0805-2R2-R 

1206 

12 

13 

14 

15 

16 

VINB2.1 

VINB2.2 

BST2 

DGND 

LDRV 


17 

HDRV 

CMP3 

32 

R78 

Q1A 

18 

PH1 

FB3 

31 

88.7K 

FDS6982 

2 R70 0 


C474 0.22uF 19 

EVM_5V0 

BST1 

AGND.5 

30 

R71 

B 20K 

B 

20 

EN_BCK1 

AGND.4 

29 

C31 

21 

CMP1 

AGND.3 

28 

100pF 

Rbottom = VFBxRtop/(VOUT-VFB) 

EVM_5V0 

22 

FB1 

AGND.2 

27 

C30 

1000pF Rbottom = 0.8xRtop/(.2) 

L6 

23 

SS 

AGND.1 

26 

R69 0.025 1 2 

24 

TRIP 

V3P3 

25 

4.7uH-74477004 

C473 

3300pF 

C35 C34 

1206 

TPS65232 

C472 

22uF 22uF 

1uF 

Q1B 

FDS6982 

4 R72 0 

PH3.2 

PH3.1 

PGND3.2 

PGND3.1 

EN_BCK3 

37 

36 

35 

34 

33 

C42 

22uF 

C44 

22uF 

49 

PWR PAD 

A C25 


A 

R66 Rbottom = VFBxRtop/(VOUT-VFB) 

1000pF 

C227 

4.22K 

1000pF 

Title: 


Rbottom = 0.8xRtop/(4.2) 

C99 

1000pF 

Page Contents: POWER SUPPLY III 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


+ 

+ 

+ 

D 

S 

G 

+ 

+ 

3 

6 

5 

R67 

22.1K 

C33 

0.1uF 

R62 

20K 

C478 0.1uF 

1 2 

2.2uH-HCP0805-2R2-R 

1206 

R75 0.025 

R77 

22.1K C45 

1000pF 

+ 

+ 

D 

S 

G 

1 

8 

7 

C29 

1000pF 

C27 R65 C28 

100pF 215K 1000pF 

+ 

+ 

+ 

A-47

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


D D 

I_MON_1V5_HIGH 44 


NETRA MEMORY POWER SUPPLY 1.5/1.8V 

PLL AND VTT USE ALT_1V5 POWER SUPPLY SO DDR2 AND DDR3 CAN BE SUPPORTED 

EVM_1V5 7,8,17,20,21,22,44,48,50,51 

TP19 

L14 

EVM_1V5 

1 

1 2 

R202 0.025 

1.8uH-7447715001 

TEST POINT 

1206 

R196 

C U33 

C 

R170 100K 1 

C220 C225 

RT/CLK PWRGD 14 

100uF 100uF 

2 

C148 0.1uF 

EVM_12V 

GND.1 

BOOT 

13 

3 

GND.2 

PH.2 

12 

R194 

4 

10.0K 

JP1 

PVIN.1 

PH.1 

11 

C119 

10uF 

C118 

10uF 

C126 

4.7uF 

B 0.018uF 

TP13 

B 

EVM_1V8_D 

5 

6 

PVIN.2 

VIN 

R174 

3.83K 

C136 

C132 

56pF 

C143 

.018uF 

TP20 

TEST POINT 

1 

TEST POINT 

Rtop = (Vout-Vref/Vref) * RBottom 

FOR 1.5 VOLTS 

10K = (1.5-0.8/0.8) * RBottom 

10K = 0.875 * RBottom 

11.5K = RBottom 

2 

HEADER 3 

1 

3 

R489 

NO-POP 

FOR 1.8 VOLTS 

10K = 1.25 * RBottom 

8.06K = RBottom 

C713 

0.1uF 

EVM_1V5 


A 

EVM_1V5 7,8,17,20,21,22,44,48,50,51 

Title: 



POWER SUPPLY 1V5/1V8 MEMORY 

EVM_12V 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

EVM_12V 23,24,39,41,43,46,51 


0 

15 

PWRPAD 

C127 

10uF 

1 

7 

VSENSE 

TPS54620 

EN 10 

SS/TR 9 

COMP 8 

R187 

8.06K 

R205 1K 

EVM_1V8_D 

R206 

EVM_1V8_D 5,15,16,44,50 

10K 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


D D 

EVM_3V3 

C797 

2.2uF 

1 

2 

4 

7 

5 

U67 

IN1 

IN2 

BIAS 

SS 

EN 

TPS74701 

VOUT2 

VOUT1 

PG 3 

FB 8 

GND 6 

10 

9 

R486 

4.99K 1% 

VOUT = 0.8 * ( 1+(RTOP/RBOTTOM) ) 

EVM_ALT_1V5 

EVM_ALT_1V5 16,44 


I_MON_1V5_ALT_HIGH 44 

PP1 

C800 

0.001uF 

R485 

4.32K 1% C798 

5.6pF 

C799 

10uF 

R484 0.02 

1.5 = 0.8 * ( 1+(RTOP/RBOTTOM )) 

11 

1.875 = ( 1+(RTOP/RBOTTOM )) 

C C 

0.875 RBOTTOM = RTOP 

EVM_1V5 

R207 1K 

R208 

10K C714 

0.1uF 

B B 

EVM_1V5 

EVM_1V5 7,8,17,20,21,22,44,47,50,51 

EVM_ALT_1V5 

EVM_ALT_1V5 16,44 

EVM_3V3 

A A 

EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,38,39,41,43,44,45,46,49,50,51 


Title: 



POWER SUPPLY 1V5 ALT 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 


A-49

5 

5 

+ 

4 

4 

3 

3 

G 

D 

S 

2 

2 

1 

1 


SUPPORT OUTPUT VOLTAGES OF 0.75 TO 1.2 VOLTS 

EVM_3V3 EVM_1V0_AVS 

1 

EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,38,39,41,43,44,45,46,48,50,51 EVM_1V0_AVS 18,20,44 

EVM_5V0 

EVM_5V0 11,23,25,39,41,43,44,46,50,51 

EVM_5V0 

D D 

C103 

100uF 

I_MON_1V0_AVS_HIGH 44 

G 


D 

R92 

S 

8 

7 

Q4A 

IRF7910pbf 

2 

EVM_1V0_AVS 18,20,44 

U29 

EVM_1V0_AVS 

L12 

+ 

C102 

100uF 

1 

HDRV 8 

ENn 

1 

2 

FB SW 7 

1 2 R84 0.025 

1.2uH-74470001 

C C 

3 

EVM_3V3 

COMP BOOT 

6 

C100 

Q7 

4 

VDD LDRV 5 

0.22uF 

1206 

R145 1K 

G 

BSS138 

TPS40041 

C58 C57 C54 

C94 

Q4B 

100uF 100uF NO-POP 

1uF 

4 

IRF7910pbf 

C711 

0.01uF 

D 

6 

5 

PAD 

PAD 

S 

3 

R85 0 

R86 590 C104 560pF C59 820pF 

R121 17.8K 

R87 10.0K 

C101 33pF 

1 

1 

A-50 C6A816x/AM389x EVM Technical Reference 

TP14 

TEST POINT 

TP12 

TEST POINT 

B B 

1 

TP18 

TEST POINT 

R133 

38.3K 

R134 

NO-POP 

0.75 V R = 38.3K 

R89 

110K 

EVM_3V3 

R93 

100K 

R13 

NO-POP 

1.00 V R = 14.7K 

R105 

1.2 V R = 10.0K 

R126 EVM_3V3 

75K 

EVM_3V3 

EVM_3V3 

24.3K 

DESIGNED FOR 1 VOLT R27 

R15 

R63 

NO-POP 

NO-POP 

10K 

3 

3 

3 

3 

D 

D 

D 

D 

Q2 

NTA4153NT1G 

G 

1 

R90 10K 

Q3 

NTA4153NT1G 

G 

1 

R94 10K 

Q5 

NTA4153NT1G 

G 

1 

R119 10K 

Q6 

NTA4153NT1G 

G 

1 

R130 10K 

S 

S 

S 

S 

R127 

R106 

R91 

R88 

NO-POP 

10K 

10K 

10K 


A 

2 

2 

2 

2 


POWER SUPPLY 1V0_AVS 

Title: 


GP0_IO0 

14 

GP0_IO1 

14 

Revision: 

DWG NO 513832-0001 

A 

52 

Sheet o f Wednesday, November 03, 2010 49 GP0_IO2 

14 

Size: B 

Date: 

GP0_IO3 

14

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


EVM_5V0 

EVM_5V0 

VDCDC = VFB_DCDC x (( Rtop + Rbottom)/Rbottom ) 

+ CT1 

33uF 

U10 

R48 

10K 

VDCDC = 0.6 x (( Rtop + Rbottom)/Rbottom ) 

8 

TP9 

VINDCDC 

PGn 

5 

1 

NO-POP 

1V8_DIGITAL 

1 TP8 

NO-POP 

D D 

10 

EN_DCDC 

SW 7 L4 2.2uH 

9 

15 

MODE 

VINLDO1 

FB_DCDC 11 

VLDO1 

14 

1V8_ANALOG 

1 

TP10 

NO-POP 

C17 

22pF 

R36 

200K 1% 

+ C19 

33uF 

0.1uF 

EVM_3V3 

+ CT2 

33uF 

3 

18 

EN_LDO1 

VINLDO2 

FB_LDO1 

VLDO2 

13 

17 

0V9_A 

1 

TP11 

NO-POP 

R51 

261K 1% + C20 C21 

33uF 0.1uF 

R37 

100K 1% 

R53 

4 

EN_LDO2 

FB_LDO2 

16 

80.6K 1% 

VLDO1 = VFB_LDO x (( Rtop + Rbottom)/Rbottom ) 

VLDO1 = 0.5 x (( Rtop + Rbottom)/Rbottom ) 

C C 

R54 10K 1 

MRn 

C24 

33uF 

C23 

0.1uF 

R40 

100K 1% 

R52 

100K 1% 

2 

EVM_1V0_CON 

C22 

TRST 

0.1uF 

VLDO2 = VFB_LDO x (( Rtop + Rbottom)/Rbottom ) 

R55 10K 

RSTn 

20 

19 

RSTSNS 

VLDO2 = 0.5 x (( Rtop + Rbottom)/Rbottom ) 

R204 

100K 

12 

C712 

AGND 

.1uF 

TPS65001 

EVM_5V0 

PGND 6 

PWR_PAD 

0V9_A 

EVM_0V9 

21 

R56 0.02 

R50 

100K 

B I_MON_0V9_HIGH 44 

B 

EVM_0V9 5,44 


1V8_ANALOG 

EVM_1V8_A 

R47 0.02 

EVM_1V5 

R35 4.99K 

5 

U5 

SENSE1 

C18 

EVM_1V8_A 9,44 

EVM_3V3 

EVM_3V3 

C462 

1V8_DIGITAL 

EVM_1V8_D 

0.1uF R30 

10K 

R32 0.02 

VDD 6 


I_MON_1V8ANALOG_HIGH 44 

EVM_5V0 

R34 

10K 1% 

C16 

NO-POP 

4 

3 

CT 

MR 

RESET 


1 

GND 2 

1 

TP7 

EVM_1V8_D 5,15,16,44,47 


I_MON_1V8DIGITAL_HIGH 44 


EVM_1V8_A 

EVM_5V0 11,23,25,39,41,43,44,46,49,51 


A 

EVM_1V0_CON 

EVM_1V8_A 9,44 

EVM_1V8_D 

Title: 


EVM_1V0_CON 9,11,15,16,17,20,44,46 

EVM_1V8_D 5,15,16,44,47 

Page Contents: POWER SUPPLY 0V9/1V8_A/1V8B 


Revision: 

Size: B 

DWG NO 513832-0001 

A 

EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,38,39,41,43,44,45,46,48,49,51 EVM_1V5 7,8,17,20,21,22,44,47,48,51 


+ 

A-51

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


TP2 

TP-30 

EVM_12V 

SW1 

SWITCH 

8 

2 

5 

7 

R5 

2k 

D D 

+ C4 

100uF 

3 

1 

6 

4 

SILKSCREEN: 

12V IN 

J1 

F1 

CENTER 

1 2 

SHUNT 

DS1 

SLEEVE 

F_4.0A 

LED GRN 

2.5 MM JACK 

RASM712 

D1 

SMCJ14A-13-F 

EVM_3V3 

EVM_3V3 

EVM_1V5 

C633 

PCB EDGE 

R167 

U32 

0.1uF 

C 10K 

C 

R179 4.99K 

5 

SENSE1 VDD 6 

R178 

4 

CT RESET 

1 

CPU_PORz 14 

10K 1% 

C635 

3 

MR GND 2 

0.1uF 

DRIVE CONN 


EVM_12V EVM_5V0 

EVM_3V3 

P11 

EVM_12V 

MH1 

6 


9 

MP2 

1 

+12 

1 

2 

TACH FAN CONNECTOR 

GND2 

2 

R166 

3 

GND1 

3 

10K 

+5 

4 

SW6 

8 

MP1 

A 

B 

HEADER 3 

MH2 

7 

A1 B1 

J8 

PUSHBUTTON SW 

EVM_3V3 

B B 

EVM_3V3 2,3,5,6,11,13,14,15,18,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,38,39,41,43,44,45,46,48,49,50 

BOARD MOUNTING HOLES - ONE IN EACH CORNER 

BOARD MOUNTING HOLES - FOR EXPANSION CONNECTORS 

EVM_5V0 

Mounting holes 0.250 pad 0.125 drill 

EVM_5V0 11,23,25,39,41,43,44,46,49,50 

MH6 

MH3 

EVM_12V 

MH7 

MH8 

MH9 

1 

1 

1 

1 

1 

EVM_12V 23,24,39,41,43,46,47 

MH4 

MH5 

EVM_1V5 

1 

1 

MH1 

MH2 

EVM_1V5 7,8,17,20,21,22,44,47,48,50 

1 

1 


A 

Title: 


1 TP1 

1 TP6 

1 TP5 

1 TP26 

1 TP17 

1 TP25 

TEST POINT 

TEST POINT 

TEST POINT 

TEST POINT 

TEST POINT 

TEST POINT 

1 TP16 

1 TP23 

Page Contents: POWER INPUT 

TEST POINT 

TEST POINT 

Revision: 

Size: B 

DWG NO 513832-0001 

A 

Date: 



5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


3.5 

D D 

EVM_3V3 

3.0 

C C 

2.0 

EVM_1V8_D 

EVM_1V8_A 

EVM_1V5 

VOLTS 

EVM_1V5 ( ACTUALLY 1V8 FOR DDR2 ) 

ALT_EVM_1V5 

EVM_1V0_CON 

1.0 

EVM_1V0_AVS 

EVM_0V9 

B B 

10 20 30 40 50 60 70 80 90 


A 

MILLISECONDS 

Title: 


Page Contents: POWER SEQUENCE 

Revision: 

Size: B 

DWG NO 513832-0001 

B 

Date: 


A-53

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


D D 

REVISION A - MAY 31, 2010 

INITIAL RELEASE 

REVISION B - AUG 1, 2010 

ADDED ETHERNET MDIO ADDRESS FIX 

ADDED EXTERNAL REFERENCE FOR VDAC 

UPDATED POWER SEQUENCING 

C C 

B B 


A 

Title: 



REVISIONS 

Revision: 

Size: B 

DWG NO 513832-0001 

B 

Date: 



Appendix B 

Mechanical Information 

This appendix contains the mechanical information about the 

C6A816x/AM389x EVM produced by Spectrum Digital. 

B-1


THIS DRAWING IS NOT TO SCALE 

B-2 C6A816x/AM389x EVM Technical Reference

Printed in U.S.A., January 2011 

513830-0001 Rev A

C6A816x/AM389x Evaluation Module - Spectrum Digital Support

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