2003 Course - K. K. Wagh Education Society
2003 Course - K. K. Wagh Education Society 2003 Course - K. K. Wagh Education Society
2. Christopher M. King, Curtis patton and RSA press “Security architecture, design deployment and operations”. 3. Stephen northcatt, leny zeltser, et al “INSIDE NETWORK Perimeter Security” Pearson Education Asia. 4. Robert Bragge, Mark Rhodes, Heith straggberg “Network Security - the complete reference”, Tata McGraw Hill Publication 10449 Advanced Computer Architecture and Computing Teaching Scheme Theory : 4 Hrs/Week Examination Scheme Theory: 100 Marks Duration: 3 Hours UNIT I: Overview of Parallel Processing and Pipelining Processing Necessity of high performance, Constraints of conventional architecture, Parallelism in uniprocessor system, Evolution of parallel processors, future trends, Architectural Classification, Applications of parallel processing, Instruction level Parallelism and Thread Level Parallelism, Explicitly Parallel Instruction Computing (EPIC) Architecture, Case study of Intel Itanium Processor Principles of scalable performance : Performance Metrics and Measures, Speedup Performance Laws. UNIT II: Pipeline Architecture 6 Hrs. Principles and implementation of Pipelining, Classification of pipelining processors, General pipelining reservation table, Design aspect of Arithmetic and Instruction pipelining, Pipelining hazards and resolving techniques, Data buffering techniques, Job sequencing and Collision, Advanced pipelining techniques, loop unrolling techniques, out of order execution, software scheduling, trace scheduling, Predicated execution, Speculative loading, Register Stack Engine, Software pipelining, VLIW (Very Long Instruction Word) processor, Case study: Superscalar Architecture- Pentium, Ultra SPARC 8 Hrs
UNIT III: Vector and Array Processor Basic vector architecture, Issues in Vector Processing, Vector performance modeling, vectorizers and optimizers, Case study: Cray Arch. SIMD Computer Organization Masking and Data network mechanism, Inter PE Communication, Interconnection networks of SIMD, Static Vs Dynamic network, cube hyper cube and Mesh Interconnection network. Parallel Algorithms For Array Processors: Matrix Multiplication. Sorting, FFT 8 Hrs. UNIT IV: Multiprocessor Architecture Loosely and Tightly coupled multiprocessors, Processor characteristics of multiprocessors, Inter Processor communication network, Time shared bus, Crossbar switch, Multiport Memory Model, Memory contention and arbitration techniques, Cache coherency and bus snooping, Massively Parallel Processors (MPP), COW’s and NOW’s Cluster and Network of Work Stations), Chip Multiprocessing (CMP), Case Study of IBM Power4 Processor Inter Processor Communication and Synchronization 8 Hrs. UNIT V: Multithreaded Architecture Multithreaded processors, Latency hiding techniques, Principles of multithreading, Issues and solutions, Parallel Programming Techniques Message passing program development, Synchronous and asynchronous message passing , Message passing parallel programming, Shared Memory Programming, Data
- Page 1 and 2: Structure of B.E (2003 Course):- De
- Page 3 and 4: UNIT II: Divide And Conquer And Gre
- Page 5 and 6: Background, Critical section proble
- Page 7 and 8: Teaching Scheme Lectures: 3 Hours /
- Page 9 and 10: • To learn issues in modeling lar
- Page 11 and 12: Error detection and recovery, Autom
- Page 13 and 14: • To Learn and Understand the kno
- Page 15 and 16: Utilization and functionality, arch
- Page 17 and 18: UNIT IV : Segmentation : Region Ext
- Page 19 and 20: Introduction, Parallel database arc
- Page 21 and 22: • Learn key concepts of Multimedi
- Page 23 and 24: screening, color cycling, morphing
- Page 25 and 26: PART II: Assignments related to Ope
- Page 27 and 28: The project will be undertaken pref
- Page 29: Principles, RSA, ECC, DSA, key mana
- Page 33 and 34: . http://www.ibm.com/servers/eserve
- Page 35 and 36: Fix Distribution: Overview of Fix D
- Page 37 and 38: Text Books: 1. Andrew S. Tanenbaum
- Page 39 and 40: Text Books 1. Rajkamal, “Embedded
- Page 41 and 42: Conceptual view of ISDN and ISDN st
- Page 43 and 44: Understanding quality attributes, a
- Page 45 and 46: 2. Submit a IDL definition for a fe
- Page 47: Computer Laboratory II Assignment N
2. Christopher M. King, Curtis patton and RSA press “Security architecture, design<br />
deployment and operations”.<br />
3. Stephen northcatt, leny zeltser, et al “INSIDE NETWORK Perimeter Security”<br />
Pearson <strong>Education</strong> Asia.<br />
4. Robert Bragge, Mark Rhodes, Heith straggberg “Network Security - the complete<br />
reference”, Tata McGraw Hill Publication<br />
10449 Advanced Computer Architecture and Computing<br />
Teaching Scheme<br />
Theory : 4 Hrs/Week<br />
Examination Scheme<br />
Theory: 100 Marks<br />
Duration: 3 Hours<br />
UNIT I:<br />
Overview of Parallel Processing and Pipelining Processing<br />
Necessity of high performance, Constraints of conventional architecture, Parallelism in<br />
uniprocessor system, Evolution of parallel processors, future trends, Architectural<br />
Classification, Applications of parallel processing, Instruction level Parallelism and<br />
Thread Level Parallelism, Explicitly Parallel Instruction Computing (EPIC) Architecture,<br />
Case study of Intel Itanium Processor<br />
Principles of scalable performance : Performance Metrics and Measures, Speedup<br />
Performance Laws.<br />
UNIT II:<br />
Pipeline Architecture<br />
6 Hrs.<br />
Principles and implementation of Pipelining, Classification of pipelining processors,<br />
General pipelining reservation table, Design aspect of Arithmetic and Instruction<br />
pipelining, Pipelining hazards and resolving techniques, Data buffering techniques, Job<br />
sequencing and Collision, Advanced pipelining techniques, loop unrolling techniques,<br />
out of order execution, software scheduling, trace scheduling, Predicated execution,<br />
Speculative loading, Register Stack Engine, Software pipelining, VLIW (Very Long<br />
Instruction Word) processor, Case study: Superscalar Architecture- Pentium, Ultra<br />
SPARC<br />
8 Hrs
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