Intel PXA250 and PXA210 Applications Processors

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JTAG/Debug Port 9.3 Layout Use the JTAG/Debug the port layout recommendations given in ARM’s application note, Multi- ICE System Design Considerations, Application Note 72. The recommended connector is a 2x10- way, 2.54 mm pitch pin header, shown in Figure 9-1. If board space is critical, use a small form-factor receptacle with a smaller pitch. Then use a cable interface that has a wire “dongle” with a 2.54 mm pitch pin header on one end and the smaller pitch connector on the other. Place the JTAG/Debug connector as close as possible to the applications processor to minimize signal degradation. If you follow these design recommendations, a JTAG bridge board is not required. Essentially, the JTAG bridge board for the example form factor reference design uses a 220 ohm resistor to tie nTRST high so that the JTAG logic can be brought out of reset (otherwise it would not come out of reset since nTRST is open-drain). 9-2 PXA250 and PXA210 Applications Processors Design Guide
SA-1110/Applications Processor Migration A The Intel® PXA250 an PXA210 applications processors represent the next generation follow-on to Intel® StrongARM* SA-1110 product. This appendix highlights the migration path needed to change an SA-1110 design to one that uses the applications processor. The majority of application code running on the SA-1110 will directly run on the applications processor, but there are substantial differences in hardware implementation and low-level coding, especially device configuration, that need to be noted. The applications processor has numerous new hardware and software features that substantially benefit a handheld product design. The applications processor can be considered a superset of the SA-1110, but with so many new features direct socket compatibility is impractical. For a detailed analysis of the differences between these products, refer to the full specifications of each device: • SA-1110 Advanced Developers Manual, Order# 278240 [http://developer.intel.com] • Intel® PXA250 and PXA210 Applications Processors Developer’s Manual, Order# 278522 • ARM* Architecture Reference Manual, Order# ARM DDI 0100D-10 • Intel 80200 Developers’ manual, Order# 273411-002 [http://developer.intel.com] Or later updated versions of any of the above. This appendix is separated into sections that focus on three different issues: 1. SA-1110 hardware migration issues — Hardware Compatibility —Signal Changes — Power Delivery — Package —Clocks —UCB1300 2. SA-1110 software migration issues — Software Compatibility — Address space — Page Table Changes — Configuration registers —DMA 3. Using new features in the applications processor PXA250 and PXA210 Applications Processors Design Guide A-1
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Intel ® PXA250 and PXA210 Applicat
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Contents Contents 1 Introduction...
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Contents A.1 SA-1110 Hardware Migra
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Contents 2-7 SRAM / ROM / Flash / S
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Introduction 1 Table 1-1. Revision
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Introduction • System memory inte
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Introduction Table 1-3. Signal Pin
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Introduction Figure 1-2. PXA250 App
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Introduction Table 1-4. PXA250 Appl
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Introduction Figure 1-3. PXA210 App
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Introduction Table 1-5. PXA210 Appl
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System Memory Interface 2 This sect
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System Memory Interface Table 2-1.
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. System Memory Interface 2.4 SDRAM
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System Memory Interface Figure 2-5.
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System Memory Interface Figure 2-6.
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Page 47 and 48: LCD Display Controller Figure 3-1.
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DCPXA250 Processor Card 32-bit vers
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DCPXA210 Processor Card 4 CONNECTOR
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Intel PXA250 and PXA210 Applications Processors

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