Intel PXA250 and PXA210 Applications Processors

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Power and Clocking Figure 8-5. Example Form Factor Reference Design Power System Design LDO ON/OFF Audio AMP LDO ON/OFF Audio_DC3P3V MMC_VDD LDO ON/OFF 3.3V LDO ON/OFF LCD_DC3P3V LDO ON/OFF 3.2V LDO ON/OFF LCD_DC5V LDO ON/OFF LCD_DC4V CF_VDD LDO ON/OFF 3.3V Boost Converter MAX633 LCD_DC15V LCD_DC14V- Boost Converter LTC1308A DC_5P5V LCD_DC11P7V- LDO 3.2 V LDO 3.3 V DC_3P3V DC_CORE Buck Converter LTC1878 0.8 - 1.3 V Wall Input Current Limited Battery Charger LTC1730 battery LDO 1.3 V DC_PLL 8.7.2 CORE Power The example form factor reference design has a variable 0.8 V – 1.3 V core power supply for the applications processor. This voltage varies depending on the performance required by the application. A Linear Technologies LTC1878 buck converter is chosen for this application. The power is drawn directly from the Li+ battery. This device operates at 550 kHz and can supply up to 1 A at 0.8 V and 800 mA at 1.3 V with up to 95% efficiency. The device is turned on/off by the SA_PWR_EN signal directly from the applications processor. The required output voltage is statically adjusted by selecting the value of the feed-back resistor. Ultimately, output voltage can be changed using software control of the Linear Technologies LTC1663 DAC. This DAC is controllable via the standard I2C bus, and can modify the voltage of the feedback path of the buck converter, which effects a change in the output voltage. 8.7.3 PLL Power DC_PLL supplies power to the three PLLs within the applications processor. This pin requires a 0.85 V to 1.3 V nominal supply at an expected 20 mA load. 8-22 PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking 8.7.4 I/O 3.3 V Power A simple LDO linear regulator supplies the 3.3V rail. The Analog Devices ADP3335 is chosen for its very low drop-out – 200 mV at 500 mA and 110 mV at 200 mA. So typically, the input cut-off voltage for this device is about 3.3 V + 0.11 V = 3.41 V. The power is drawn directly from the Li+ battery. For a 3.6 V battery, this device has a 82% efficiency. There are four zones of operation for the Li+ battery: • 4.1 – 3.8 V zone 10% of the time; • 3.7 – 3.6 V zone at 70% of the time; • 3.5 – 3.4 V at 10% of the time; and • 3.4 – 3.1 V at 10% of the time. The ADP3335 operates in zone 1,2, 3, and cutoffs in zone 4. The overall efficiency is: 0.1(3.3/4.0) + 0.7(3.3/3.6) + 0.1(3.3/3.4) = 0.0825 + 0.642 + 0.097 = 0.82 To access the energy in zone 4 use the second LDO linear regulator in a parallel configuration with the ADP3335 and set it to output 3.2 V. Input to this regulator is 5.5 V from the boost converter. When the battery voltage drops below 3.5 V, the ADP3335 drops-out and the second regulator takes over. 8.7.5 Peripheral 5.5 V Power The example form factor reference design provides a 5.5 V rail to supply power to LCD, Audio amplifier and Radio modules. An LT1308A boost converter is used. This device supplies up to 1 A at 5.5 V while operating at 600 kHz with up to 90% efficiency at rated load and 3.6 V input. In addition, a low battery voltage detect circuit has an open-drain output. The detect voltage is set at 3.45 V by a resistor divider circuit. When the battery drops below 3.45 V the output transitions to a logic low. This output signal is used as a processor interrupt. PXA250 and PXA210 Applications Processors Design Guide 8-23
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Intel ® PXA250 and PXA210 Applicat
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Contents Contents 1 Introduction...
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Contents A.1 SA-1110 Hardware Migra
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Contents 2-7 SRAM / ROM / Flash / S
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Introduction 1 Table 1-1. Revision
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Introduction • System memory inte
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Introduction Table 1-3. Signal Pin
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Introduction Figure 1-2. PXA250 App
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Introduction Table 1-4. PXA250 Appl
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Introduction Figure 1-3. PXA210 App
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Introduction Table 1-5. PXA210 Appl
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System Memory Interface 2 This sect
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System Memory Interface Table 2-1.
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. System Memory Interface 2.4 SDRAM
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Page 39 and 40: System Memory Interface Figure 2-5.
Page 41 and 42: System Memory Interface Figure 2-6.
Page 43 and 44: System Memory Interface 2.7 System
Page 45 and 46: LCD Display Controller 3 This chapt
Page 47 and 48: LCD Display Controller Figure 3-1.
Page 49 and 50: LCD Display Controller Figure 3-5.
Page 51 and 52: LCD Display Controller Note: This e
Page 53 and 54: LCD Display Controller However, typ
Page 55 and 56: USB Interface 4 4.1 Self Powered De
Page 57 and 58: MultiMediaCard (MMC) 5 The MultiMed
Page 59 and 60: MultiMediaCard (MMC) Figure 5-1. Ap
Page 61 and 62: MultiMediaCard (MMC) Warning: Conne
Page 63 and 64: AC97 6 The AC97 controller unit (AC
Page 65 and 66: I 2 C 7 The Inter-Integrated Circui
Page 67 and 68: . I2C Figure 7-2. Using an Analog S
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Page 75 and 76: Power and Clocking Table 8-6. PXA25
Page 81 and 82: Power and Clocking Figure 8-2. Hard
Page 83 and 84: Power and Clocking Table 8-10. Slee
Page 85 and 86: Power and Clocking Table 8-14. Sync
Page 87 and 88: Power and Clocking Table 8-16. Vari
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Page 93 and 94: JTAG/Debug Port 9 9.1 Description T
Page 95 and 96: SA-1110/Applications Processor Migr
Page 105 and 106: Example Form Factor Reference Desig
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BBPXA2xx Development Baseboard Sche
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DCPXA250 Processor Card 32-bit vers
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DCPXA210 Processor Card 4 CONNECTOR
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Intel PXA250 and PXA210 Applications Processors

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