Intel PXA250 and PXA210 Applications Processors

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Power and Clocking Table 8-18. Synchronous Memory Interface AC Specifications (2.5 V) Symbol Description MIN MAX Notes 1 SDRAM / SMROM tsynCLK tsynCMD tsynRCD tsynCAS tsynSDOS tsynSDOH tsynSDIS tsynDIH tffCLK tffAS tffCES tffADV tffOS tffCEH SDCLK period nSDCAS, nSDRAS, nWE, nSDCS assert time nSDRAS to nSDCAS assert time nSDCAS to nSDCAS assert time MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS, nWE, nOE, SDCKE(1:0), RDnWR output setup time to SDCLK(2:0) rise MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS, nWE, nOE, SDCKE(1:0), RDnWR output hold time from SDCLK(2:0) rise MD(31:0) read data input setup time from SDCLK(2:0) rise MD(31:0) read data input hold time from SDCLK(2:0) rise Fast Flash (Synchronous READS only) SDCLK period MA(25:0) setup to nSDCAS (as nADV) asserted nCS setup to nSDCAS (as nADV) asserted nSDCAS (as nADV) pulse width nSDCAS (as nADV) deassertion to nOE assertion nOE deassertion to nCS deassertion TBD TBD NOTES: 1. These numbers are for a maximum 99.5 MHz MEMCLK and 99.5 MHz output SDCLK. 2. SDCLK for SDRAM and SMROM can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be 99.5 MHz at the fastest. 3. This number represents 1/2 SDCLK period. 4. SDCLK for Fast Flash can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be divide-by-2 of the 132.7 MHz MEMCLK at its fastest. 8.7 Example Form Factor Reference Design Power Delivery Example 8.7.1 Power System Features of the example form factor reference design power system (example in Figure 8-5, “Example Form Factor Reference Design Power System Design” on page 8-22) are: • A standard-size cylindrical single-cell Li+ 3.6 V battery with a 1.8 Ahr capacity • Battery temperature monitoring thermistor during charge cycles • Battery voltage monitoring • Charger supply voltage fault monitoring • Low battery interrupt signal to the microprocessor. 8-20 PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking • Provide power gating switches for the CF, LCD, backlight, RS-232, MMC, Radio, and audio amplifier subsystems • Provide a high-efficiency 5.5 V supply rail for LCD and other devices • Provide a high-efficiency 3.3 V supply rail for I/O and general system power • Provide a high-efficiency 0.8 – 1.3 V Core/PLL supply for the microprocessor • Provide separate, clean power rails for the LCD and Audio subsystems • A small, low-cost, low-heat dissipation pulse-charge method for the battery 8.7.1.1 Power System Configuration The example form factor reference design power system design is described in Figure 8-5, “Example Form Factor Reference Design Power System Design” on page 8-22. Note that there are four main power rails in the system: • 3.3 V I/O power • 0.8-1.3 V Core power • 1.3 V PLL power • 5.5 V power PXA250 and PXA210 Applications Processors Design Guide 8-21
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Intel ® PXA250 and PXA210 Applicat
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Contents Contents 1 Introduction...
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Contents A.1 SA-1110 Hardware Migra
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Contents 2-7 SRAM / ROM / Flash / S
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Introduction 1 Table 1-1. Revision
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Introduction • System memory inte
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Introduction Table 1-3. Signal Pin
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Introduction Figure 1-2. PXA250 App
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Introduction Table 1-4. PXA250 Appl
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Introduction Figure 1-3. PXA210 App
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Introduction Table 1-5. PXA210 Appl
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System Memory Interface 2 This sect
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System Memory Interface Table 2-1.
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. System Memory Interface 2.4 SDRAM
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Page 37 and 38: System Memory Interface Table 2-8.
Page 39 and 40: System Memory Interface Figure 2-5.
Page 41 and 42: System Memory Interface Figure 2-6.
Page 43 and 44: System Memory Interface 2.7 System
Page 45 and 46: LCD Display Controller 3 This chapt
Page 47 and 48: LCD Display Controller Figure 3-1.
Page 49 and 50: LCD Display Controller Figure 3-5.
Page 51 and 52: LCD Display Controller Note: This e
Page 53 and 54: LCD Display Controller However, typ
Page 55 and 56: USB Interface 4 4.1 Self Powered De
Page 57 and 58: MultiMediaCard (MMC) 5 The MultiMed
Page 59 and 60: MultiMediaCard (MMC) Figure 5-1. Ap
Page 61 and 62: MultiMediaCard (MMC) Warning: Conne
Page 63 and 64: AC97 6 The AC97 controller unit (AC
Page 65 and 66: I 2 C 7 The Inter-Integrated Circui
Page 67 and 68: . I2C Figure 7-2. Using an Analog S
Page 69 and 70: Power and Clocking 8 8.1 Operating
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Page 75 and 76: Power and Clocking Table 8-6. PXA25
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Page 83 and 84: Power and Clocking Table 8-10. Slee
Page 85 and 86: Power and Clocking Table 8-14. Sync
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Page 93 and 94: JTAG/Debug Port 9 9.1 Description T
Page 95 and 96: SA-1110/Applications Processor Migr
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BBPXA2xx Development Baseboard Sche
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DCPXA250 Processor Card 32-bit vers
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DCPXA210 Processor Card 4 CONNECTOR
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Intel PXA250 and PXA210 Applications Processors

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