Intel PXA250 and PXA210 Applications Processors

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Power and Clocking Table 8-15. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications (2.5 V) Symbol Description MEMCLK Frequency (MHz) 99.5 118.0 132.7 147.5 165.9 Notes SRAM / ROM / Flash / Synchronous Fast Flash (WRITES) (Asynchronous) tromAS tromAH tromASW tromAHW tromCES tromCEH tromDS tromDSWH tromDH tromNWE MA(25:0) setup to nCS, nOE, nSDCAS (as nADV) asserted MA(25:0) hold after nCS, nOE, nSDCAS (as nADV) deasserted MA(25:0) setup to nWE asserted MA(25:0) hold after nWE deasserted nCS setup to nWE asserted nCS hold after nWE deasserted MD(31:0), DQM(3:0) write data setup to nWE asserted MD(31:0), DQM(3:0) write data setup to nWE deasserted MD(31:0), DQM(3:0) write data hold after nWE deasserted nWE high time between beats of write data NOTES: 1. This number represents 1 MEMCLK period 2. This number represents 3 MEMCLK periods 3. This number represents 2 MEMCLK periods TBD 8-18 PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking Table 8-16. Variable Latency I/O Interface AC Specifications (2.5 V) Symbol Description MEMCLK Frequency (MHz) 99.5 118.0 132.7 147.5 165.9 Notes Variable Latency IO Interface (VLIO) (Asynchronous) tvlioAS tvlioASRW tvlioAH tvlioCES tvlioCEH tvlioDSW tvlioDSWH tvlioDHW tvlioDHR tvlioRDYH MA(25:0) setup to nCS asserted MA(25:0) setup to nOE or nPWE asserted MA(25:0) hold after nOE or nPWE deasserted nCS setup to nOE or nPWE asserted nCS hold after nOE or nPWE deasserted MD(31:0), DQM(3:0) write data setup to nPWE asserted MD(31:0), DQM(3:0) write data setup to nPWE deasserted MD(31:0), DQM(3:0) hold after nPWE deasserted MD(31:0) read data hold after nOE deasserted RDY hold after nOE, nPWE deasserted nPWE, nOE high time between beats of write or read tvlioNPWE data NOTES: 1. This number represents 1 MEMCLK period 2. This number represents 2 MEMCLK periods TBD Table 8-17. Card Interface (PCMCIA or Compact Flash) AC Specifications (2.5 V) Symbol Description MEMCLK Frequency (MHz) 99.5 118.0 132.7 147.5 165.9 Notes tcardAS tcardAH tcardDS tcardDH tcardCMD Card Interface (PCMCIA or Compact Flash) (Asynchronous) MA(25:0), nPREG, PSKTSEL, nPCE setup to nPWE, nPOE, nPIOW, or nPIOR asserted MA(25:0), nPREG, PSKTSEL, nPCE hold after nPWE, nPOE, nPIOW, or nPIOR deasserted MD(31:0) setup to nPWE, nPOE, nPIOW, or nPIOR asserted MD(31:0) hold after nPWE, nPOE, nPIOW, or nPIOR deasserted nPWE, nPOE, nPIOW, or nPIOR command assertion NOTE: 1. These numbers are minimums. They can be much longer based on the programmable Card Interface timing registers. TBD PXA250 and PXA210 Applications Processors Design Guide 8-19
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Intel ® PXA250 and PXA210 Applicat
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Contents Contents 1 Introduction...
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Contents A.1 SA-1110 Hardware Migra
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Contents 2-7 SRAM / ROM / Flash / S
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Introduction 1 Table 1-1. Revision
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Introduction • System memory inte
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Introduction Table 1-3. Signal Pin
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Introduction Figure 1-2. PXA250 App
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Introduction Table 1-4. PXA250 Appl
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Introduction Figure 1-3. PXA210 App
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Introduction Table 1-5. PXA210 Appl
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System Memory Interface 2 This sect
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System Memory Interface Table 2-1.
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. System Memory Interface 2.4 SDRAM
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System Memory Interface Table 2-4.
Page 35 and 36: System Memory Interface Table 2-6.
Page 37 and 38: System Memory Interface Table 2-8.
Page 39 and 40: System Memory Interface Figure 2-5.
Page 41 and 42: System Memory Interface Figure 2-6.
Page 43 and 44: System Memory Interface 2.7 System
Page 45 and 46: LCD Display Controller 3 This chapt
Page 47 and 48: LCD Display Controller Figure 3-1.
Page 49 and 50: LCD Display Controller Figure 3-5.
Page 51 and 52: LCD Display Controller Note: This e
Page 53 and 54: LCD Display Controller However, typ
Page 55 and 56: USB Interface 4 4.1 Self Powered De
Page 57 and 58: MultiMediaCard (MMC) 5 The MultiMed
Page 59 and 60: MultiMediaCard (MMC) Figure 5-1. Ap
Page 61 and 62: MultiMediaCard (MMC) Warning: Conne
Page 63 and 64: AC97 6 The AC97 controller unit (AC
Page 65 and 66: I 2 C 7 The Inter-Integrated Circui
Page 67 and 68: . I2C Figure 7-2. Using an Analog S
Page 69 and 70: Power and Clocking 8 8.1 Operating
Page 71 and 72: Power and Clocking Since few system
Page 73 and 74: Power and Clocking Table 8-4. 32.76
Page 75 and 76: Power and Clocking Table 8-6. PXA25
Page 81 and 82: Power and Clocking Figure 8-2. Hard
Page 83 and 84: Power and Clocking Table 8-10. Slee
Page 85: Power and Clocking Table 8-14. Sync
Page 89 and 90: Power and Clocking • Provide powe
Page 91 and 92: Power and Clocking 8.7.4 I/O 3.3 V
Page 93 and 94: JTAG/Debug Port 9 9.1 Description T
Page 95 and 96: SA-1110/Applications Processor Migr
Page 105 and 106: Example Form Factor Reference Desig
Page 107 and 108: 8 1 7 6 5 4 3 2 Copyright 2002 Inte
Page 109 and 110: 8 1 Sheet 4 of 16 1 7 6 5 4 3 2 Cop
Page 115 and 116: 8 1 Sheet 10 of 16 1 7 6 5 4 3 2 Co
Page 117 and 118: 8 IN_PWR {10,15} D10 1 Pg. 12 7 6 5
Page 119 and 120: 8 C C 1 7 6 5 4 3 2 Copyright 2002
Page 121 and 122: 8 B B A A PXA250 Processor Referenc
Page 123 and 124: BBPXA2xx Development Baseboard Sche
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BBPXA2xx Development Baseboard Sche
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DCPXA250 Processor Card 32-bit vers
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DCPXA210 Processor Card 4 CONNECTOR
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Intel PXA250 and PXA210 Applications Processors

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