Intel PXA250 and PXA210 Applications Processors

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Power and Clocking Table 8-12. Variable Latency I/O Interface AC Specifications (3.3 V) Symbol Description MEMCLK Frequency (MHz) 99.5 118.0 132.7 147.5 165.9 Notes Variable Latency IO Interface (VLIO) (Asynchronous) tvlioAS MA(25:0) setup to nCS asserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 tvlioASRW MA(25:0) setup to nOE or nPWE asserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 tvlioAH MA(25:0) hold after nOE or nPWE deasserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 tvlioCES nCS setup to nOE or nPWE asserted 20 ns 17 ns 15 ns 13.6 ns 12 ns 2 tvlioCEH nCS hold after nOE or nPWE deasserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 tvlioDSW MD(31:0), DQM(3:0) write data setup to nPWE asserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 tvlioDSWH MD(31:0), DQM(3:0) write data setup to nPWE deasserted 20 ns 17 ns 15 ns 13.6 ns 12 ns 2 tvlioDHW MD(31:0), DQM(3:0) hold after nPWE deasserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 tvlioDHR MD(31:0) read data hold after nOE deasserted 0 ns 0 ns 0 ns 0 ns 0 ns — tvlioRDYH RDY hold after nOE, nPWE deasserted 0 ns 0 ns 0 ns 0 ns 0 ns — nPWE, nOE high time between beats of write or read tvlioNPWE data NOTES: 1. This number represents 1 MEMCLK period 2. This number represents 2 MEMCLK periods 20 ns 17 ns 15 ns 13.6 ns 12 ns 2 Table 8-13. Card Interface (PCMCIA or Compact Flash) AC Specifications (3.3 V) Symbol Description MEMCLK Frequency (MHz) 99.5 118.0 132.7 147.5 165.9 Notes tcardAS tcardAH tcardDS Card Interface (PCMCIA or Compact Flash) (Asynchronous) MA(25:0), nPREG, PSKTSEL, nPCE setup to nPWE, nPOE, nPIOW, or nPIOR asserted MA(25:0), nPREG, PSKTSEL, nPCE hold after nPWE, nPOE, nPIOW, or nPIOR deasserted MD(31:0) setup to nPWE, nPOE, nPIOW, or nPIOR asserted 20 ns 17 ns 15 ns 13.6 ns 12 ns 1 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 tcardDH MD(31:0) hold after nPWE, nPOE, nPIOW, or nPIOR deasserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 tcardCMD nPWE, nPOE, nPIOW, or nPIOR command assertion 30 ns 25.5 ns 22.5 ns 20.4 ns 18 ns 1 NOTE: 1. These numbers are minimums. They can be much longer based on the programmable Card Interface timing registers. 8-16 PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking Table 8-14. Synchronous Memory Interface AC Specifications (3.3 V) Symbol Description MIN MAX Notes 1 SDRAM / SMROM tsynCLK SDCLK period 10 ns 20 ns 2 tsynCMD nSDCAS, nSDRAS, nWE, nSDCS assert time 1 sdclk — — tsynRCD nSDRAS to nSDCAS assert time 1 sdclk — — tsynCAS nSDCAS to nSDCAS assert time 2 sdclk — — tsynSDOS MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS, nWE, nOE, SDCKE(1:0), RDnWR output setup time to SDCLK(2:0) rise 5ns — 3 tsynSDOH MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS, nWE, nOE, SDCKE(1:0), RDnWR output hold time from SDCLK(2:0) rise 5ns — 3 tsynSDIS MD(31:0) read data input setup time from SDCLK(2:0) rise 0.5 ns — tsynDIH MD(31:0) read data input hold time from SDCLK(2:0) rise 1.5 ns — — Fast Flash (Synchronous READS only) tffCLK SDCLK period 15 ns 20 ns 4 tffAS MA(25:0) setup to nSDCAS (as nADV) asserted 0.5 sdclk — — tffCES nCS setup to nSDCAS (as nADV) asserted 0.5 sdclk — — tffADV nSDCAS (as nADV) pulse width 1 sdclk — — tffOS nSDCAS (as nADV) deassertion to nOE assertion 3 sdclk — — tffCEH nOE deassertion to nCS deassertion 4 sdclk — — NOTES: 1. These numbers are for a maximum 99.5 MHz MEMCLK and 99.5 MHz output SDCLK. 2. SDCLK for SDRAM and SMROM can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be 99.5 MHz at the fastest. 3. This number represents 1/2 SDCLK period. 4. SDCLK for Fast Flash can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be divide-by-2 of the 132.7 MHz MEMCLK at its fastest. PXA250 and PXA210 Applications Processors Design Guide 8-17
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Intel ® PXA250 and PXA210 Applicat
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Contents Contents 1 Introduction...
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Contents A.1 SA-1110 Hardware Migra
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Contents 2-7 SRAM / ROM / Flash / S
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Introduction 1 Table 1-1. Revision
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Introduction • System memory inte
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Introduction Table 1-3. Signal Pin
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Introduction Figure 1-2. PXA250 App
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Introduction Table 1-4. PXA250 Appl
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Introduction Figure 1-3. PXA210 App
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Introduction Table 1-5. PXA210 Appl
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System Memory Interface 2 This sect
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System Memory Interface Table 2-1.
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. System Memory Interface 2.4 SDRAM
Page 33 and 34: System Memory Interface Table 2-4.
Page 39 and 40: System Memory Interface Figure 2-5.
Page 41 and 42: System Memory Interface Figure 2-6.
Page 43 and 44: System Memory Interface 2.7 System
Page 45 and 46: LCD Display Controller 3 This chapt
Page 47 and 48: LCD Display Controller Figure 3-1.
Page 49 and 50: LCD Display Controller Figure 3-5.
Page 51 and 52: LCD Display Controller Note: This e
Page 53 and 54: LCD Display Controller However, typ
Page 55 and 56: USB Interface 4 4.1 Self Powered De
Page 57 and 58: MultiMediaCard (MMC) 5 The MultiMed
Page 59 and 60: MultiMediaCard (MMC) Figure 5-1. Ap
Page 61 and 62: MultiMediaCard (MMC) Warning: Conne
Page 63 and 64: AC97 6 The AC97 controller unit (AC
Page 65 and 66: I 2 C 7 The Inter-Integrated Circui
Page 67 and 68: . I2C Figure 7-2. Using an Analog S
Page 69 and 70: Power and Clocking 8 8.1 Operating
Page 71 and 72: Power and Clocking Since few system
Page 73 and 74: Power and Clocking Table 8-4. 32.76
Page 75 and 76: Power and Clocking Table 8-6. PXA25
Page 81 and 82: Power and Clocking Figure 8-2. Hard
Page 83: Power and Clocking Table 8-10. Slee
Page 87 and 88: Power and Clocking Table 8-16. Vari
Page 89 and 90: Power and Clocking • Provide powe
Page 91 and 92: Power and Clocking 8.7.4 I/O 3.3 V
Page 93 and 94: JTAG/Debug Port 9 9.1 Description T
Page 95 and 96: SA-1110/Applications Processor Migr
Page 105 and 106: Example Form Factor Reference Desig
Page 107 and 108: 8 1 7 6 5 4 3 2 Copyright 2002 Inte
Page 109 and 110: 8 1 Sheet 4 of 16 1 7 6 5 4 3 2 Cop
Page 115 and 116: 8 1 Sheet 10 of 16 1 7 6 5 4 3 2 Co
Page 117 and 118: 8 IN_PWR {10,15} D10 1 Pg. 12 7 6 5
Page 119 and 120: 8 C C 1 7 6 5 4 3 2 Copyright 2002
Page 121 and 122: 8 B B A A PXA250 Processor Referenc
Page 123 and 124: BBPXA2xx Development Baseboard Sche
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BBPXA2xx Development Baseboard Sche
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DCPXA250 Processor Card 32-bit vers
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DCPXA210 Processor Card 4 CONNECTOR
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