Intel PXA250 and PXA210 Applications Processors
Share Embed Flag
Download ePaper

Intel PXA250 and PXA210 Applications Processors

Intel PXA250 and PXA210 Applications Processors Intel PXA250 and PXA210 Applications Processors

kip.uni.heidelberg.de
from kip.uni.heidelberg.de More from this publisher
21.03.2014 Views

Power and Clocking Note: If Hardware Reset is entered during Sleep Mode, the proper power-supply stabilization times and nRESET timing requirements indicated in Table 8-7, “Power-On Timing Specifications” on page 8-12 must be observed. Figure 8-1. Power-On Reset Timing t R_VCCQ VCCQ, PWR_EN t R_VCCN VCCN VCC nTRST t D_VCCN t D_VCC t R_VCC t D_NTRST t D_JTAG JTAG PINS nRESET t D_NRESET nRESET_OUT t D_OUT Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET_OUT is deasserted or PXA250 enters Sleep Mode Table 8-7. Power-On Timing Specifications Symbol Description Min Typical Max t R_VCCQ VCCQ Rise / Stabilization time 0.01 ms — 100 ms t R_VCCN VCCN Rise / Stabilization time 0.01 ms — 100 ms t R_VCC VCC, PLL_VCC Rise / Stabilization time 0.01 ms — 10 ms t D_VCCN Delay between VCCQ stable and VCCN applied 0ms — — t D_VCC Delay from VCCN stable and VCC, PLL_VCC applied 0ms — — t D_NTRST Delay between VCC, PLL_VCC stable and nTRST deasserted 50 ms — — t D_JTAG t D_NRESET t D_OUT Delay between nTRST deasserted and JTAG pins active, with nRESET asserted Delay between VCC, PLL_VCC stable and nRESET deasserted Delay between nRESET deasserted and nRESET_OUT deasserted 0.03 ms — — 50 ms — — 18.1 ms — 18.2 ms 8.5.3 Hardware Reset Timing The timing sequences shown in Figure 8-2 “Hardware Reset Timing” assumes the power supplies are stable at the assertion of nRESET. If the power supplies are unstable, follow the timings indicated in Section 8.5.2, “Power On Timing” on page 11. 8-12 PXA250 and PXA210 Applications Processors Design Guide

Power and Clocking Figure 8-2. Hardware Reset Timing nRESET nRESET_OUT t DHW_NRESET t DHW_OUT t DHW_OUT_A Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is deasserted or PXA250 enters Sleep Mode Table 8-8. Hardware Reset Timing Specifications Symbol Description Min Typical Max t DHW_NRESET Minimum assertion time of nRESET 0.001 ms — — t DHW_OUT_A Delay between nRESET Asserted and nRESET_OUT Asserted 0ms — 0.001 ms t DHW_OUT Delay between nRESET deasserted and nRESET_OUT deasserted 18.1 ms — 18.2 ms 8.5.4 Watchdog Reset Timing Watchdog Reset is an internally generated reset and therefore has no external pin dependencies. The nRESET_OUT pin is the only indicator of Watchdog Reset, and it stays asserted for t DHW_OUT . Refer to Figure 8-2, “Hardware Reset Timing” on page 8-13 for more information. 8.5.5 GPIO Reset Timing GPIO Reset is generated externally. The pin used as the GPIO Reset is reconfigured as a standard GPIO after the reset propagates internally. Because the clock module is not reset by GPIO Reset, timing varies based on the frequency of the selected clock. Timing also varies in the Frequency Change Sequence (see Section 8.4.1, “32.768 kHz Oscillator Specifications” on page 4). Figure 8-3 “GPIO Reset Timing” shows the possible GPIO Reset timing. Figure 8-3. GPIO Reset Timing t A_GP[1] GP[1] nRESET_OUT t DGP_OUT t DGP_OUT_A Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is deasserted or PXA250 enters Sleep Mode PXA250 and PXA210 Applications Processors Design Guide 8-13

Power <strong>and</strong> Clocking<br />

Figure 8-2. Hardware Reset Timing<br />

nRESET<br />

nRESET_OUT<br />

t DHW_NRESET<br />

t DHW_OUT<br />

t DHW_OUT_A<br />

Note: nBATT_FAULT <strong>and</strong> nVDD_FAULT must be high before nRESET is deasserted<br />

or <strong>PXA250</strong> enters Sleep Mode<br />

Table 8-8. Hardware Reset Timing Specifications<br />

Symbol Description Min Typical Max<br />

t DHW_NRESET Minimum assertion time of nRESET 0.001 ms — —<br />

t DHW_OUT_A Delay between nRESET Asserted <strong>and</strong> nRESET_OUT Asserted 0ms — 0.001 ms<br />

t DHW_OUT<br />

Delay between nRESET deasserted <strong>and</strong> nRESET_OUT<br />

deasserted<br />

18.1 ms — 18.2 ms<br />

8.5.4 Watchdog Reset Timing<br />

Watchdog Reset is an internally generated reset <strong>and</strong> therefore has no external pin dependencies.<br />

The nRESET_OUT pin is the only indicator of Watchdog Reset, <strong>and</strong> it stays asserted for<br />

t DHW_OUT . Refer to Figure 8-2, “Hardware Reset Timing” on page 8-13 for more information.<br />

8.5.5 GPIO Reset Timing<br />

GPIO Reset is generated externally. The pin used as the GPIO Reset is reconfigured as a st<strong>and</strong>ard<br />

GPIO after the reset propagates internally. Because the clock module is not reset by GPIO Reset,<br />

timing varies based on the frequency of the selected clock. Timing also varies in the Frequency<br />

Change Sequence (see Section 8.4.1, “32.768 kHz Oscillator Specifications” on page 4). Figure<br />

8-3 “GPIO Reset Timing” shows the possible GPIO Reset timing.<br />

Figure 8-3. GPIO Reset Timing<br />

t A_GP[1]<br />

GP[1]<br />

nRESET_OUT<br />

t DGP_OUT<br />

t DGP_OUT_A<br />

Note: nBATT_FAULT <strong>and</strong> nVDD_FAULT must be high before nRESET is deasserted<br />

or <strong>PXA250</strong> enters Sleep Mode<br />

<strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide 8-13

logo

products

Resources

Company

Terms of service
Privacy policy
Cookie policy
Cookie settings
Imprint
Change language
Made with love in Switzerland
© 2024 Yumpu.com all rights reserved

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!