Intel PXA250 and PXA210 Applications Processors

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Power and Clocking Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 5 of 6) Pin Pin Count Alt_fn 1-(in) Alt_fn 2-(in) Alt_fn 1-(out) Alt_fn 2-(out) Signal Description and Comments Power Supply GP40 1 DTR FFUART data terminal Ready VCCQ GP41 1 RTS FFUART request to send VCCQ GP42 1 BTRXD BTUART receive data VCCQ GP43 1 BTTXD BTUART transmit data VCCQ GP44 1 CTS BTUART clear to send VCCQ GP45 1 RTS BTUART request to send VCCQ GP46 1 ICP_RXD RXD ICP receive data STD_UART receive data VCCQ GP47 1 TXD ICP_TXD STD_UART transmit data ICP transmit data VCCQ GP58 1 LDD[0] LCD data pin 0 VCCQ GP59 1 LDD[1] LCD data pin 1 VCCQ GP60 1 LDD[2] LCD data pin 2 VCCQ GP61 1 LDD[3] LCD data pin 3 VCCQ GP62 1 LDD[4] LCD data pin 4 VCCQ GP63 1 LDD[5] LCD data pin 5 VCCQ GP64 1 LDD[6] LCD data pin 6 VCCQ GP65 1 LDD[7] LCD data pin 7 VCCQ GP66 1 MBREQ LDD[8] LCD data pin 8 Alternate Bus Master Request VCCQ GP67 1 LDD[9] LCD data pin 9 MMCCS0 MMC Chip Select 0 VCCQ GP68 1 MMCCS1 MMC Chip Select 1 LDD[10] LCD data pin 10 VCCQ GP69 1 MMCCLK MMC_CLK LDD[11] LCD data pin 11 VCCQ GP70 1 RTCCLK Real Time clock (1Hz) LDD[12] LCD data pin 12 VCCQ GP71 1 GP72 1 3.6 MHz 3.6MHz Oscillator clock LDD[13] LCD data pin 13 32 KHz 32 KHz clock LDD[14] LCD data pin 14 VCCQ VCCQ 8-10 PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 6 of 6) Pin Pin Count Alt_fn 1-(in) Alt_fn 2-(in) Alt_fn 1-(out) Alt_fn 2-(out) Signal Description and Comments Power Supply GP73 1 MBGNT LDD[15] LCD data pin 15 memory controller grant VCCQ GP74 1 LCD_FCL K LCD Frame clock VCCQ GP75 1 LCD_LCL K LCD line clock VCCQ GP76 1 LCD_PCL K LCD Pixel clock VCCQ GP77 1 LCD_AC BIAS LCD AC Bias VCCQ PXTAL 1 3.6Mhz Crystal input 0.8 * VCC PEXTAL 1 3.6Mhz Crystal output 0.8 * VCC TXTAL 1 32khz Crystal input 0.8 * VCC TEXTAL 1 32khz Crystal output 0.8 * VCC 8.5.2 Power On Timing The External Voltage Regulator and other power-on devices must provide the applications processor with a specific sequence of power and resets to ensure proper operation. This sequence is shown in Figure 8-1, “Power-On Reset Timing” on page 8-12 and detailed in Table 8-7, “Power- On Timing Specifications” on page 8-12. It is important that the applications processor power supplies be powered-up in a certain order to avoid high current situations. The required order is: 1. VCCQ 2. VCCN 3. VCC and PLL_VCC VCCN may be powered at the same time as VCCQ, however do not apply power to VCCN before powering VCCQ. PXA250 and PXA210 Applications Processors Design Guide 8-11
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Intel ® PXA250 and PXA210 Applicat
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Contents Contents 1 Introduction...
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Contents A.1 SA-1110 Hardware Migra
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Contents 2-7 SRAM / ROM / Flash / S
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Introduction 1 Table 1-1. Revision
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Introduction • System memory inte
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Introduction Table 1-3. Signal Pin
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Introduction Figure 1-2. PXA250 App
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Introduction Table 1-4. PXA250 Appl
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Introduction Figure 1-3. PXA210 App
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Introduction Table 1-5. PXA210 Appl
Page 27 and 28: System Memory Interface 2 This sect
Page 29 and 30: System Memory Interface Table 2-1.
Page 31 and 32: . System Memory Interface 2.4 SDRAM
Page 39 and 40: System Memory Interface Figure 2-5.
Page 41 and 42: System Memory Interface Figure 2-6.
Page 43 and 44: System Memory Interface 2.7 System
Page 45 and 46: LCD Display Controller 3 This chapt
Page 47 and 48: LCD Display Controller Figure 3-1.
Page 49 and 50: LCD Display Controller Figure 3-5.
Page 51 and 52: LCD Display Controller Note: This e
Page 53 and 54: LCD Display Controller However, typ
Page 55 and 56: USB Interface 4 4.1 Self Powered De
Page 57 and 58: MultiMediaCard (MMC) 5 The MultiMed
Page 59 and 60: MultiMediaCard (MMC) Figure 5-1. Ap
Page 61 and 62: MultiMediaCard (MMC) Warning: Conne
Page 63 and 64: AC97 6 The AC97 controller unit (AC
Page 65 and 66: I 2 C 7 The Inter-Integrated Circui
Page 67 and 68: . I2C Figure 7-2. Using an Analog S
Page 69 and 70: Power and Clocking 8 8.1 Operating
Page 71 and 72: Power and Clocking Since few system
Page 73 and 74: Power and Clocking Table 8-4. 32.76
Page 75 and 76: Power and Clocking Table 8-6. PXA25
Page 77: Power and Clocking Table 8-6. PXA25
Page 81 and 82: Power and Clocking Figure 8-2. Hard
Page 83 and 84: Power and Clocking Table 8-10. Slee
Page 85 and 86: Power and Clocking Table 8-14. Sync
Page 87 and 88: Power and Clocking Table 8-16. Vari
Page 89 and 90: Power and Clocking • Provide powe
Page 91 and 92: Power and Clocking 8.7.4 I/O 3.3 V
Page 93 and 94: JTAG/Debug Port 9 9.1 Description T
Page 95 and 96: SA-1110/Applications Processor Migr
Page 105 and 106: Example Form Factor Reference Desig
Page 107 and 108: 8 1 7 6 5 4 3 2 Copyright 2002 Inte
Page 109 and 110: 8 1 Sheet 4 of 16 1 7 6 5 4 3 2 Cop
Page 115 and 116: 8 1 Sheet 10 of 16 1 7 6 5 4 3 2 Co
Page 117 and 118: 8 IN_PWR {10,15} D10 1 Pg. 12 7 6 5
Page 119 and 120: 8 C C 1 7 6 5 4 3 2 Copyright 2002
Page 121 and 122: 8 B B A A PXA250 Processor Referenc
Page 123 and 124: BBPXA2xx Development Baseboard Sche
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BBPXA2xx Development Baseboard Sche
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DCPXA250 Processor Card 32-bit vers
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DCPXA210 Processor Card 4 CONNECTOR
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Intel PXA250 and PXA210 Applications Processors

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