Intel PXA250 and PXA210 Applications Processors

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Power and Clocking Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 3 of 6) Pin Pin Count Alt_fn 1-(in) Alt_fn 2-(in) Alt_fn 1-(out) Alt_fn 2-(out) Signal Description and Comments Power Supply MMCMD 1 MMC Command VCCQ MMDAT 1 MMC Data VCCQ AC_RESET_n 1 ac97 RESET VCCQ UDC+ 1 USB client high differential signal VCCQ UDC- 1 USB client low differential signal VCCQ SCL 1 I2C Clock VCCQ SDA 1 I2C Bidirectional Data VCCQ nRESET 1 Hardware reset VCCQ nRESET_OUT 1 Reset output VCCQ BOOT_SEL[2:0] 3 ROM Width Select (16/32) VCCQ PWR_EN 1 power enable VCCQ nBATT_FAULT 1 Battery Fault VCCQ nVDD_FAULT 1 VDD Fault VCCQ nTRST 1 JTAG Reset VCCQ TDI 1 JTAG Data In VCCQ TDO 1 JTAG Data Out VCCQ TMS 1 JTAG Mode Select VCCQ TCK 1 JTAG Clock VCCQ TESTCLK 1 TEST Clock VCCQ TEST 1 TEST mode VCCQ GP0 1 Reserved for sleep wakeup VCCQ GP1 1 GP_RST Active low GP_reset VCCQ GP2 1 General Purpose I/O pin VCCQ GP3 1 General Purpose I/O pin VCCQ GP4 1 General Purpose I/O pin VCCQ GP5 1 General Purpose I/O pin VCCQ GP6 1 MMCCLK MMC Clock VCCQ GP7 1 48 MHz 48 mhz clock output VCCQ GP8 1 MMCCS0 MMC Chip Select 0 VCCQ GP9 1 MMCCS1 MMC Chip Select 1 VCCQ GP10 1 RTCCLK real time clock (1Hz) VCCQ 8-8 PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 4 of 6) Pin Pin Count Alt_fn 1-(in) Alt_fn 2-(in) Alt_fn 1-(out) Alt_fn 2-(out) Signal Description and Comments Power Supply GP11 1 3.6 MHz 3.6 MHz oscillator out VCCQ GP12 1 32 KHz 32 KHz out VCCQ GP13 1 MBGNT memory controller grant VCCQ GP14 1 MBREQ Alternate Bus Master Request VCCQ GP16 1 PWM0 PWM0 output VCCQ GP17 1 PWM1 PWM1 output VCCQ GP23 1 SCLK SSP clock VCCQ GP24 1 SFRM SSP Frame VCCQ GP25 1 TXD SSP transmit VCCQ GP26 1 RXD SSP receive VCCQ GP27 1 EXTCLK SSP ext_clk VCCQ BITCLK AC97 bit_clk GP28 1 BITCLK BITCLK I2S bit_clk I2S bit_clk VCCQ BITCLK AC97 bit_clk GP29 1 SDATA_IN0 SDATA_ IN AC97 Sdata_in0 I2S Sdata_in VCCQ GP30 1 SDATA_ OUT SDATA_ OUT I2S Sdata_out AC97 Sdata_out VCCQ GP31 1 SYNC SYNC I2S sync AC97 sync VCCQ GP32 1 SDATA_IN1 SYSCLK I2S sysclk AC97 Sdata_in1 VCCQ GP34 1 FFRXD FFUART receive MMCCS0 MMC Chip Select 0 VCCQ GP35 1 CTS FFUART Clear to send VCCQ GP36 1 DCD FFUART Data carrier detect VCCQ GP37 1 DSR FFUART data set ready VCCQ GP38 1 RI FFUART Ring Indicator VCCQ GP39 1 MMCCS1 MMC Chip Select 1 FFTXD FFUART transmit data VCCQ PXA250 and PXA210 Applications Processors Design Guide 8-9
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Intel ® PXA250 and PXA210 Applicat
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Contents Contents 1 Introduction...
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Contents A.1 SA-1110 Hardware Migra
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Contents 2-7 SRAM / ROM / Flash / S
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Introduction 1 Table 1-1. Revision
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Introduction • System memory inte
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Introduction Table 1-3. Signal Pin
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Page 17 and 18:
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Introduction Figure 1-2. PXA250 App
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Introduction Table 1-4. PXA250 Appl
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Introduction Figure 1-3. PXA210 App
Page 25 and 26: Introduction Table 1-5. PXA210 Appl
Page 27 and 28: System Memory Interface 2 This sect
Page 29 and 30: System Memory Interface Table 2-1.
Page 31 and 32: . System Memory Interface 2.4 SDRAM
Page 39 and 40: System Memory Interface Figure 2-5.
Page 41 and 42: System Memory Interface Figure 2-6.
Page 43 and 44: System Memory Interface 2.7 System
Page 45 and 46: LCD Display Controller 3 This chapt
Page 47 and 48: LCD Display Controller Figure 3-1.
Page 49 and 50: LCD Display Controller Figure 3-5.
Page 51 and 52: LCD Display Controller Note: This e
Page 53 and 54: LCD Display Controller However, typ
Page 55 and 56: USB Interface 4 4.1 Self Powered De
Page 57 and 58: MultiMediaCard (MMC) 5 The MultiMed
Page 59 and 60: MultiMediaCard (MMC) Figure 5-1. Ap
Page 61 and 62: MultiMediaCard (MMC) Warning: Conne
Page 63 and 64: AC97 6 The AC97 controller unit (AC
Page 65 and 66: I 2 C 7 The Inter-Integrated Circui
Page 67 and 68: . I2C Figure 7-2. Using an Analog S
Page 69 and 70: Power and Clocking 8 8.1 Operating
Page 71 and 72: Power and Clocking Since few system
Page 73 and 74: Power and Clocking Table 8-4. 32.76
Page 75: Power and Clocking Table 8-6. PXA25
Page 79 and 80: Power and Clocking Table 8-6. PXA25
Page 81 and 82: Power and Clocking Figure 8-2. Hard
Page 83 and 84: Power and Clocking Table 8-10. Slee
Page 85 and 86: Power and Clocking Table 8-14. Sync
Page 87 and 88: Power and Clocking Table 8-16. Vari
Page 89 and 90: Power and Clocking • Provide powe
Page 91 and 92: Power and Clocking 8.7.4 I/O 3.3 V
Page 93 and 94: JTAG/Debug Port 9 9.1 Description T
Page 95 and 96: SA-1110/Applications Processor Migr
Page 105 and 106: Example Form Factor Reference Desig
Page 107 and 108: 8 1 7 6 5 4 3 2 Copyright 2002 Inte
Page 109 and 110: 8 1 Sheet 4 of 16 1 7 6 5 4 3 2 Cop
Page 115 and 116: 8 1 Sheet 10 of 16 1 7 6 5 4 3 2 Co
Page 117 and 118: 8 IN_PWR {10,15} D10 1 Pg. 12 7 6 5
Page 119 and 120: 8 C C 1 7 6 5 4 3 2 Copyright 2002
Page 121 and 122: 8 B B A A PXA250 Processor Referenc
Page 123 and 124: BBPXA2xx Development Baseboard Sche
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BBPXA2xx Development Baseboard Sche
Page 164:
DCPXA250 Processor Card 32-bit vers
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DCPXA210 Processor Card 4 CONNECTOR
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Intel PXA250 and PXA210 Applications Processors

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