Intel PXA250 and PXA210 Applications Processors
Intel PXA250 and PXA210 Applications Processors Intel PXA250 and PXA210 Applications Processors
Power and Clocking Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 3 of 6) Pin Pin Count Alt_fn 1-(in) Alt_fn 2-(in) Alt_fn 1-(out) Alt_fn 2-(out) Signal Description and Comments Power Supply MMCMD 1 MMC Command VCCQ MMDAT 1 MMC Data VCCQ AC_RESET_n 1 ac97 RESET VCCQ UDC+ 1 USB client high differential signal VCCQ UDC- 1 USB client low differential signal VCCQ SCL 1 I2C Clock VCCQ SDA 1 I2C Bidirectional Data VCCQ nRESET 1 Hardware reset VCCQ nRESET_OUT 1 Reset output VCCQ BOOT_SEL[2:0] 3 ROM Width Select (16/32) VCCQ PWR_EN 1 power enable VCCQ nBATT_FAULT 1 Battery Fault VCCQ nVDD_FAULT 1 VDD Fault VCCQ nTRST 1 JTAG Reset VCCQ TDI 1 JTAG Data In VCCQ TDO 1 JTAG Data Out VCCQ TMS 1 JTAG Mode Select VCCQ TCK 1 JTAG Clock VCCQ TESTCLK 1 TEST Clock VCCQ TEST 1 TEST mode VCCQ GP0 1 Reserved for sleep wakeup VCCQ GP1 1 GP_RST Active low GP_reset VCCQ GP2 1 General Purpose I/O pin VCCQ GP3 1 General Purpose I/O pin VCCQ GP4 1 General Purpose I/O pin VCCQ GP5 1 General Purpose I/O pin VCCQ GP6 1 MMCCLK MMC Clock VCCQ GP7 1 48 MHz 48 mhz clock output VCCQ GP8 1 MMCCS0 MMC Chip Select 0 VCCQ GP9 1 MMCCS1 MMC Chip Select 1 VCCQ GP10 1 RTCCLK real time clock (1Hz) VCCQ 8-8 PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 4 of 6) Pin Pin Count Alt_fn 1-(in) Alt_fn 2-(in) Alt_fn 1-(out) Alt_fn 2-(out) Signal Description and Comments Power Supply GP11 1 3.6 MHz 3.6 MHz oscillator out VCCQ GP12 1 32 KHz 32 KHz out VCCQ GP13 1 MBGNT memory controller grant VCCQ GP14 1 MBREQ Alternate Bus Master Request VCCQ GP16 1 PWM0 PWM0 output VCCQ GP17 1 PWM1 PWM1 output VCCQ GP23 1 SCLK SSP clock VCCQ GP24 1 SFRM SSP Frame VCCQ GP25 1 TXD SSP transmit VCCQ GP26 1 RXD SSP receive VCCQ GP27 1 EXTCLK SSP ext_clk VCCQ BITCLK AC97 bit_clk GP28 1 BITCLK BITCLK I2S bit_clk I2S bit_clk VCCQ BITCLK AC97 bit_clk GP29 1 SDATA_IN0 SDATA_ IN AC97 Sdata_in0 I2S Sdata_in VCCQ GP30 1 SDATA_ OUT SDATA_ OUT I2S Sdata_out AC97 Sdata_out VCCQ GP31 1 SYNC SYNC I2S sync AC97 sync VCCQ GP32 1 SDATA_IN1 SYSCLK I2S sysclk AC97 Sdata_in1 VCCQ GP34 1 FFRXD FFUART receive MMCCS0 MMC Chip Select 0 VCCQ GP35 1 CTS FFUART Clear to send VCCQ GP36 1 DCD FFUART Data carrier detect VCCQ GP37 1 DSR FFUART data set ready VCCQ GP38 1 RI FFUART Ring Indicator VCCQ GP39 1 MMCCS1 MMC Chip Select 1 FFTXD FFUART transmit data VCCQ PXA250 and PXA210 Applications Processors Design Guide 8-9
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- Page 29 and 30: System Memory Interface Table 2-1.
- Page 31 and 32: . System Memory Interface 2.4 SDRAM
- Page 33 and 34: System Memory Interface Table 2-4.
- Page 35 and 36: System Memory Interface Table 2-6.
- Page 37 and 38: System Memory Interface Table 2-8.
- Page 39 and 40: System Memory Interface Figure 2-5.
- Page 41 and 42: System Memory Interface Figure 2-6.
- Page 43 and 44: System Memory Interface 2.7 System
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- Page 55 and 56: USB Interface 4 4.1 Self Powered De
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Power <strong>and</strong> Clocking<br />
Table 8-6. <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> VCCN vs. VCCQ (Sheet 3 of 6)<br />
Pin<br />
Pin<br />
Count<br />
Alt_fn<br />
1-(in)<br />
Alt_fn<br />
2-(in)<br />
Alt_fn<br />
1-(out)<br />
Alt_fn<br />
2-(out)<br />
Signal Description <strong>and</strong><br />
Comments<br />
Power<br />
Supply<br />
MMCMD 1 MMC Comm<strong>and</strong> VCCQ<br />
MMDAT 1 MMC Data VCCQ<br />
AC_RESET_n 1 ac97 RESET VCCQ<br />
UDC+ 1 USB client high differential signal VCCQ<br />
UDC- 1 USB client low differential signal VCCQ<br />
SCL 1 I2C Clock VCCQ<br />
SDA 1 I2C Bidirectional Data VCCQ<br />
nRESET 1 Hardware reset VCCQ<br />
nRESET_OUT 1 Reset output VCCQ<br />
BOOT_SEL[2:0] 3 ROM Width Select (16/32) VCCQ<br />
PWR_EN 1 power enable VCCQ<br />
nBATT_FAULT 1 Battery Fault VCCQ<br />
nVDD_FAULT 1 VDD Fault VCCQ<br />
nTRST 1 JTAG Reset VCCQ<br />
TDI 1 JTAG Data In VCCQ<br />
TDO 1 JTAG Data Out VCCQ<br />
TMS 1 JTAG Mode Select VCCQ<br />
TCK 1 JTAG Clock VCCQ<br />
TESTCLK 1 TEST Clock VCCQ<br />
TEST 1 TEST mode VCCQ<br />
GP0 1 Reserved for sleep wakeup VCCQ<br />
GP1 1 GP_RST Active low GP_reset VCCQ<br />
GP2 1 General Purpose I/O pin VCCQ<br />
GP3 1 General Purpose I/O pin VCCQ<br />
GP4 1 General Purpose I/O pin VCCQ<br />
GP5 1 General Purpose I/O pin VCCQ<br />
GP6 1 MMCCLK MMC Clock VCCQ<br />
GP7 1 48 MHz 48 mhz clock output VCCQ<br />
GP8 1 MMCCS0 MMC Chip Select 0 VCCQ<br />
GP9 1 MMCCS1 MMC Chip Select 1 VCCQ<br />
GP10 1 RTCCLK real time clock (1Hz) VCCQ<br />
8-8 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
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