Intel PXA250 and PXA210 Applications Processors

More documents

Recommendations

Info

Power and Clocking • Drive the PEXTAL pin with a digital signal that has a low level near 0 V and a high level near VCC. Do not exceed VCC or go below VSS by more than 100 mV. The minimum slew rate is 1 V per 100 ns. The maximum current drawn by the external clock source when the clock is at its maximum positive voltage should be about 1 mA. • Float the PXTAL pin or drive it complementary to the PEXTAL pin, using the same voltage level, slew rate, and input current restrictions. If floated, some degree of noise susceptibility will be introduced in the system, and it is therefore not recommended. 8.5 Reset and Power AC Timing Specifications The applications processor asserts the nRESET_OUT pin in one of several modes: • Power On • Hardware Reset • Watchdog Reset • GPIO Reset • Sleep Mode The following sections give the timing and other specifications for the entry and exit of these modes. 8.5.1 Power Supply Connectivity The PXA250 applications processor requires two or three externally-supplied voltage levels. VCCQ requires high voltage, VCCN requires high or medium voltage, and VCC and PLL_VCC require low voltage. PLL_VCC must be separated from other low voltage supplies. Depending on the availability of independent regulator outputs and the desired memory voltage, VCCQ may have to be separated from VCCN. VCCN does not have to be separated at the board level. Note: Shaded sections are not supported for the PXA210 applications processor. Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 1 of 6) Pin Pin Count Alt_fn 1-(in) Alt_fn 2-(in) Alt_fn 1-(out) Alt_fn 2-(out) Signal Description and Comments Power Supply MA(25:0) 26 Main Memory Address Bus VCCN MD(31:16) 16 Main Memory Data Bus (high) VCCN MD(15:0) 16 Main Memory Data Bus (low) VCCN nOE 1 Main Memory Bus Output Enable VCCN nWE 1 Main Memory Bus Write Enable VCCN nSDRAS 1 Main Memory Bus RAS VCCN nSDCAS 1 Main Memory Bus CAS VCCN DQM(3:2) 2 Main Memory Bus SDRAM byte selects VCCN 8-6 PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 2 of 6) Pin Pin Count Alt_fn 1-(in) Alt_fn 2-(in) Alt_fn 1-(out) Alt_fn 2-(out) Signal Description and Comments Power Supply DQM(1:0) 2 nSDCS(3:2) 2 nSDCS(1:0) 2 SDCKE(1:0) 2 Main Memory Bus SDRAM byte selects Main Memory Bus SDRAM chip selects Main Memory Bus SDRAM chip selects Main Memory Bus SDRAM clock enable VCCN VCCN VCCN VCCN SDCLK(2) 1 Main Memory Bus SDRAM clocks VCCN SDCLK(1:0) 2 Main Memory Bus SDRAM clocks VCCN RD/nWR 1 CC Steering Signal VCCN CS(0) 1 Static chip selects VCCN GP15 1 nCS_1 Active low chip select 1 VCCN GP18 1 RDY Ext. Bus Ready VCCN GP19 1 DREQ[1] Ext. Bus Master Request VCCN GP20 1 DREQ[0] Ext. Bus Master Request VCCN GP21 1 General Purpose I/O pin VCCN GP22 1 General Purpose I/O pin VCCN GP33 1 nCS[5] Active low chip select 5 VCCN GP48 1 nPOE Output Enable for Card Space VCCN GP49 1 nPWE Write Enable for Card Space VCCN GP50 1 nPIOR I/O Read for Card Space VCCN GP51 1 nPIOW I/O Write for Card Space VCCN GP52 1 nPCE[1] Card Enable for Card Space VCCN GP53 1 MMCCLK nPCE[2] Card Enable for Card Space MMC CLock VCCN GP54 1 MMCCLK pSKTSEL MMC CLock Socket Select for Card Space VCCN GP55 1 nPREG Card Address bit 26 VCCN GP56 1 nPWAIT Wait signal for Card Space VCCN GP57 1 nIOIS16 Bus Width select for I/O Card Space VCCN GP78 1 nCS[2] Active low chip select 2 VCCN GP79 1 nCS[3] Active low chip select 3 VCCN GP80 1 nCS[4] Active low chip select 4 VCCN PXA250 and PXA210 Applications Processors Design Guide 8-7
Page 1 and 2:
Intel ® PXA250 and PXA210 Applicat
Page 3 and 4:
Contents Contents 1 Introduction...
Page 5 and 6:
Contents A.1 SA-1110 Hardware Migra
Page 7 and 8:
Contents 2-7 SRAM / ROM / Flash / S
Page 9 and 10:
Introduction 1 Table 1-1. Revision
Page 11 and 12:
Introduction • System memory inte
Page 13 and 14:
Introduction Table 1-3. Signal Pin
Page 15 and 16:
Page 17 and 18:
Page 19 and 20:
Introduction Figure 1-2. PXA250 App
Page 21 and 22:
Introduction Table 1-4. PXA250 Appl
Page 23 and 24: Introduction Figure 1-3. PXA210 App
Page 25 and 26: Introduction Table 1-5. PXA210 Appl
Page 27 and 28: System Memory Interface 2 This sect
Page 29 and 30: System Memory Interface Table 2-1.
Page 31 and 32: . System Memory Interface 2.4 SDRAM
Page 39 and 40: System Memory Interface Figure 2-5.
Page 41 and 42: System Memory Interface Figure 2-6.
Page 43 and 44: System Memory Interface 2.7 System
Page 45 and 46: LCD Display Controller 3 This chapt
Page 47 and 48: LCD Display Controller Figure 3-1.
Page 49 and 50: LCD Display Controller Figure 3-5.
Page 51 and 52: LCD Display Controller Note: This e
Page 53 and 54: LCD Display Controller However, typ
Page 55 and 56: USB Interface 4 4.1 Self Powered De
Page 57 and 58: MultiMediaCard (MMC) 5 The MultiMed
Page 59 and 60: MultiMediaCard (MMC) Figure 5-1. Ap
Page 61 and 62: MultiMediaCard (MMC) Warning: Conne
Page 63 and 64: AC97 6 The AC97 controller unit (AC
Page 65 and 66: I 2 C 7 The Inter-Integrated Circui
Page 67 and 68: . I2C Figure 7-2. Using an Analog S
Page 69 and 70: Power and Clocking 8 8.1 Operating
Page 71 and 72: Power and Clocking Since few system
Page 73: Power and Clocking Table 8-4. 32.76
Page 77 and 78: Power and Clocking Table 8-6. PXA25
Page 79 and 80: Power and Clocking Table 8-6. PXA25
Page 81 and 82: Power and Clocking Figure 8-2. Hard
Page 83 and 84: Power and Clocking Table 8-10. Slee
Page 85 and 86: Power and Clocking Table 8-14. Sync
Page 87 and 88: Power and Clocking Table 8-16. Vari
Page 89 and 90: Power and Clocking • Provide powe
Page 91 and 92: Power and Clocking 8.7.4 I/O 3.3 V
Page 93 and 94: JTAG/Debug Port 9 9.1 Description T
Page 95 and 96: SA-1110/Applications Processor Migr
Page 105 and 106: Example Form Factor Reference Desig
Page 107 and 108: 8 1 7 6 5 4 3 2 Copyright 2002 Inte
Page 109 and 110: 8 1 Sheet 4 of 16 1 7 6 5 4 3 2 Cop
Page 115 and 116: 8 1 Sheet 10 of 16 1 7 6 5 4 3 2 Co
Page 117 and 118: 8 IN_PWR {10,15} D10 1 Pg. 12 7 6 5
Page 119 and 120: 8 C C 1 7 6 5 4 3 2 Copyright 2002
Page 121 and 122: 8 B B A A PXA250 Processor Referenc
Page 123 and 124: BBPXA2xx Development Baseboard Sche
Page 162 and 163:
BBPXA2xx Development Baseboard Sche
Page 164:
DCPXA250 Processor Card 32-bit vers
Page 176:
DCPXA210 Processor Card 4 CONNECTOR
show all

Intel PXA250 and PXA210 Applications Processors

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?