Intel PXA250 and PXA210 Applications Processors
Intel PXA250 and PXA210 Applications Processors
Intel PXA250 and PXA210 Applications Processors
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Power <strong>and</strong> Clocking<br />
• Drive the PEXTAL pin with a digital signal that has a low level near 0 V <strong>and</strong> a high level near<br />
VCC. Do not exceed VCC or go below VSS by more than 100 mV. The minimum slew rate is<br />
1 V per 100 ns. The maximum current drawn by the external clock source when the clock is at<br />
its maximum positive voltage should be about 1 mA.<br />
• Float the PXTAL pin or drive it complementary to the PEXTAL pin, using the same voltage<br />
level, slew rate, <strong>and</strong> input current restrictions. If floated, some degree of noise susceptibility<br />
will be introduced in the system, <strong>and</strong> it is therefore not recommended.<br />
8.5 Reset <strong>and</strong> Power AC Timing Specifications<br />
The applications processor asserts the nRESET_OUT pin in one of several modes:<br />
• Power On<br />
• Hardware Reset<br />
• Watchdog Reset<br />
• GPIO Reset<br />
• Sleep Mode<br />
The following sections give the timing <strong>and</strong> other specifications for the entry <strong>and</strong> exit of these<br />
modes.<br />
8.5.1 Power Supply Connectivity<br />
The <strong>PXA250</strong> applications processor requires two or three externally-supplied voltage levels.<br />
VCCQ requires high voltage, VCCN requires high or medium voltage, <strong>and</strong> VCC <strong>and</strong> PLL_VCC<br />
require low voltage. PLL_VCC must be separated from other low voltage supplies. Depending on<br />
the availability of independent regulator outputs <strong>and</strong> the desired memory voltage, VCCQ may have<br />
to be separated from VCCN. VCCN does not have to be separated at the board level.<br />
Note:<br />
Shaded sections are not supported for the <strong>PXA210</strong> applications processor.<br />
Table 8-6. <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> VCCN vs. VCCQ (Sheet 1 of 6)<br />
Pin<br />
Pin<br />
Count<br />
Alt_fn<br />
1-(in)<br />
Alt_fn<br />
2-(in)<br />
Alt_fn<br />
1-(out)<br />
Alt_fn<br />
2-(out)<br />
Signal Description <strong>and</strong><br />
Comments<br />
Power<br />
Supply<br />
MA(25:0) 26 Main Memory Address Bus VCCN<br />
MD(31:16) 16 Main Memory Data Bus (high) VCCN<br />
MD(15:0) 16 Main Memory Data Bus (low) VCCN<br />
nOE 1 Main Memory Bus Output Enable VCCN<br />
nWE 1 Main Memory Bus Write Enable VCCN<br />
nSDRAS 1 Main Memory Bus RAS VCCN<br />
nSDCAS 1 Main Memory Bus CAS VCCN<br />
DQM(3:2) 2<br />
Main Memory Bus SDRAM byte<br />
selects<br />
VCCN<br />
8-6 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide