Intel PXA250 and PXA210 Applications Processors

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Power and Clocking Table 8-3. Power Consumption Specifications (Sheet 2 of 2) Symbol Description Min 1 Typical 1 Max 1 P VCCN_HB @2.5V P VCCN_HB @3.3V Power from VCCN Supply, High Range (PXA250 applications processor) Power from VCCN Supply, High Range (PXA250 applications processor) — 115 mW 250 mW — 160 mW 440 mW PT_IDLE_H Total Power, IDLE Mode, High Range — 135mW — Peak Voltage Range (PXA250 applications processor only) P T_P Total Power, Peak Range — 635 mW 950 mW P VCC_P Power from VCC Supply, Peak Range — 470 mW 360 mW P VCCN_P @2.5V P VCCN_P @3.3V Power from VCCN Supply, Peak Range — 115 mW 255 mW Power from VCCN Supply, Peak Range — 160 mW 440 mW PT_IDLE_H Total Power, IDLE Mode, High Range — 185mW — NOTE: 1. These numbers are pre-silicon estimates, and will be replaced with the correct values when characterization is complete. 8.4 Oscillator Electrical Specifications The applications processor contains two oscillators – 32.768 kHz and 3.6864 MHz; each chosen for a specific crystal. When choosing a crystal, match the crystal parameters as closely as possible. 8.4.1 32.768 kHz Oscillator Specifications The 32.768 kHz Oscillator is connected between the TXTAL (amplifier input) and TEXTAL (amplified output). The 32.768 kHz specifications are shown in Table 8-4. Table 8-4. 32.768 kHz Oscillator Specifications (Sheet 1 of 2) Symbol Description Min Typical Max Crystal Specifications - Typical is FOX NC38 F XT Crystal Frequency, TXTAL/TEXTAL — 32.768 kHz — L MT Motional Inductance, TXTAL/TEXTAL — 6827.81 H — C MT Motional Capacitance, TXTAL/TEXTAL — 3.455 fF — R MT Motional Resistance, TXTAL/TEXTAL 6kΩ 16 kΩ 35 kΩ C OT Shunt Capacitance TXTAL to TEXTAL — 1.6 pF — C LT Load Capacitance TXTAL/TEXTAL — 12.5 pF — Amplifier Specifications V IH_X Input High Voltage, TXTAL 0.8 V*VCC — VCC V IL_X Input Low Voltage, TXTAL VSS — 0.2 V*VCC I IN_XT Input Leakage, TXTAL — — 1 µA C IN_XT Input Capacitance, TXTAL/TEXTAL — 18 pF 25 pF 8-4 PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking Table 8-4. 32.768 kHz Oscillator Specifications (Sheet 2 of 2) Symbol Description Min Typical Max t S_XT Stabilization Time 2s — 10 s Board Specifications R P_XT Parasitic Resistance, TXTAL/TEXTAL to any node 20 MΩ — — C P_XT Parasitic Capacitance, TXTAL/TEXTAL, total — — 5pF C OP_XT Parasitic Shunt Capacitance, TXTAL to TEXTAL — — 0.4 pF To drive the 32.768 kHz crystal pins from an external source: • Drive the TEXTAL pin with a digital signal that has a low level near 0 V and a high level near VCC. Do not exceed VCC or go below VSS by more than 100 mV. The minimum slew rate is 1V per µs. The maximum current drawn by the external clock source when the clock is at its maximum positive voltage should be about 1mA. • Float the TXTAL pin or drive it complementary to the TEXTAL pin, using the same voltage level, slew rate, and input current restrictions. 8.4.2 3.6864 MHz Oscillator Specifications The 3.6864 MHz Oscillator is connected between the PXTAL (amplifier input) and PEXTAL (amplified output). The 3.6864 MHz specifications are shown in Table 8-5 Table 8-5. 3.6864 MHz Oscillator Specifications Symbol Description Min Typical Max Crystal Specifications - Typical is FOX HC49S F XP Crystal Frequency, PXTAL/PEXTAL — 3.6864 MHz — L MP Motional Inductance, PXTAL/PEXTAL — 0.50593 H — C MP Motional Capacitance, PXTAL/PEXTAL — 3.68488 fF — R MP Motional Resistance, PXTAL/PEXTAL 50 Ω 99.3 Ω 200 Ω C OP Shunt Capacitance PXTAL to PEXTAL — 1.7 pF — C LP Load Capacitance PXTAL/PEXTAL — 20 pF — Amplifier Specifications V IH_X Input High Voltage, PXTAL 0.8V*VCC — VCC V IL_X Input Low Voltage, PXTAL VSS — 0.2 V*VCC I IN_XP Input Leakage, PXTAL — — 10 µA C IN_XP Input Capacitance, PXTAL/PEXTAL — 40 pF 50 pF t S_XP Stabilization Time 17.8 ms — 67.8 ms Board Specifications R P_XP Parasitic Resistance, PXTAL/PEXTAL to any node 20 MΩ — — C P_XP Parasitic Capacitance, PXTAL/PEXTAL, total — — 5pF C OP_XP Parasitic Shunt Capacitance, PXTAL to PEXTAL — — 0.4 pF To drive the 3.6864 MHz crystal pins from an external source: PXA250 and PXA210 Applications Processors Design Guide 8-5
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Intel ® PXA250 and PXA210 Applicat
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Contents Contents 1 Introduction...
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Contents A.1 SA-1110 Hardware Migra
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Contents 2-7 SRAM / ROM / Flash / S
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Introduction 1 Table 1-1. Revision
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Introduction • System memory inte
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Introduction Table 1-3. Signal Pin
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Introduction Figure 1-2. PXA250 App
Page 21 and 22: Introduction Table 1-4. PXA250 Appl
Page 23 and 24: Introduction Figure 1-3. PXA210 App
Page 25 and 26: Introduction Table 1-5. PXA210 Appl
Page 27 and 28: System Memory Interface 2 This sect
Page 29 and 30: System Memory Interface Table 2-1.
Page 31 and 32: . System Memory Interface 2.4 SDRAM
Page 39 and 40: System Memory Interface Figure 2-5.
Page 41 and 42: System Memory Interface Figure 2-6.
Page 43 and 44: System Memory Interface 2.7 System
Page 45 and 46: LCD Display Controller 3 This chapt
Page 47 and 48: LCD Display Controller Figure 3-1.
Page 49 and 50: LCD Display Controller Figure 3-5.
Page 51 and 52: LCD Display Controller Note: This e
Page 53 and 54: LCD Display Controller However, typ
Page 55 and 56: USB Interface 4 4.1 Self Powered De
Page 57 and 58: MultiMediaCard (MMC) 5 The MultiMed
Page 59 and 60: MultiMediaCard (MMC) Figure 5-1. Ap
Page 61 and 62: MultiMediaCard (MMC) Warning: Conne
Page 63 and 64: AC97 6 The AC97 controller unit (AC
Page 65 and 66: I 2 C 7 The Inter-Integrated Circui
Page 67 and 68: . I2C Figure 7-2. Using an Analog S
Page 69 and 70: Power and Clocking 8 8.1 Operating
Page 71: Power and Clocking Since few system
Page 75 and 76: Power and Clocking Table 8-6. PXA25
Page 81 and 82: Power and Clocking Figure 8-2. Hard
Page 83 and 84: Power and Clocking Table 8-10. Slee
Page 85 and 86: Power and Clocking Table 8-14. Sync
Page 87 and 88: Power and Clocking Table 8-16. Vari
Page 89 and 90: Power and Clocking • Provide powe
Page 91 and 92: Power and Clocking 8.7.4 I/O 3.3 V
Page 93 and 94: JTAG/Debug Port 9 9.1 Description T
Page 95 and 96: SA-1110/Applications Processor Migr
Page 105 and 106: Example Form Factor Reference Desig
Page 107 and 108: 8 1 7 6 5 4 3 2 Copyright 2002 Inte
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Page 117 and 118: 8 IN_PWR {10,15} D10 1 Pg. 12 7 6 5
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Page 121 and 122: 8 B B A A PXA250 Processor Referenc
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BBPXA2xx Development Baseboard Sche
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BBPXA2xx Development Baseboard Sche
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DCPXA250 Processor Card 32-bit vers
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DCPXA210 Processor Card 4 CONNECTOR
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Intel PXA250 and PXA210 Applications Processors

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