Intel PXA250 and PXA210 Applications Processors

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Contents Figures 1-1 Applications Processor Block Diagram......................................................................................1-2 1-2 PXA250 Applications Processor..............................................................................................1-11 1-3 PXA210 Applications Processor..............................................................................................1-15 2-1 General Memory Interface Configuration ..................................................................................2-2 2-2 SDRAM Memory System Example............................................................................................2-4 2-3 32-Bit Variable Latency I/O Read Timing (Burst-of-Four, One Wait Cycle Per Beat)..............2-10 2-4 Expansion Card External Logic for a Two-Socket Configuration.............................................2-12 2-5 Expansion Card External Logic for a One-Socket Configuration.............................................2-13 2-6 Alternate Bus Master Mode .....................................................................................................2-15 2-7 Variable Latency I/O ................................................................................................................2-16 2-8 CS, CKE, DQM, CLK, MA minimum loading topology.............................................................2-17 2-9 CS, CKE, DQM, CLK, MA Maximum Loading Topology .........................................................2-17 2-10MD Minimum Loading Topology..............................................................................................2-17 2-11MD maximum loading topology ...............................................................................................2-18 3-1 Single Panel Monochrome Passive Display Typical Connection ..............................................3-3 3-2 Passive Monochrome Single Panel Displays, Double-Pixel Data Typical Connection..............3-3 3-3 Passive Monochrome Dual Panel Displays Typical Connection ...............................................3-4 3-4 Passive Color Single Panel Displays Typical Connection .........................................................3-4 3-5 Passive Color Dual Panel Displays Typical Connection............................................................3-5 3-6 Active Color Display Typical Connection...................................................................................3-7 4-1 Self Powered Device .................................................................................................................4-1 5-1 Applications Processor MMC and SDCard Signal Connections................................................5-3 5-2 Applications Processor MMC to SDCard Simplified Signal Connection....................................5-5 6-1 AC97 connection .......................................................................................................................6-1 7-1 Linear Technology DAC with I2C Interface ...............................................................................7-2 7-2 Using an Analog Switch to Allow a Second CF Card ................................................................7-3 7-3 I 2 C Pull-Ups and Pull-Downs.....................................................................................................7-3 8-1 Power-On Reset Timing ..........................................................................................................8-12 8-2 Hardware Reset Timing...........................................................................................................8-13 8-3 GPIO Reset Timing .................................................................................................................8-13 8-4 Sleep Mode Timing..................................................................................................................8-14 8-5 Example Form Factor Reference Design Power System Design............................................8-22 9-1 JTAG/Debug Port Wiring Diagram ............................................................................................9-1 Tables 1-1 Revision History.........................................................................................................................1-1 1-2 Related Documentation .............................................................................................................1-1 1-3 Signal Pin Descriptions..............................................................................................................1-4 1-4 PXA250 Applications Processor Pinout — Ballpad Number Order .........................................1-12 1-5 PXA210 Applications Processor Pinout — Ballpad Number Order .........................................1-16 2-1 Memory Address Map ...............................................................................................................2-3 2-2 SDRAM Memory Types Supported by the Applications Processor...........................................2-5 2-3 Normal Mode Memory Address Mapping ..................................................................................2-6 2-4 Applications Processor Compatibility Mode Address Line Mapping..........................................2-7 2-5 Valid Booting Configurations Based on Package Type .............................................................2-8 2-6 BOOT_SEL Definitions..............................................................................................................2-8 vi PXA250 and PXA210 Applications Processors Design Guide
Contents 2-7 SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications ..........................................2-9 2-8 Variable Latency I/O Interface AC Specifications ....................................................................2-10 2-9 Card Interface (PCMCIA or Compact Flash) AC Specifications ..............................................2-13 2-10Minimum and Maximum Trace Lengths for the SDRAM Signals.............................................2-18 3-1 LCD Controller Data Pin Utilization............................................................................................3-1 3-2 Passive Display Pins Required..................................................................................................3-2 3-3 Active Display Pins Required.....................................................................................................3-6 3-4 PXA250 LCD Controller Ball Positions ......................................................................................3-7 5-1 MMC Signal Description ............................................................................................................5-1 5-2 SDCard Socket Signals .............................................................................................................5-2 5-3 MMC Controller Supported Sockets and Devices .....................................................................5-2 5-4 SDCard Pull-up and Pull-down Resistors ..................................................................................5-6 5-5 MMC Pull-up and Pull-down Resistors ......................................................................................5-6 7-1 I2C Signal Description ...............................................................................................................7-1 8-1 Voltage, Temperature, and Frequency Electrical Specifications ...............................................8-1 8-2 Absolute Maximum Ratings .......................................................................................................8-2 8-3 Power Consumption Specifications ...........................................................................................8-3 8-4 32.768 kHz Oscillator Specifications .........................................................................................8-4 8-5 3.6864 MHz Oscillator Specifications ........................................................................................8-5 8-6 PXA250 and PXA210 VCCN vs. VCCQ ....................................................................................8-6 8-7 Power-On Timing Specifications..............................................................................................8-12 8-8 Hardware Reset Timing Specifications....................................................................................8-13 8-9 GPIO Reset Timing Specifications ..........................................................................................8-14 8-10Sleep Mode Timing Specifications...........................................................................................8-14 8-11SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications (3.3 V) ............................8-15 8-12Variable Latency I/O Interface AC Specifications (3.3 V) ........................................................8-16 8-13Card Interface (PCMCIA or Compact Flash) AC Specifications (3.3 V) ..................................8-16 8-14Synchronous Memory Interface AC Specifications (3.3 V)......................................................8-17 8-15SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications (2.5 V) ............................8-18 8-16Variable Latency I/O Interface AC Specifications (2.5 V) ........................................................8-19 8-17Card Interface (PCMCIA or Compact Flash) AC Specifications (2.5 V) ..................................8-19 8-18Synchronous Memory Interface AC Specifications (2.5 V)......................................................8-20 PXA250 and PXA210 Applications Processors Design Guide vii
Page 1 and 2: Intel ® PXA250 and PXA210 Applicat
Page 3 and 4: Contents Contents 1 Introduction...
Page 5: Contents A.1 SA-1110 Hardware Migra
Page 9 and 10: Introduction 1 Table 1-1. Revision
Page 11 and 12: Introduction • System memory inte
Page 13 and 14: Introduction Table 1-3. Signal Pin
Page 19 and 20: Introduction Figure 1-2. PXA250 App
Page 21 and 22: Introduction Table 1-4. PXA250 Appl
Page 23 and 24: Introduction Figure 1-3. PXA210 App
Page 25 and 26: Introduction Table 1-5. PXA210 Appl
Page 27 and 28: System Memory Interface 2 This sect
Page 29 and 30: System Memory Interface Table 2-1.
Page 31 and 32: . System Memory Interface 2.4 SDRAM
Page 39 and 40: System Memory Interface Figure 2-5.
Page 41 and 42: System Memory Interface Figure 2-6.
Page 43 and 44: System Memory Interface 2.7 System
Page 45 and 46: LCD Display Controller 3 This chapt
Page 47 and 48: LCD Display Controller Figure 3-1.
Page 49 and 50: LCD Display Controller Figure 3-5.
Page 51 and 52: LCD Display Controller Note: This e
Page 53 and 54: LCD Display Controller However, typ
Page 55 and 56: USB Interface 4 4.1 Self Powered De
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MultiMediaCard (MMC) 5 The MultiMed
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MultiMediaCard (MMC) Figure 5-1. Ap
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MultiMediaCard (MMC) Warning: Conne
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AC97 6 The AC97 controller unit (AC
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I 2 C 7 The Inter-Integrated Circui
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. I2C Figure 7-2. Using an Analog S
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Power and Clocking 8 8.1 Operating
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Power and Clocking Since few system
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Power and Clocking Table 8-4. 32.76
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Power and Clocking Table 8-6. PXA25
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Power and Clocking Figure 8-2. Hard
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Power and Clocking Table 8-10. Slee
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Power and Clocking Table 8-14. Sync
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Power and Clocking Table 8-16. Vari
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Power and Clocking • Provide powe
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Power and Clocking 8.7.4 I/O 3.3 V
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JTAG/Debug Port 9 9.1 Description T
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SA-1110/Applications Processor Migr
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Example Form Factor Reference Desig
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8 1 7 6 5 4 3 2 Copyright 2002 Inte
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8 1 Sheet 4 of 16 1 7 6 5 4 3 2 Cop
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8 1 Sheet 6 of 16 1 7 6 5 4 3 2 Cop
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8 1 Sheet 8 of 16 1 7 6 5 4 3 2 Cop
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8 1 Sheet 10 of 16 1 7 6 5 4 3 2 Co
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8 IN_PWR {10,15} D10 1 Pg. 12 7 6 5
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8 C C 1 7 6 5 4 3 2 Copyright 2002
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8 B B A A PXA250 Processor Referenc
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BBPXA2xx Development Baseboard Sche
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BBPXA2xx Development Baseboard Sche
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DCPXA250 Processor Card 32-bit vers
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DCPXA210 Processor Card 4 CONNECTOR
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