Intel PXA250 and PXA210 Applications Processors
Intel PXA250 and PXA210 Applications Processors Intel PXA250 and PXA210 Applications Processors
I2C The actual value of the pull-up is system dependant and a guide is presented in the I 2 C Bus Specification on determining the maximum and minimum resistors to use when the system is intended for standard or fast-mode I 2 C bus devices. 7.2 Utilized Features The applications processor I 2 C bus interface unit is compatible with the two pin interface developed by Phillips Corporation. A complete list of features and capabilities can be found in the I 2 C Bus Specification. 7-4 PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking 8 8.1 Operating Conditions Table 8-1 shows voltage, frequency, and temperature specifications for the applications processor for four different ranges. The temperature specification for each range is constant; the frequency range is operation voltage dependent. On a prototype design, the VCC/PLL_VCC regulator should have a range from 0.85 V to 1.65 V. PLL_VCC and VCC must be connected together on the board or driven by the same supply. Table 8-1. Voltage, Temperature, and Frequency Electrical Specifications Symbol Description Min Typical Max t A Ambient Temperature -40°C — 85° C V VSS VSS, VSSN, VSSQ Voltage -0.3 V 0V 0.3 V V VCCQ VCCQ 3.0 V 3.3 V 3.6 V V VCCN_H VCCN @ 3.3V 3.0 V 3.3 V 3.6 V V VCCN_L VCCN @ 2.5V 2.375 V 2.5 V 2.625 V Low Voltage Range (PXA210 and PXA250) V VCC_L VCC, PLL_VCC Voltage, Low Range 0.8075 V 0.85 V 0.935 V f TURBO_L Turbo Mode Frequency, Low Range 99.5 MHz — 132.7 MHz f SDRAM_L External Synchronous Memory Frequency, Low Range — — 66.4 MHz Medium Voltage Range (PXA250 and PXA210) V VCC_M VCC, PLL_VCC Voltage, Mid Range 0.9 V 1.0 V 1.1 V f TURBO_M Turbo Mode Frequency, Mid Range 99.5 MHz — 199.1 MHz f SDRAM_M External Synchronous Memory Frequency, Mid Range — — 99.5 MHz High Voltage Range (PXA250 applications processor only) V VCC_H VCC, PLL_VCC Voltage, High Range 1.0 V 1.1 V 1.21 V f TURBO_H Turbo Mode Frequency, High Range 99.5 MHz — 298.7 MHz f SDRAM_H External Synchronous Memory Frequency, High Range — — 99.5 MHz Peak Voltage Range (PXA250 applications processor only) V VCC_P VCC, PLL_VCC Voltage, Peak Range 1.17 V 1.3 V 1.43 V f TURBO_P Turbo Mode Frequency, Peak Range 99.5 MHz — 398.2 MHz f SDRAM_P External Synchronous Memory Frequency, Peak Range — — 99.5 MHz NOTE: When VCCN=2.5 V, the I/O signals that are supplied by VCCN are 2.5 V tolerant only. Do not apply 3.3 V to any pin supplied by VCCN in this case. PXA250 and PXA210 Applications Processors Design Guide 8-1
- Page 17 and 18: Introduction Table 1-3. Signal Pin
- Page 19 and 20: Introduction Figure 1-2. PXA250 App
- Page 21 and 22: Introduction Table 1-4. PXA250 Appl
- Page 23 and 24: Introduction Figure 1-3. PXA210 App
- Page 25 and 26: Introduction Table 1-5. PXA210 Appl
- Page 27 and 28: System Memory Interface 2 This sect
- Page 29 and 30: System Memory Interface Table 2-1.
- Page 31 and 32: . System Memory Interface 2.4 SDRAM
- Page 33 and 34: System Memory Interface Table 2-4.
- Page 35 and 36: System Memory Interface Table 2-6.
- Page 37 and 38: System Memory Interface Table 2-8.
- Page 39 and 40: System Memory Interface Figure 2-5.
- Page 41 and 42: System Memory Interface Figure 2-6.
- Page 43 and 44: System Memory Interface 2.7 System
- Page 45 and 46: LCD Display Controller 3 This chapt
- Page 47 and 48: LCD Display Controller Figure 3-1.
- Page 49 and 50: LCD Display Controller Figure 3-5.
- Page 51 and 52: LCD Display Controller Note: This e
- Page 53 and 54: LCD Display Controller However, typ
- Page 55 and 56: USB Interface 4 4.1 Self Powered De
- Page 57 and 58: MultiMediaCard (MMC) 5 The MultiMed
- Page 59 and 60: MultiMediaCard (MMC) Figure 5-1. Ap
- Page 61 and 62: MultiMediaCard (MMC) Warning: Conne
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- Page 65 and 66: I 2 C 7 The Inter-Integrated Circui
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- Page 71 and 72: Power and Clocking Since few system
- Page 73 and 74: Power and Clocking Table 8-4. 32.76
- Page 75 and 76: Power and Clocking Table 8-6. PXA25
- Page 77 and 78: Power and Clocking Table 8-6. PXA25
- Page 79 and 80: Power and Clocking Table 8-6. PXA25
- Page 81 and 82: Power and Clocking Figure 8-2. Hard
- Page 83 and 84: Power and Clocking Table 8-10. Slee
- Page 85 and 86: Power and Clocking Table 8-14. Sync
- Page 87 and 88: Power and Clocking Table 8-16. Vari
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- Page 91 and 92: Power and Clocking 8.7.4 I/O 3.3 V
- Page 93 and 94: JTAG/Debug Port 9 9.1 Description T
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I2C<br />
The actual value of the pull-up is system dependant <strong>and</strong> a guide is presented in the I 2 C Bus<br />
Specification on determining the maximum <strong>and</strong> minimum resistors to use when the system is<br />
intended for st<strong>and</strong>ard or fast-mode I 2 C bus devices.<br />
7.2 Utilized Features<br />
The applications processor I 2 C bus interface unit is compatible with the two pin interface<br />
developed by Phillips Corporation. A complete list of features <strong>and</strong> capabilities can be found in the<br />
I 2 C Bus Specification.<br />
7-4 <strong>PXA250</strong> <strong>and</strong> <strong>PXA210</strong> <strong>Applications</strong> <strong>Processors</strong> Design Guide
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